* [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
@ 2021-09-17 20:52 José Roberto de Souza
2021-09-17 20:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe José Roberto de Souza
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: José Roberto de Souza @ 2021-09-17 20:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Imre Deak, Gwan-gyeong Mun, José Roberto de Souza
Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all
platforms that supports DMC, not only for geminilake and broxton.
While at is also taking the oportunity to simply the code.
BSpec: 7402
BSpec: 49436
Cc: Imre Deak <imre.deak@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index b0268552b2863..2dc9d632969db 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -255,20 +255,10 @@ intel_get_stepping_info(struct drm_i915_private *i915,
static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
{
- u32 val, mask;
-
- mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
-
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- mask |= DC_STATE_DEBUG_MASK_CORES;
-
/* The below bit doesn't need to be cleared ever afterwards */
- val = intel_de_read(dev_priv, DC_STATE_DEBUG);
- if ((val & mask) != mask) {
- val |= mask;
- intel_de_write(dev_priv, DC_STATE_DEBUG, val);
- intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
- }
+ intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
+ DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
+ intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
}
/**
--
2.33.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe
2021-09-17 20:52 [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load José Roberto de Souza
@ 2021-09-17 20:52 ` José Roberto de Souza
2021-09-23 13:27 ` Gwan-gyeong Mun
2021-09-17 20:52 ` [Intel-gfx] [PATCH 3/3] drm/i915/display: Match PSR2 selective fetch sequences with specification José Roberto de Souza
` (4 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: José Roberto de Souza @ 2021-09-17 20:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Gwan-gyeong Mun, José Roberto de Souza
Alderlake-P was getting 'max time under evasion' messages when PSR2
was enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
period of time longer than VBLANK_EVASION_TIME_US.
For PSR1 we had the same issue so intel_psr_wait_for_idle() was
implemented to wait for PSR1 to get into idle state but nothing was
done for PSR2.
For PSR2 we can't only wait for idle state as PSR2 tends to keep
into sleep state that means it is ready to send selective updates.
To do so it was necessary to add intel_wait_for_condition(), this
takes as parameter a function that will return true when the desidered
condition is meet.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 3 +-
drivers/gpu/drm/i915/display/intel_psr.c | 64 ++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 5 +-
drivers/gpu/drm/i915/intel_uncore.c | 47 ++++++++++++++
drivers/gpu/drm/i915/intel_uncore.h | 7 ++
5 files changed, 100 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 68f4ba8c46e75..662596adb1da6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -303,8 +303,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
};
val = intel_de_read(dev_priv,
EDP_PSR2_STATUS(intel_dp->psr.transcoder));
- status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
- EDP_PSR2_STATUS_STATE_SHIFT;
+ status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
if (status_val < ARRAY_SIZE(live_status))
status = live_status[status_val];
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c1894b056d6c1..bd13325782f11 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1763,15 +1763,33 @@ void intel_psr_update(struct intel_dp *intel_dp,
mutex_unlock(&intel_dp->psr.lock);
}
-/**
- * psr_wait_for_idle - wait for PSR1 to idle
- * @intel_dp: Intel DP
- * @out_value: PSR status in case of failure
- *
- * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
- *
- */
-static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
+static bool _is_psr2_read_for_pipe_update(void *data)
+{
+ struct intel_dp *intel_dp = data;
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 val;
+
+ val = intel_uncore_read_fw(&dev_priv->uncore,
+ EDP_PSR2_STATUS(intel_dp->psr.transcoder));
+ val &= EDP_PSR2_STATUS_STATE_MASK;
+
+ return val == EDP_PSR2_STATUS_STATE_SLEEP || val == EDP_PSR2_STATUS_STATE_IDLE;
+}
+
+static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ unsigned int fw;
+
+ fw = intel_uncore_forcewake_for_reg(&dev_priv->uncore,
+ EDP_PSR2_STATUS(intel_dp->psr.transcoder),
+ FW_REG_READ);
+ return intel_wait_for_condition(&dev_priv->uncore,
+ _is_psr2_read_for_pipe_update,
+ intel_dp, fw, 50);
+}
+
+static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1781,15 +1799,13 @@ static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
* exit training time + 1.5 ms of aux channel handshake. 50 ms is
* defensive enough to cover everything.
*/
- return __intel_wait_for_register(&dev_priv->uncore,
- EDP_PSR_STATUS(intel_dp->psr.transcoder),
- EDP_PSR_STATUS_STATE_MASK,
- EDP_PSR_STATUS_STATE_IDLE, 2, 50,
- out_value);
+ return intel_de_wait_for_clear(dev_priv,
+ EDP_PSR_STATUS(intel_dp->psr.transcoder),
+ EDP_PSR_STATUS_STATE_MASK, 50);
}
/**
- * intel_psr_wait_for_idle - wait for PSR1 to idle
+ * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
* @new_crtc_state: new CRTC state
*
* This function is expected to be called from pipe_update_start() where it is
@@ -1806,19 +1822,23 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
new_crtc_state->uapi.encoder_mask) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- u32 psr_status;
+ int ret;
mutex_lock(&intel_dp->psr.lock);
- if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) {
+
+ if (!intel_dp->psr.enabled) {
mutex_unlock(&intel_dp->psr.lock);
continue;
}
- /* when the PSR1 is enabled */
- if (psr_wait_for_idle(intel_dp, &psr_status))
- drm_err(&dev_priv->drm,
- "PSR idle timed out 0x%x, atomic update may fail\n",
- psr_status);
+ if (intel_dp->psr.psr2_enabled)
+ ret = _psr2_ready_for_pipe_update_locked(intel_dp);
+ else
+ ret = _psr1_ready_for_pipe_update_locked(intel_dp);
+
+ if (ret)
+ drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
+
mutex_unlock(&intel_dp->psr.lock);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3a21f7c003de..7aaa0bc9a8fe7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4698,8 +4698,9 @@ enum {
#define _PSR2_STATUS_A 0x60940
#define _PSR2_STATUS_EDP 0x6f940
#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
-#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
-#define EDP_PSR2_STATUS_STATE_SHIFT 28
+#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
+#define EDP_PSR2_STATUS_STATE_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x3)
+#define EDP_PSR2_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x0)
#define _PSR2_SU_STATUS_A 0x60914
#define _PSR2_SU_STATUS_EDP 0x6f914
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f9767054dbdf9..1467b7709ca3a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2379,6 +2379,28 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
#undef done
}
+static int __intel_wait_for_condition_fw(bool (*func)(void *data), void *data,
+ unsigned int fast_timeout_us,
+ unsigned int slow_timeout_ms)
+{
+#define done (func(data))
+ int ret;
+
+ /* Catch any overuse of this function */
+ might_sleep_if(slow_timeout_ms);
+ GEM_BUG_ON(fast_timeout_us > 20000);
+ GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
+
+ ret = -ETIMEDOUT;
+ if (fast_timeout_us && fast_timeout_us <= 20000)
+ ret = _wait_for_atomic(done, fast_timeout_us, 0);
+ if (ret && slow_timeout_ms)
+ ret = wait_for(done, slow_timeout_ms);
+
+ return ret;
+#undef done
+}
+
/**
* __intel_wait_for_register - wait until register matches expected state
* @uncore: the struct intel_uncore
@@ -2438,6 +2460,31 @@ int __intel_wait_for_register(struct intel_uncore *uncore,
return ret;
}
+int intel_wait_for_condition(struct intel_uncore *uncore,
+ bool (*func)(void *data),
+ void *data,
+ unsigned int fw,
+ unsigned int slow_timeout_ms)
+{
+ unsigned int fast_timeout_us = 2;
+ int ret;
+
+ might_sleep_if(slow_timeout_ms);
+
+ spin_lock_irq(&uncore->lock);
+ intel_uncore_forcewake_get__locked(uncore, fw);
+
+ ret = __intel_wait_for_condition_fw(func, data, fast_timeout_us, 0);
+
+ intel_uncore_forcewake_put__locked(uncore, fw);
+ spin_unlock_irq(&uncore->lock);
+
+ if (ret && slow_timeout_ms)
+ ret = __wait_for(, (func(data)), slow_timeout_ms * 1000, 10, 1000);
+
+ return ret;
+}
+
bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
{
bool ret;
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 531665b08039c..e3041525a6db8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -275,6 +275,7 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
unsigned int fast_timeout_us,
unsigned int slow_timeout_ms,
u32 *out_value);
+
static inline int
intel_wait_for_register_fw(struct intel_uncore *uncore,
i915_reg_t reg,
@@ -286,6 +287,12 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
2, timeout_ms, NULL);
}
+int intel_wait_for_condition(struct intel_uncore *uncore,
+ bool (*func)(void *data),
+ void *data,
+ unsigned int fw,
+ unsigned int timeout_ms);
+
/* register access functions */
#define __raw_read(x__, s__) \
static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
--
2.33.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/display: Match PSR2 selective fetch sequences with specification
2021-09-17 20:52 [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load José Roberto de Souza
2021-09-17 20:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe José Roberto de Souza
@ 2021-09-17 20:52 ` José Roberto de Souza
2021-09-20 18:12 ` Gwan-gyeong Mun
2021-09-17 21:05 ` [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load Imre Deak
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: José Roberto de Souza @ 2021-09-17 20:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Gwan-gyeong Mun, José Roberto de Souza
We were not completely following the selective fetch programming
sequence, here some things we were doing wrong:
- not programming plane selective fetch a PSR2_MAN_TRK_CTL registers
when doing a modeset
- programming PSR2_MAN_TRK_CTL out of vblank
With this changes the last remainig underrun found in Alderlake-P is
fixed.
Bspec: 55229
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 4 ++-
drivers/gpu/drm/i915/display/intel_display.c | 12 +++----
drivers/gpu/drm/i915/display/intel_psr.c | 33 ++++++++++++++-----
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
.../drm/i915/display/skl_universal_plane.c | 4 +--
5 files changed, 36 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index c7618fef01439..901ad3a4c8c3b 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -536,8 +536,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
if (DISPLAY_VER(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
- if (!intel_crtc_needs_modeset(crtc_state))
+ if (plane_state)
intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
+ else
+ intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
if (plane->cursor.base != base ||
plane->cursor.size != fbc_ctl ||
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f6c0c595f6313..224bf622a1c1a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6812,11 +6812,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
}
- if (!mode_changed) {
- ret = intel_psr2_sel_fetch_update(state, crtc);
- if (ret)
- return ret;
- }
+ ret = intel_psr2_sel_fetch_update(state, crtc);
+ if (ret)
+ return ret;
return 0;
}
@@ -9709,10 +9707,10 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
if (new_crtc_state->update_pipe)
intel_pipe_fastset(old_crtc_state, new_crtc_state);
-
- intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
}
+ intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
+
if (dev_priv->display.atomic_update_watermarks)
dev_priv->display.atomic_update_watermarks(state, crtc);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index bd13325782f11..101a23bdd7b5b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -561,15 +561,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_SU_SDP_SCANLINE;
if (intel_dp->psr.psr2_sel_fetch_enabled) {
+ u32 tmp;
+
/* Wa_1408330847 */
if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
DIS_RAM_BYPASS_PSR2_MAN_TRACK,
DIS_RAM_BYPASS_PSR2_MAN_TRACK);
- intel_de_write(dev_priv,
- PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
- PSR2_MAN_TRK_CTL_ENABLE);
+ tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
+ drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
intel_de_write(dev_priv,
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
@@ -1450,6 +1451,18 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
}
+void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+
+ if (!crtc_state->enable_psr2_sel_fetch)
+ return;
+
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+}
+
void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
@@ -1464,11 +1477,11 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
- val = plane_state ? plane_state->ctl : 0;
- val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
- if (!val || plane->id == PLANE_CURSOR)
+ if (plane->id == PLANE_CURSOR) {
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
+ plane_state->ctl);
return;
+ }
clip = &plane_state->psr2_sel_fetch_area;
@@ -1487,14 +1500,16 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
val = (drm_rect_height(clip) - 1) << 16;
val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
+
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
+ PLANE_SEL_FETCH_CTL_ENABLE);
}
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (!HAS_PSR2_SEL_FETCH(dev_priv) ||
- !crtc_state->enable_psr2_sel_fetch)
+ if (!crtc_state->enable_psr2_sel_fetch)
return;
intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 641521b101c82..e502964697c62 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -51,6 +51,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
int color_plane);
+void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state);
void intel_psr_pause(struct intel_dp *intel_dp);
void intel_psr_resume(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 724e7b04f3b63..247155f2a5538 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -656,6 +656,7 @@ skl_disable_plane(struct intel_plane *plane,
skl_write_plane_wm(plane, crtc_state);
+ intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
@@ -1096,8 +1097,7 @@ skl_program_plane(struct intel_plane *plane,
(plane_state->view.color_plane[1].y << 16) |
plane_state->view.color_plane[1].x);
- if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
- intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
+ intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
/*
* Enable the scaler before the plane so that we don't
--
2.33.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
2021-09-17 20:52 [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load José Roberto de Souza
2021-09-17 20:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe José Roberto de Souza
2021-09-17 20:52 ` [Intel-gfx] [PATCH 3/3] drm/i915/display: Match PSR2 selective fetch sequences with specification José Roberto de Souza
@ 2021-09-17 21:05 ` Imre Deak
2021-09-20 19:06 ` Imre Deak
2021-09-17 21:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] " Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Imre Deak @ 2021-09-17 21:05 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Gwan-gyeong Mun
On Fri, Sep 17, 2021 at 01:52:39PM -0700, José Roberto de Souza wrote:
> Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all
> platforms that supports DMC, not only for geminilake and broxton.
According to the spec it's only required for BXT and GLK, see
Bspec 4234, 49193, 49194.
The register description is a bit vague, would need to be clarified
probably.
> While at is also taking the oportunity to simply the code.
>
> BSpec: 7402
> BSpec: 49436
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 16 +++-------------
> 1 file changed, 3 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index b0268552b2863..2dc9d632969db 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -255,20 +255,10 @@ intel_get_stepping_info(struct drm_i915_private *i915,
>
> static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> {
> - u32 val, mask;
> -
> - mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> -
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - mask |= DC_STATE_DEBUG_MASK_CORES;
> -
> /* The below bit doesn't need to be cleared ever afterwards */
> - val = intel_de_read(dev_priv, DC_STATE_DEBUG);
> - if ((val & mask) != mask) {
> - val |= mask;
> - intel_de_write(dev_priv, DC_STATE_DEBUG, val);
> - intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> - }
> + intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
> + DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
> + intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> }
>
> /**
> --
> 2.33.0
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
2021-09-17 20:52 [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load José Roberto de Souza
` (2 preceding siblings ...)
2021-09-17 21:05 ` [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load Imre Deak
@ 2021-09-17 21:14 ` Patchwork
2021-09-17 21:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-17 22:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2021-09-17 21:14 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
URL : https://patchwork.freedesktop.org/series/94819/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
2021-09-17 20:52 [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load José Roberto de Souza
` (3 preceding siblings ...)
2021-09-17 21:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] " Patchwork
@ 2021-09-17 21:37 ` Patchwork
2021-09-17 22:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2021-09-17 21:37 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8619 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
URL : https://patchwork.freedesktop.org/series/94819/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10605 -> Patchwork_21087
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21087:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {fi-jsl-1}: [TIMEOUT][1] ([i915#4136]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-jsl-1/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-jsl-1/igt@i915_module_load@reload.html
Known issues
------------
Here are the changes found in Patchwork_21087 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-cfl-8109u/igt@amdgpu/amd_basic@cs-sdma.html
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [PASS][4] -> [INCOMPLETE][5] ([i915#4130])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@core_hotunplug@unbind-rebind.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-skl-6700k2/igt@core_hotunplug@unbind-rebind.html
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][6] ([i915#4130])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@core_hotunplug@unbind-rebind.html
- fi-skl-guc: [PASS][7] -> [INCOMPLETE][8] ([i915#4130])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_module_load@reload:
- fi-rkl-11600: [PASS][10] -> [DMESG-WARN][11] ([i915#4136])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-rkl-11600/igt@i915_module_load@reload.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-rkl-11600/igt@i915_module_load@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([i915#1155])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#4103]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#109285])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#3301])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-tgl-1115g4: NOTRUN -> [FAIL][18] ([i915#1602] / [i915#2722])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-tgl-1115g4/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-8109u: [INCOMPLETE][19] ([i915#4130]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-kbl-7567u: [DMESG-WARN][21] ([i915#4136]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7567u/igt@i915_module_load@reload.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-kbl-7567u/igt@i915_module_load@reload.html
- fi-kbl-guc: [INCOMPLETE][23] ([i915#4139]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-guc/igt@i915_module_load@reload.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-kbl-guc/igt@i915_module_load@reload.html
#### Warnings ####
* igt@i915_module_load@reload:
- fi-kbl-8809g: [INCOMPLETE][25] ([i915#4136]) -> [INCOMPLETE][26] ([i915#4130])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-8809g/igt@i915_module_load@reload.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-kbl-8809g/igt@i915_module_load@reload.html
- fi-cml-u2: [INCOMPLETE][27] ([i915#4130] / [i915#4136]) -> [INCOMPLETE][28] ([i915#4136])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cml-u2/igt@i915_module_load@reload.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-cml-u2/igt@i915_module_load@reload.html
- fi-kbl-soraka: [INCOMPLETE][29] ([i915#4130] / [i915#4136]) -> [INCOMPLETE][30] ([i915#4136])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-soraka/igt@i915_module_load@reload.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/fi-kbl-soraka/igt@i915_module_load@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4130]: https://gitlab.freedesktop.org/drm/intel/issues/4130
[i915#4136]: https://gitlab.freedesktop.org/drm/intel/issues/4136
[i915#4139]: https://gitlab.freedesktop.org/drm/intel/issues/4139
Participating hosts (38 -> 32)
------------------------------
Additional (1): fi-tgl-1115g4
Missing (7): fi-ilk-m540 bat-dg1-6 fi-tgl-u2 fi-hsw-4200u fi-ctg-p8600 bat-jsl-2 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10605 -> Patchwork_21087
CI-20190529: 20190529
CI_DRM_10605: e61e36045f57a5aaeef91f54274937843ee3d0d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6211: 7b275b3eb17ddf6e7c5b7b9ba359b7f5345a5311 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21087: 2073d47be967f1f5a3ae2103f8cb85c0780c5a95 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2073d47be967 drm/i915/display: Match PSR2 selective fetch sequences with specification
d6400e4f4298 drm/i915/display: Wait PSR2 get out of deep sleep to update pipe
191f1179b625 drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/index.html
[-- Attachment #2: Type: text/html, Size: 10437 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
2021-09-17 20:52 [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load José Roberto de Souza
` (4 preceding siblings ...)
2021-09-17 21:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-09-17 22:50 ` Patchwork
5 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2021-09-17 22:50 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 27028 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
URL : https://patchwork.freedesktop.org/series/94819/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10605_full -> Patchwork_21087_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21087_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21087_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21087_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {shard-rkl}: ([FAIL][3], [FAIL][4], [FAIL][5]) ([i915#3002] / [i915#3811]) -> ([FAIL][6], [FAIL][7]) ([i915#3002])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-rkl-6/igt@runner@aborted.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-rkl-2/igt@runner@aborted.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-rkl-2/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-rkl-2/igt@runner@aborted.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-rkl-6/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_21087_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-reset-rebind:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#4130])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl1/igt@device_reset@unbind-reset-rebind.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl7/igt@device_reset@unbind-reset-rebind.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-iclb: [PASS][10] -> [TIMEOUT][11] ([i915#3070])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb3/igt@gem_eio@in-flight-contexts-immediate.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb1/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_eio@unwedge-stress:
- shard-skl: [PASS][12] -> [TIMEOUT][13] ([i915#2369] / [i915#3063])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl5/igt@gem_eio@unwedge-stress.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-skl: NOTRUN -> [WARN][18] ([i915#2658])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl4/igt@gem_pread@exhaustion.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271]) +63 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl4/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_suspend@debugfs-reader:
- shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#456])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb5/igt@i915_suspend@debugfs-reader.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-tglb3/igt@i915_suspend@debugfs-reader.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3777])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3886]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][24] ([fdo#109278] / [i915#3886])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb3/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +9 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-frame-dump:
- shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +4 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl10/igt@kms_chamelium@vga-frame-dump.html
* igt@kms_color@pipe-c-ctm-0-25:
- shard-skl: [PASS][27] -> [DMESG-WARN][28] ([i915#1982])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl8/igt@kms_color@pipe-c-ctm-0-25.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl9/igt@kms_color@pipe-c-ctm-0-25.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109278] / [fdo#109279]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb3/igt@kms_cursor_crc@pipe-a-cursor-512x512-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][30] ([i915#180]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109278]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb3/igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109274] / [fdo#109278])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy:
- shard-iclb: [PASS][33] -> [FAIL][34] ([i915#2346])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb2/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-skl: [PASS][35] -> [INCOMPLETE][36] ([i915#198] / [i915#1982])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl9/igt@kms_flip@flip-vs-suspend@a-edp1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl2/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [PASS][37] -> [FAIL][38] ([i915#2122])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [PASS][39] -> [SKIP][40] ([i915#3701])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271]) +7 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][42] -> [DMESG-WARN][43] ([i915#180]) +4 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109280])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#533])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-tglb: [PASS][46] -> [INCOMPLETE][47] ([i915#2828] / [i915#456])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][48] ([fdo#108145] / [i915#265]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#658]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][50] -> [SKIP][51] ([fdo#109441]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-iclb: NOTRUN -> [SKIP][52] ([i915#2530])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb1/igt@nouveau_crc@pipe-a-source-rg.html
* igt@sysfs_clients@recycle:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#2994]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl4/igt@sysfs_clients@recycle.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- shard-iclb: [INCOMPLETE][54] ([i915#4130]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb3/igt@core_hotunplug@unbind-rebind.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb1/igt@core_hotunplug@unbind-rebind.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [DMESG-WARN][56] ([i915#180]) -> [PASS][57] +3 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][58] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb8/igt@gem_eio@unwedge-stress.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [SKIP][60] ([fdo#109271]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][62] ([i915#2849]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@kms_color@pipe-b-ctm-green-to-red:
- shard-skl: [DMESG-WARN][64] ([i915#1982]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl3/igt@kms_color@pipe-b-ctm-green-to-red.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl4/igt@kms_color@pipe-b-ctm-green-to-red.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [FAIL][66] ([i915#79]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-skl: [INCOMPLETE][68] ([i915#146] / [i915#198]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl1/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][70] ([i915#1188]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-skl: [INCOMPLETE][72] ([i915#198] / [i915#2828]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][74] ([fdo#108145] / [i915#265]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][76] ([fdo#109441]) -> [PASS][77] +3 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][78] ([i915#1804] / [i915#2684]) -> [WARN][79] ([i915#2684])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: [FAIL][80] ([i915#3743]) -> [FAIL][81] ([i915#3722])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-skl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-skl6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-iclb: [SKIP][82] ([i915#658]) -> [SKIP][83] ([i915#2920]) +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb4/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][84], [FAIL][85], [FAIL][86], [FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][95], [FAIL][96], [FAIL][97], [FAIL][98], [FAIL][99], [FAIL][100], [FAIL][101], [FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl3/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl3/igt@runner@aborted.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl3/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl4/igt@runner@aborted.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl6/igt@runner@aborted.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl1/igt@runner@aborted.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl4/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl1/igt@runner@aborted.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl1/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl1/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl1/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl3/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/shard-kbl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2481]: https://gitlab.freedesktop.org/drm/intel/issues/2481
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2828]: https://gitlab.freedesktop.org/drm/intel/issues/2828
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3115]: https://gitlab.freedesktop.org/drm/intel/issues/3115
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3699]: https://gitlab.freedesktop.org/drm/intel/issues/3699
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3721]: https://gitlab.freedesktop.org/drm/intel/issues/3721
[i915#3722]: https://gitlab.freedesktop.org/drm/intel/issues/3722
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777
[i915#3811]: https://gitlab.freedesktop.org/drm/intel/issues/3811
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4130]: https://gitlab.freedesktop.org/drm/intel/issues/4130
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_10605 -> Patchwork_21087
CI-20190529: 20190529
CI_DRM_10605: e61e36045f57a5aaeef91f54274937843ee3d0d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6211: 7b275b3eb17ddf6e7c5b7b9ba359b7f5345a5311 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21087: 2073d47be967f1f5a3ae2103f8cb85c0780c5a95 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21087/index.html
[-- Attachment #2: Type: text/html, Size: 29607 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/display: Match PSR2 selective fetch sequences with specification
2021-09-17 20:52 ` [Intel-gfx] [PATCH 3/3] drm/i915/display: Match PSR2 selective fetch sequences with specification José Roberto de Souza
@ 2021-09-20 18:12 ` Gwan-gyeong Mun
0 siblings, 0 replies; 11+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-20 18:12 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx
Looks good to me.
Tested-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On 9/17/21 11:52 PM, José Roberto de Souza wrote:
> We were not completely following the selective fetch programming
> sequence, here some things we were doing wrong:
> - not programming plane selective fetch a PSR2_MAN_TRK_CTL registers
> when doing a modeset
> - programming PSR2_MAN_TRK_CTL out of vblank
>
> With this changes the last remainig underrun found in Alderlake-P is
> fixed.
>
> Bspec: 55229
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 4 ++-
> drivers/gpu/drm/i915/display/intel_display.c | 12 +++----
> drivers/gpu/drm/i915/display/intel_psr.c | 33 ++++++++++++++-----
> drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
> .../drm/i915/display/skl_universal_plane.c | 4 +--
> 5 files changed, 36 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index c7618fef01439..901ad3a4c8c3b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -536,8 +536,10 @@ static void i9xx_update_cursor(struct intel_plane *plane,
> if (DISPLAY_VER(dev_priv) >= 9)
> skl_write_cursor_wm(plane, crtc_state);
>
> - if (!intel_crtc_needs_modeset(crtc_state))
> + if (plane_state)
> intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
> + else
> + intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
>
> if (plane->cursor.base != base ||
> plane->cursor.size != fbc_ctl ||
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f6c0c595f6313..224bf622a1c1a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6812,11 +6812,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>
> }
>
> - if (!mode_changed) {
> - ret = intel_psr2_sel_fetch_update(state, crtc);
> - if (ret)
> - return ret;
> - }
> + ret = intel_psr2_sel_fetch_update(state, crtc);
> + if (ret)
> + return ret;
>
> return 0;
> }
> @@ -9709,10 +9707,10 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
>
> if (new_crtc_state->update_pipe)
> intel_pipe_fastset(old_crtc_state, new_crtc_state);
> -
> - intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> }
>
> + intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
> +
> if (dev_priv->display.atomic_update_watermarks)
> dev_priv->display.atomic_update_watermarks(state, crtc);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index bd13325782f11..101a23bdd7b5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -561,15 +561,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> val |= EDP_PSR2_SU_SDP_SCANLINE;
>
> if (intel_dp->psr.psr2_sel_fetch_enabled) {
> + u32 tmp;
> +
> /* Wa_1408330847 */
> if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> DIS_RAM_BYPASS_PSR2_MAN_TRACK);
>
> - intel_de_write(dev_priv,
> - PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> - PSR2_MAN_TRK_CTL_ENABLE);
> + tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> + drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
> } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> intel_de_write(dev_priv,
> PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
> @@ -1450,6 +1451,18 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
> }
>
> +void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> +
> + if (!crtc_state->enable_psr2_sel_fetch)
> + return;
> +
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
> +}
> +
> void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state,
> @@ -1464,11 +1477,11 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> if (!crtc_state->enable_psr2_sel_fetch)
> return;
>
> - val = plane_state ? plane_state->ctl : 0;
> - val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
> - if (!val || plane->id == PLANE_CURSOR)
> + if (plane->id == PLANE_CURSOR) {
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> + plane_state->ctl);
> return;
> + }
>
> clip = &plane_state->psr2_sel_fetch_area;
>
> @@ -1487,14 +1500,16 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> val = (drm_rect_height(clip) - 1) << 16;
> val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
> +
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> + PLANE_SEL_FETCH_CTL_ENABLE);
> }
>
> void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
> - if (!HAS_PSR2_SEL_FETCH(dev_priv) ||
> - !crtc_state->enable_psr2_sel_fetch)
> + if (!crtc_state->enable_psr2_sel_fetch)
> return;
>
> intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 641521b101c82..e502964697c62 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -51,6 +51,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state,
> int color_plane);
> +void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state);
> void intel_psr_pause(struct intel_dp *intel_dp);
> void intel_psr_resume(struct intel_dp *intel_dp);
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 724e7b04f3b63..247155f2a5538 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -656,6 +656,7 @@ skl_disable_plane(struct intel_plane *plane,
>
> skl_write_plane_wm(plane, crtc_state);
>
> + intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
> intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
>
> @@ -1096,8 +1097,7 @@ skl_program_plane(struct intel_plane *plane,
> (plane_state->view.color_plane[1].y << 16) |
> plane_state->view.color_plane[1].x);
>
> - if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> - intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
> + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
>
> /*
> * Enable the scaler before the plane so that we don't
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load
2021-09-17 21:05 ` [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load Imre Deak
@ 2021-09-20 19:06 ` Imre Deak
0 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2021-09-20 19:06 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Gwan-gyeong Mun
On Sat, Sep 18, 2021 at 12:06:01AM +0300, Imre Deak wrote:
> On Fri, Sep 17, 2021 at 01:52:39PM -0700, José Roberto de Souza wrote:
> > Specification asks for DC_STATE_DEBUG_MASK_CORES to be set for all
> > platforms that supports DMC, not only for geminilake and broxton.
>
> According to the spec it's only required for BXT and GLK, see
> Bspec 4234, 49193, 49194.
>
> The register description is a bit vague, would need to be clarified
> probably.
The spec got updated now for TGL+, thanks. Provided that you can
get the spec up-to-date for GEN9 platforms as well:
Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> > While at is also taking the oportunity to simply the code.
> >
> > BSpec: 7402
> > BSpec: 49436
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dmc.c | 16 +++-------------
> > 1 file changed, 3 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index b0268552b2863..2dc9d632969db 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -255,20 +255,10 @@ intel_get_stepping_info(struct drm_i915_private *i915,
> >
> > static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> > {
> > - u32 val, mask;
> > -
> > - mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
> > -
> > - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> > - mask |= DC_STATE_DEBUG_MASK_CORES;
> > -
> > /* The below bit doesn't need to be cleared ever afterwards */
> > - val = intel_de_read(dev_priv, DC_STATE_DEBUG);
> > - if ((val & mask) != mask) {
> > - val |= mask;
> > - intel_de_write(dev_priv, DC_STATE_DEBUG, val);
> > - intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> > - }
> > + intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0,
> > + DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP);
> > + intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
> > }
> >
> > /**
> > --
> > 2.33.0
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe
2021-09-17 20:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe José Roberto de Souza
@ 2021-09-23 13:27 ` Gwan-gyeong Mun
2021-09-23 17:25 ` Souza, Jose
0 siblings, 1 reply; 11+ messages in thread
From: Gwan-gyeong Mun @ 2021-09-23 13:27 UTC (permalink / raw)
To: José Roberto de Souza, intel-gfx
On 9/17/21 11:52 PM, José Roberto de Souza wrote:
> Alderlake-P was getting 'max time under evasion' messages when PSR2
> was enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
> period of time longer than VBLANK_EVASION_TIME_US.
>
> For PSR1 we had the same issue so intel_psr_wait_for_idle() was
> implemented to wait for PSR1 to get into idle state but nothing was
> done for PSR2.
>
> For PSR2 we can't only wait for idle state as PSR2 tends to keep
> into sleep state that means it is ready to send selective updates.
>
> To do so it was necessary to add intel_wait_for_condition(), this
> takes as parameter a function that will return true when the desidered
> condition is meet.
>
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> .../drm/i915/display/intel_display_debugfs.c | 3 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 64 ++++++++++++-------
> drivers/gpu/drm/i915/i915_reg.h | 5 +-
> drivers/gpu/drm/i915/intel_uncore.c | 47 ++++++++++++++
> drivers/gpu/drm/i915/intel_uncore.h | 7 ++
> 5 files changed, 100 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 68f4ba8c46e75..662596adb1da6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -303,8 +303,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> };
> val = intel_de_read(dev_priv,
> EDP_PSR2_STATUS(intel_dp->psr.transcoder));
> - status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> - EDP_PSR2_STATUS_STATE_SHIFT;
> + status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
> if (status_val < ARRAY_SIZE(live_status))
> status = live_status[status_val];
> } else {
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index c1894b056d6c1..bd13325782f11 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1763,15 +1763,33 @@ void intel_psr_update(struct intel_dp *intel_dp,
> mutex_unlock(&intel_dp->psr.lock);
> }
>
> -/**
> - * psr_wait_for_idle - wait for PSR1 to idle
> - * @intel_dp: Intel DP
> - * @out_value: PSR status in case of failure
> - *
> - * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
> - *
> - */
> -static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
> +static bool _is_psr2_read_for_pipe_update(void *data)
> +{
> + struct intel_dp *intel_dp = data;
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u32 val;
> +
> + val = intel_uncore_read_fw(&dev_priv->uncore,
> + EDP_PSR2_STATUS(intel_dp->psr.transcoder));
> + val &= EDP_PSR2_STATUS_STATE_MASK;
> +
> + return val == EDP_PSR2_STATUS_STATE_SLEEP || val == EDP_PSR2_STATUS_STATE_IDLE;
In the state where PSR2 source hw does not send the updated area, there
are states such as FAST_SLEEP and DEEP_SLEEP.
Here, we are only waiting for the EDP_PSR2_STATUS_STATE_SLEEP /
EDP_PSR2_STATUS_STATE_IDLE status. In this regard, could you share the
state machine diagram of PSR2 Source HW?
> +}
> +
> +static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + unsigned int fw;
> +
> + fw = intel_uncore_forcewake_for_reg(&dev_priv->uncore,
> + EDP_PSR2_STATUS(intel_dp->psr.transcoder),
> + FW_REG_READ);
> + return intel_wait_for_condition(&dev_priv->uncore,
> + _is_psr2_read_for_pipe_update,
> + intel_dp, fw, 50);
> +}
> +
> +static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> @@ -1781,15 +1799,13 @@ static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
> * exit training time + 1.5 ms of aux channel handshake. 50 ms is
> * defensive enough to cover everything.
> */
> - return __intel_wait_for_register(&dev_priv->uncore,
> - EDP_PSR_STATUS(intel_dp->psr.transcoder),
> - EDP_PSR_STATUS_STATE_MASK,
> - EDP_PSR_STATUS_STATE_IDLE, 2, 50,
> - out_value);
> + return intel_de_wait_for_clear(dev_priv,
> + EDP_PSR_STATUS(intel_dp->psr.transcoder),
> + EDP_PSR_STATUS_STATE_MASK, 50);
Since EDP_PSR_STATUS_STATE_IDLE is 0x0, the code meaning is the same as
the previous code here, but from the code readability point of view, the
previous code looks better to me.
In the case of PSR1, if there is a functional change in the changed code
that I did not notice, could you please let me know?
> }
>
> /**
> - * intel_psr_wait_for_idle - wait for PSR1 to idle
> + * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
> * @new_crtc_state: new CRTC state
> *
> * This function is expected to be called from pipe_update_start() where it is
> @@ -1806,19 +1822,23 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
> for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
> new_crtc_state->uapi.encoder_mask) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> - u32 psr_status;
> + int ret;
>
> mutex_lock(&intel_dp->psr.lock);
> - if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) {
> +
> + if (!intel_dp->psr.enabled) {
> mutex_unlock(&intel_dp->psr.lock);
> continue;
> }
>
> - /* when the PSR1 is enabled */
> - if (psr_wait_for_idle(intel_dp, &psr_status))
> - drm_err(&dev_priv->drm,
> - "PSR idle timed out 0x%x, atomic update may fail\n",
> - psr_status);
> + if (intel_dp->psr.psr2_enabled)
> + ret = _psr2_ready_for_pipe_update_locked(intel_dp);
> + else
> + ret = _psr1_ready_for_pipe_update_locked(intel_dp);
> +
> + if (ret)
> + drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
> +
> mutex_unlock(&intel_dp->psr.lock);
> }
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c3a21f7c003de..7aaa0bc9a8fe7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4698,8 +4698,9 @@ enum {
> #define _PSR2_STATUS_A 0x60940
> #define _PSR2_STATUS_EDP 0x6f940
> #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
> -#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
> -#define EDP_PSR2_STATUS_STATE_SHIFT 28
> +#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
> +#define EDP_PSR2_STATUS_STATE_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x3)
> +#define EDP_PSR2_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x0)
>
> #define _PSR2_SU_STATUS_A 0x60914
> #define _PSR2_SU_STATUS_EDP 0x6f914
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index f9767054dbdf9..1467b7709ca3a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2379,6 +2379,28 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
> #undef done
> }
>
> +static int __intel_wait_for_condition_fw(bool (*func)(void *data), void *data,
> + unsigned int fast_timeout_us,
> + unsigned int slow_timeout_ms)
> +{
> +#define done (func(data))
> + int ret;
> +
> + /* Catch any overuse of this function */
> + might_sleep_if(slow_timeout_ms);
> + GEM_BUG_ON(fast_timeout_us > 20000);
> + GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
> +
> + ret = -ETIMEDOUT;
> + if (fast_timeout_us && fast_timeout_us <= 20000)
> + ret = _wait_for_atomic(done, fast_timeout_us, 0);
> + if (ret && slow_timeout_ms)
> + ret = wait_for(done, slow_timeout_ms);
> +
> + return ret;
> +#undef done
> +}
> +
> /**
> * __intel_wait_for_register - wait until register matches expected state
> * @uncore: the struct intel_uncore
> @@ -2438,6 +2460,31 @@ int __intel_wait_for_register(struct intel_uncore *uncore,
> return ret;
> }
>
> +int intel_wait_for_condition(struct intel_uncore *uncore,
> + bool (*func)(void *data),
> + void *data,
> + unsigned int fw,
> + unsigned int slow_timeout_ms)
> +{
> + unsigned int fast_timeout_us = 2;
> + int ret;
> +
> + might_sleep_if(slow_timeout_ms);
> +
> + spin_lock_irq(&uncore->lock);
> + intel_uncore_forcewake_get__locked(uncore, fw);
> +
> + ret = __intel_wait_for_condition_fw(func, data, fast_timeout_us, 0);
> +
> + intel_uncore_forcewake_put__locked(uncore, fw);
> + spin_unlock_irq(&uncore->lock);
> +
> + if (ret && slow_timeout_ms)
> + ret = __wait_for(, (func(data)), slow_timeout_ms * 1000, 10, 1000);
> +
> + return ret;
> +}
> +
> bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
> {
> bool ret;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 531665b08039c..e3041525a6db8 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -275,6 +275,7 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
> unsigned int fast_timeout_us,
> unsigned int slow_timeout_ms,
> u32 *out_value);
> +
> static inline int
> intel_wait_for_register_fw(struct intel_uncore *uncore,
> i915_reg_t reg,
> @@ -286,6 +287,12 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
> 2, timeout_ms, NULL);
> }
>
> +int intel_wait_for_condition(struct intel_uncore *uncore,
> + bool (*func)(void *data),
> + void *data,
> + unsigned int fw,
> + unsigned int timeout_ms);
> +
> /* register access functions */
> #define __raw_read(x__, s__) \
> static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe
2021-09-23 13:27 ` Gwan-gyeong Mun
@ 2021-09-23 17:25 ` Souza, Jose
0 siblings, 0 replies; 11+ messages in thread
From: Souza, Jose @ 2021-09-23 17:25 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx
On Thu, 2021-09-23 at 16:27 +0300, Gwan-gyeong Mun wrote:
>
> On 9/17/21 11:52 PM, José Roberto de Souza wrote:
> > Alderlake-P was getting 'max time under evasion' messages when PSR2
> > was enabled, this is due PIPE_SCANLINE/PIPEDSL returning 0 over a
> > period of time longer than VBLANK_EVASION_TIME_US.
> >
> > For PSR1 we had the same issue so intel_psr_wait_for_idle() was
> > implemented to wait for PSR1 to get into idle state but nothing was
> > done for PSR2.
> >
> > For PSR2 we can't only wait for idle state as PSR2 tends to keep
> > into sleep state that means it is ready to send selective updates.
> >
> > To do so it was necessary to add intel_wait_for_condition(), this
> > takes as parameter a function that will return true when the desidered
> > condition is meet.
> >
> > Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > .../drm/i915/display/intel_display_debugfs.c | 3 +-
> > drivers/gpu/drm/i915/display/intel_psr.c | 64 ++++++++++++-------
> > drivers/gpu/drm/i915/i915_reg.h | 5 +-
> > drivers/gpu/drm/i915/intel_uncore.c | 47 ++++++++++++++
> > drivers/gpu/drm/i915/intel_uncore.h | 7 ++
> > 5 files changed, 100 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 68f4ba8c46e75..662596adb1da6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -303,8 +303,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
> > };
> > val = intel_de_read(dev_priv,
> > EDP_PSR2_STATUS(intel_dp->psr.transcoder));
> > - status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >>
> > - EDP_PSR2_STATUS_STATE_SHIFT;
> > + status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val);
> > if (status_val < ARRAY_SIZE(live_status))
> > status = live_status[status_val];
> > } else {
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index c1894b056d6c1..bd13325782f11 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1763,15 +1763,33 @@ void intel_psr_update(struct intel_dp *intel_dp,
> > mutex_unlock(&intel_dp->psr.lock);
> > }
> >
> > -/**
> > - * psr_wait_for_idle - wait for PSR1 to idle
> > - * @intel_dp: Intel DP
> > - * @out_value: PSR status in case of failure
> > - *
> > - * Returns: 0 on success or -ETIMEOUT if PSR status does not idle.
> > - *
> > - */
> > -static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
> > +static bool _is_psr2_read_for_pipe_update(void *data)
> > +{
> > + struct intel_dp *intel_dp = data;
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + u32 val;
> > +
> > + val = intel_uncore_read_fw(&dev_priv->uncore,
> > + EDP_PSR2_STATUS(intel_dp->psr.transcoder));
> > + val &= EDP_PSR2_STATUS_STATE_MASK;
> > +
> > + return val == EDP_PSR2_STATUS_STATE_SLEEP || val == EDP_PSR2_STATUS_STATE_IDLE;
> In the state where PSR2 source hw does not send the updated area, there
> are states such as FAST_SLEEP and DEEP_SLEEP.
> Here, we are only waiting for the EDP_PSR2_STATUS_STATE_SLEEP /
> EDP_PSR2_STATUS_STATE_IDLE status. In this regard, could you share the
> state machine diagram of PSR2 Source HW?
I don't have it, got this 2 states from experiments of reads to EDP_PSR2_STATUS.
When PSR2 HW finish an update it goes to SLEEP and if idle enough it goes to DEEP_SLEEP.
But as VBL interrupts are enabled before intel_psr_wait_for_idle() is called, if PSR2 was in DC5/DC6/DEEP_SLEEP it goes back to SLEEP.
The check for IDLE state is also important as we could be updating screen exactly one frame after PSR2 was enabled, so it did not had enough frames
(EDP_PSR2_FRAME_BEFORE_SU)to activate PSR2.
> > +}
> > +
> > +static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> > +{
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + unsigned int fw;
> > +
> > + fw = intel_uncore_forcewake_for_reg(&dev_priv->uncore,
> > + EDP_PSR2_STATUS(intel_dp->psr.transcoder),
> > + FW_REG_READ);
> > + return intel_wait_for_condition(&dev_priv->uncore,
> > + _is_psr2_read_for_pipe_update,
> > + intel_dp, fw, 50);
> > +}
> > +
> > +static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > @@ -1781,15 +1799,13 @@ static int psr_wait_for_idle(struct intel_dp *intel_dp, u32 *out_value)
> > * exit training time + 1.5 ms of aux channel handshake. 50 ms is
> > * defensive enough to cover everything.
> > */
> > - return __intel_wait_for_register(&dev_priv->uncore,
> > - EDP_PSR_STATUS(intel_dp->psr.transcoder),
> > - EDP_PSR_STATUS_STATE_MASK,
> > - EDP_PSR_STATUS_STATE_IDLE, 2, 50,
> > - out_value);
> > + return intel_de_wait_for_clear(dev_priv,
> > + EDP_PSR_STATUS(intel_dp->psr.transcoder),
> > + EDP_PSR_STATUS_STATE_MASK, 50);
> Since EDP_PSR_STATUS_STATE_IDLE is 0x0, the code meaning is the same as
> the previous code here, but from the code readability point of view, the
> previous code looks better to me.
> In the case of PSR1, if there is a functional change in the changed code
> that I did not notice, could you please let me know?
Functions that starts with '__' are supposed to be static and only used inside of the same C file that it was defined, but someone misused and
exported this function and it spread through i915.
So here switching to intel_de_wait_for_clear() that simplify the arguments and at the end it call the __intel_wait_for_register() with the exactly
same arguments as we did.
> > }
> >
> > /**
> > - * intel_psr_wait_for_idle - wait for PSR1 to idle
> > + * intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
> > * @new_crtc_state: new CRTC state
> > *
> > * This function is expected to be called from pipe_update_start() where it is
> > @@ -1806,19 +1822,23 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
> > for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
> > new_crtc_state->uapi.encoder_mask) {
> > struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > - u32 psr_status;
> > + int ret;
> >
> > mutex_lock(&intel_dp->psr.lock);
> > - if (!intel_dp->psr.enabled || intel_dp->psr.psr2_enabled) {
> > +
> > + if (!intel_dp->psr.enabled) {
> > mutex_unlock(&intel_dp->psr.lock);
> > continue;
> > }
> >
> > - /* when the PSR1 is enabled */
> > - if (psr_wait_for_idle(intel_dp, &psr_status))
> > - drm_err(&dev_priv->drm,
> > - "PSR idle timed out 0x%x, atomic update may fail\n",
> > - psr_status);
> > + if (intel_dp->psr.psr2_enabled)
> > + ret = _psr2_ready_for_pipe_update_locked(intel_dp);
> > + else
> > + ret = _psr1_ready_for_pipe_update_locked(intel_dp);
> > +
> > + if (ret)
> > + drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
> > +
> > mutex_unlock(&intel_dp->psr.lock);
> > }
> > }
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c3a21f7c003de..7aaa0bc9a8fe7 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4698,8 +4698,9 @@ enum {
> > #define _PSR2_STATUS_A 0x60940
> > #define _PSR2_STATUS_EDP 0x6f940
> > #define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A)
> > -#define EDP_PSR2_STATUS_STATE_MASK (0xf << 28)
> > -#define EDP_PSR2_STATUS_STATE_SHIFT 28
> > +#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28)
> > +#define EDP_PSR2_STATUS_STATE_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x3)
> > +#define EDP_PSR2_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x0)
> >
> > #define _PSR2_SU_STATUS_A 0x60914
> > #define _PSR2_SU_STATUS_EDP 0x6f914
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index f9767054dbdf9..1467b7709ca3a 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -2379,6 +2379,28 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
> > #undef done
> > }
> >
> > +static int __intel_wait_for_condition_fw(bool (*func)(void *data), void *data,
> > + unsigned int fast_timeout_us,
> > + unsigned int slow_timeout_ms)
> > +{
> > +#define done (func(data))
> > + int ret;
> > +
> > + /* Catch any overuse of this function */
> > + might_sleep_if(slow_timeout_ms);
> > + GEM_BUG_ON(fast_timeout_us > 20000);
> > + GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms);
> > +
> > + ret = -ETIMEDOUT;
> > + if (fast_timeout_us && fast_timeout_us <= 20000)
> > + ret = _wait_for_atomic(done, fast_timeout_us, 0);
> > + if (ret && slow_timeout_ms)
> > + ret = wait_for(done, slow_timeout_ms);
> > +
> > + return ret;
> > +#undef done
> > +}
> > +
> > /**
> > * __intel_wait_for_register - wait until register matches expected state
> > * @uncore: the struct intel_uncore
> > @@ -2438,6 +2460,31 @@ int __intel_wait_for_register(struct intel_uncore *uncore,
> > return ret;
> > }
> >
> > +int intel_wait_for_condition(struct intel_uncore *uncore,
> > + bool (*func)(void *data),
> > + void *data,
> > + unsigned int fw,
> > + unsigned int slow_timeout_ms)
> > +{
> > + unsigned int fast_timeout_us = 2;
> > + int ret;
> > +
> > + might_sleep_if(slow_timeout_ms);
> > +
> > + spin_lock_irq(&uncore->lock);
> > + intel_uncore_forcewake_get__locked(uncore, fw);
> > +
> > + ret = __intel_wait_for_condition_fw(func, data, fast_timeout_us, 0);
> > +
> > + intel_uncore_forcewake_put__locked(uncore, fw);
> > + spin_unlock_irq(&uncore->lock);
> > +
> > + if (ret && slow_timeout_ms)
> > + ret = __wait_for(, (func(data)), slow_timeout_ms * 1000, 10, 1000);
> > +
> > + return ret;
> > +}
> > +
> > bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore)
> > {
> > bool ret;
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> > index 531665b08039c..e3041525a6db8 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.h
> > +++ b/drivers/gpu/drm/i915/intel_uncore.h
> > @@ -275,6 +275,7 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
> > unsigned int fast_timeout_us,
> > unsigned int slow_timeout_ms,
> > u32 *out_value);
> > +
> > static inline int
> > intel_wait_for_register_fw(struct intel_uncore *uncore,
> > i915_reg_t reg,
> > @@ -286,6 +287,12 @@ intel_wait_for_register_fw(struct intel_uncore *uncore,
> > 2, timeout_ms, NULL);
> > }
> >
> > +int intel_wait_for_condition(struct intel_uncore *uncore,
> > + bool (*func)(void *data),
> > + void *data,
> > + unsigned int fw,
> > + unsigned int timeout_ms);
> > +
> > /* register access functions */
> > #define __raw_read(x__, s__) \
> > static inline u##x__ __raw_uncore_read##x__(const struct intel_uncore *uncore, \
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-09-23 17:25 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-17 20:52 [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load José Roberto de Souza
2021-09-17 20:52 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Wait PSR2 get out of deep sleep to update pipe José Roberto de Souza
2021-09-23 13:27 ` Gwan-gyeong Mun
2021-09-23 17:25 ` Souza, Jose
2021-09-17 20:52 ` [Intel-gfx] [PATCH 3/3] drm/i915/display: Match PSR2 selective fetch sequences with specification José Roberto de Souza
2021-09-20 18:12 ` Gwan-gyeong Mun
2021-09-17 21:05 ` [Intel-gfx] [PATCH 1/3] drm/i915/display/dmc: Set DC_STATE_DEBUG_MASK_CORES after firmware load Imre Deak
2021-09-20 19:06 ` Imre Deak
2021-09-17 21:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] " Patchwork
2021-09-17 21:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-17 22:50 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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