From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Uma Shankar <uma.shankar@intel.com>
Subject: [Intel-gfx] [PATCH] drm/i915/fbc: Allow FBC with Yf tiling
Date: Fri, 24 Sep 2021 17:13:30 +0300 [thread overview]
Message-ID: <20210924141330.1515-1-ville.syrjala@linux.intel.com> (raw)
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
FBC+Yf tiling seems to work just fine, and unlike with linear
the hardware does appear to correctly calculate the CFB stride
with using the override stride on both cfl and glk. So no need
for any additional tweaks.
Cc: Uma Shankar <uma.shankar@intel.com> #v2
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 46f62fdf9eee..687431faf02f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -746,6 +746,7 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv,
switch (modifier) {
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_Yf_TILED:
return DISPLAY_VER(dev_priv) >= 9;
case I915_FORMAT_MOD_X_TILED:
return true;
--
2.32.0
next reply other threads:[~2021-09-24 14:13 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-24 14:13 Ville Syrjala [this message]
2021-09-24 16:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: Allow FBC with Yf tiling Patchwork
2021-09-24 19:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-27 15:16 ` [Intel-gfx] [PATCH] " Shankar, Uma
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