From: Alan Previn <alan.previn.teres.alexis@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "Anshuman Gupta" <anshuman.gupta@intel.com>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Gaurav Kumar" <kumar.gaurav@intel.com>,
"Shankar Uma" <uma.shankar@intel.com>,
"Daniele Ceraolo Spurio" <daniele.ceraolospurio@intel.com>,
"Juston Li" <juston.li@intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>
Subject: [Intel-gfx] [PATCH v13 14/17] drm/i915/pxp: black pixels on pxp disabled
Date: Fri, 24 Sep 2021 12:14:49 -0700 [thread overview]
Message-ID: <20210924191452.1539378-15-alan.previn.teres.alexis@intel.com> (raw)
In-Reply-To: <20210924191452.1539378-1-alan.previn.teres.alexis@intel.com>
From: Anshuman Gupta <anshuman.gupta@intel.com>
When protected sufaces has flipped and pxp session is disabled,
display black pixels by using plane color CTM correction.
v2:
- Display black pixels in async flip too.
v3:
- Removed the black pixels logic for async flip. [Ville]
- Used plane state to force black pixels. [Ville]
v4 (Daniele): update pxp_is_borked check.
v5: rebase on top of v9 plane decryption moving the decrypt check
(Juston)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gaurav Kumar <kumar.gaurav@intel.com>
Cc: Shankar Uma <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Juston Li <juston.li@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 12 ++++-
.../drm/i915/display/intel_display_types.h | 3 ++
.../drm/i915/display/skl_universal_plane.c | 36 ++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 46 +++++++++++++++++++
4 files changed, 94 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e84c627eb476..ba6f2fd29c94 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9016,6 +9016,11 @@ static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj)
return intel_pxp_key_check(&i915->gt.pxp, obj, false) == 0;
}
+static bool pxp_is_borked(struct drm_i915_gem_object *obj)
+{
+ return i915_gem_object_is_protected(obj) && !bo_has_valid_encryption(obj);
+}
+
static int intel_atomic_check_planes(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -9077,10 +9082,13 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state)
new_plane_state = intel_atomic_get_new_plane_state(state, plane);
old_plane_state = intel_atomic_get_old_plane_state(state, plane);
fb = new_plane_state->hw.fb;
- if (fb)
+ if (fb) {
new_plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb));
- else
+ new_plane_state->force_black = pxp_is_borked(intel_fb_obj(fb));
+ } else {
new_plane_state->decrypt = old_plane_state->decrypt;
+ new_plane_state->force_black = old_plane_state->force_black;
+ }
}
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3a64cade03e6..da5b95235aa8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -626,6 +626,9 @@ struct intel_plane_state {
/* Plane pxp decryption state */
bool decrypt;
+ /* Plane state to display black pixels when pxp is borked */
+ bool force_black;
+
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ff9b5486ca1f..a0e53a3b267a 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1008,6 +1008,33 @@ static u32 skl_surf_address(const struct intel_plane_state *plane_state,
}
}
+static void intel_load_plane_csc_black(struct intel_plane *intel_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
+ enum pipe pipe = intel_plane->pipe;
+ enum plane_id plane = intel_plane->id;
+ u16 postoff = 0;
+
+ drm_dbg_kms(&dev_priv->drm, "plane color CTM to black %s:%d\n",
+ intel_plane->base.name, plane);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
+ intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
+
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
+ intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -1120,14 +1147,21 @@ skl_program_plane(struct intel_plane *plane,
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+ plane_color_ctl = intel_de_read_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
/*
* FIXME: pxp session invalidation can hit any time even at time of commit
* or after the commit, display content will be garbage.
*/
- if (plane_state->decrypt)
+ if (plane_state->decrypt) {
plane_surf |= PLANE_SURF_DECRYPT;
+ } else if (plane_state->force_black) {
+ intel_load_plane_csc_black(plane);
+ plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
+ }
+ intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
+ plane_color_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 682c239b2d55..8f162a487eb9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7257,6 +7257,7 @@ enum {
#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
#define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30) /* Pre-ICL */
#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
+#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
#define PLANE_COLOR_INPUT_CSC_ENABLE (1 << 20) /* ICL+ */
#define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23) /* Pre-ICL */
#define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
@@ -11399,6 +11400,51 @@ enum skl_power_gate {
_PAL_PREC_MULTI_SEG_DATA_A, \
_PAL_PREC_MULTI_SEG_DATA_B)
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
+/* Plane CSC Registers */
+#define _PLANE_CSC_RY_GY_1_A 0x70210
+#define _PLANE_CSC_RY_GY_2_A 0x70310
+
+#define _PLANE_CSC_RY_GY_1_B 0x71210
+#define _PLANE_CSC_RY_GY_2_B 0x71310
+
+#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
+ _PLANE_CSC_RY_GY_1_B)
+#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+ _PLANE_INPUT_CSC_RY_GY_2_B)
+#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
+ _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
+ _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
+#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
+
+#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
+#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
+
+#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
+ _PLANE_CSC_PREOFF_HI_1_B)
+#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
+ _PLANE_CSC_PREOFF_HI_2_B)
+#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
+ (index) * 4)
+
+#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
+#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
+
+#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
+#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
+
+#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
+ _PLANE_CSC_POSTOFF_HI_1_B)
+#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
+ _PLANE_CSC_POSTOFF_HI_2_B)
+#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
+ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
+ (index) * 4)
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
--
2.25.1
next prev parent reply other threads:[~2021-09-24 19:14 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-24 19:14 [Intel-gfx] [PATCH v13 00/17] drm/i915: Introduce Intel PXP Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 01/17] drm/i915/pxp: Define PXP component interface Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 02/17] mei: pxp: export pavp client to me client bus Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 03/17] drm/i915/pxp: define PXP device flag and kconfig Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 04/17] drm/i915/pxp: allocate a vcs context for pxp usage Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 05/17] drm/i915/pxp: Implement funcs to create the TEE channel Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 06/17] drm/i915/pxp: set KCR reg init Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 07/17] drm/i915/pxp: Create the arbitrary session after boot Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 08/17] drm/i915/pxp: Implement arb session teardown Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 09/17] drm/i915/pxp: Implement PXP irq handler Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 10/17] drm/i915/pxp: interfaces for using protected objects Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 11/17] drm/i915/pxp: start the arb session on demand Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 12/17] drm/i915/pxp: Enable PXP power management Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 13/17] drm/i915/pxp: Add plane decryption support Alan Previn
2021-09-24 19:14 ` Alan Previn [this message]
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 15/17] drm/i915/pxp: add pxp debugfs Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 16/17] drm/i915/pxp: add PXP documentation Alan Previn
2021-09-24 19:14 ` [Intel-gfx] [PATCH v13 17/17] drm/i915/pxp: enable PXP for integrated Gen12 Alan Previn
2021-09-24 22:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce Intel PXP (rev13) Patchwork
2021-09-24 22:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-24 22:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-25 2:39 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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