From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 12/14] drm/i915: Add encoder hook to get the PLL type used by TC ports
Date: Thu, 16 Mar 2023 15:17:22 +0200 [thread overview]
Message-ID: <20230316131724.359612-13-imre.deak@intel.com> (raw)
In-Reply-To: <20230316131724.359612-1-imre.deak@intel.com>
Add an encoder hook, which can be called on enabled TC ports to
determine if the port uses a TBT or a non-TBT PLL. An upcoming patch
will use this to sanity check active TC port's PHY state wrt. the PLL
type used by the port.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 37 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_ddi.h | 3 ++
.../drm/i915/display/intel_display_types.h | 5 +++
3 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e79da640759c3..da4e1a047a806 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3541,6 +3541,37 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
intel_ddi_get_config(encoder, crtc_state);
}
+static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)
+{
+ return pll->info->id == DPLL_ID_ICL_TBTPLL;
+}
+
+static enum icl_port_dpll_id
+icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+
+ if (drm_WARN_ON(&i915->drm, !pll))
+ return ICL_PORT_DPLL_DEFAULT;
+
+ if (icl_ddi_tc_pll_is_tbt(pll))
+ return ICL_PORT_DPLL_DEFAULT;
+ else
+ return ICL_PORT_DPLL_MG_PHY;
+}
+
+enum icl_port_dpll_id
+intel_ddi_port_pll_type(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (!encoder->port_pll_type)
+ return ICL_PORT_DPLL_DEFAULT;
+
+ return encoder->port_pll_type(encoder, crtc_state);
+}
+
static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct intel_shared_dpll *pll)
@@ -3553,7 +3584,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
if (drm_WARN_ON(&i915->drm, !pll))
return;
- if (pll->info->id == DPLL_ID_ICL_TBTPLL)
+ if (icl_ddi_tc_pll_is_tbt(pll))
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
else
port_dpll_id = ICL_PORT_DPLL_MG_PHY;
@@ -3566,7 +3597,7 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
icl_set_active_port_dpll(crtc_state, port_dpll_id);
- if (crtc_state->shared_dpll->info->id == DPLL_ID_ICL_TBTPLL)
+ if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
else
crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
@@ -4402,6 +4433,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->enable_clock = jsl_ddi_tc_enable_clock;
encoder->disable_clock = jsl_ddi_tc_disable_clock;
encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
+ encoder->port_pll_type = icl_ddi_tc_port_pll_type;
encoder->get_config = icl_ddi_combo_get_config;
} else {
encoder->enable_clock = icl_ddi_combo_enable_clock;
@@ -4414,6 +4446,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->enable_clock = icl_ddi_tc_enable_clock;
encoder->disable_clock = icl_ddi_tc_disable_clock;
encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
+ encoder->port_pll_type = icl_ddi_tc_port_pll_type;
encoder->get_config = icl_ddi_tc_get_config;
} else {
encoder->enable_clock = icl_ddi_combo_enable_clock;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index 361f6874dde53..c85e74ae68e4d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -40,6 +40,9 @@ void hsw_ddi_enable_clock(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void hsw_ddi_disable_clock(struct intel_encoder *encoder);
bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder);
+enum icl_port_dpll_id
+intel_ddi_port_pll_type(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
void hsw_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state);
struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 06bbfd426ac70..abb72e1f27d5c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -255,6 +255,11 @@ struct intel_encoder {
* Returns whether the port clock is enabled or not.
*/
bool (*is_clock_enabled)(struct intel_encoder *encoder);
+ /*
+ * Returns the PLL type the port uses.
+ */
+ enum icl_port_dpll_id (*port_pll_type)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int *n_entries);
--
2.37.1
next prev parent reply other threads:[~2023-03-16 13:40 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-16 13:17 [Intel-gfx] [PATCH 00/14] drm/i915/tc: Fix a few TypeC / MST issues Imre Deak
2023-03-16 13:17 ` [Intel-gfx] [PATCH 01/14] drm/i915/tc: Abort DP AUX transfer on a disconnected TC port Imre Deak
2023-03-21 11:09 ` Kahola, Mika
2023-03-21 13:45 ` Imre Deak
2023-03-22 11:19 ` Andrzej Hajda
2023-03-22 12:04 ` Imre Deak
2023-03-16 13:17 ` [Intel-gfx] [PATCH 02/14] drm/i915/tc: Fix TC port link ref init for DP MST during HW readout Imre Deak
2023-03-21 12:06 ` Kahola, Mika
2023-03-21 14:00 ` Imre Deak
2023-03-24 7:03 ` Kahola, Mika
2023-03-16 13:17 ` [Intel-gfx] [PATCH 03/14] drm/i915/tc: Fix the ICL PHY ownership check in TC-cold state Imre Deak
2023-03-16 13:51 ` Souza, Jose
2023-03-16 13:17 ` [Intel-gfx] [PATCH 04/14] drm/i915/tc: Fix system resume MST mode restore for DP-alt sinks Imre Deak
2023-03-20 20:16 ` Ville Syrjälä
2023-03-20 21:36 ` Imre Deak
2023-03-16 13:17 ` [Intel-gfx] [PATCH 05/14] drm/i915/tc: Wait for IOM/FW PHY initialization of legacy TC ports Imre Deak
2023-03-24 8:14 ` Kahola, Mika
2023-03-16 13:17 ` [Intel-gfx] [PATCH 06/14] drm/i915/tc: Factor out helpers converting HPD mask to TC mode Imre Deak
2023-03-24 8:16 ` Kahola, Mika
2023-03-16 13:17 ` [Intel-gfx] [PATCH 07/14] drm/i915/tc: Fix target TC mode for a disconnected legacy port Imre Deak
2023-03-16 13:17 ` [Intel-gfx] [PATCH 08/14] drm/i915/tc: Fix TC mode for a legacy port if the PHY is not ready Imre Deak
2023-03-16 13:17 ` [Intel-gfx] [PATCH 09/14] drm/i915/tc: Fix initial TC mode on disabled legacy ports Imre Deak
2023-03-16 13:17 ` [Intel-gfx] [PATCH 10/14] drm/i915/tc: Make the TC mode readout consistent in all PHY states Imre Deak
2023-03-16 13:17 ` [Intel-gfx] [PATCH 11/14] drm/i915/tc: Assume a TC port is legacy if VBT says the port has HDMI Imre Deak
2023-03-20 20:01 ` Ville Syrjälä
2023-03-20 21:33 ` Imre Deak
2023-03-21 22:00 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-03-16 13:17 ` Imre Deak [this message]
2023-03-16 13:17 ` [Intel-gfx] [PATCH 13/14] drm/i915/tc: Factor out a function querying active links on a TC port Imre Deak
2023-03-20 20:05 ` Ville Syrjälä
2023-03-20 21:34 ` Imre Deak
2023-03-21 22:01 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-03-16 13:17 ` [Intel-gfx] [PATCH 14/14] drm/i915/tc: Check the PLL type used by an enabled " Imre Deak
2023-03-21 22:01 ` [Intel-gfx] [PATCH v2 " Imre Deak
2023-03-16 22:27 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tc: Fix a few TypeC / MST issues Patchwork
2023-03-17 8:54 ` Imre Deak
2023-03-20 20:19 ` [Intel-gfx] [PATCH 00/14] " Ville Syrjälä
2023-03-20 21:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tc: Fix a few TypeC / MST issues (rev2) Patchwork
2023-03-20 21:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-20 21:48 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-20 21:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-21 2:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-21 22:16 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/tc: Fix a few TypeC / MST issues (rev5) Patchwork
2023-03-21 22:16 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: " Patchwork
2023-03-21 22:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-21 22:37 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-03-21 23:43 ` Imre Deak
2023-03-22 9:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tc: Fix a few TypeC / MST issues (rev6) Patchwork
2023-03-22 9:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-22 9:45 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-22 10:01 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-22 15:07 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-22 18:38 ` Imre Deak
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