From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 3/6] drm/i915/vrr: Make delayed vblank operational in VRR mode on adl/dg2
Date: Mon, 20 Mar 2023 22:33:49 +0200 [thread overview]
Message-ID: <20230320203352.19515-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230320203352.19515-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On adl/dg2 a chicken bit needs to be set for TRANS_SET_CONTENXT_LATENCY
to take effect in VRR mode. Can't really think of a reason why we'd
ever disable that chicken bit, so let's just always set it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 6d749de71058..348a7cc8e620 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -173,6 +173,14 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ /*
+ * TRANS_SET_CONTEXT_LATENCY with VRR enabled
+ * requires this chicken bit on ADL/DG2.
+ */
+ if (DISPLAY_VER(dev_priv) == 13)
+ intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
+ 0, PIPE_VBLANK_WITH_DELAY);
+
if (!crtc_state->vrr.enable)
return;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d22ffd7a32dc..09740f7295eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5544,13 +5544,12 @@
[TRANSCODER_B] = _CHICKEN_TRANS_B, \
[TRANSCODER_C] = _CHICKEN_TRANS_C, \
[TRANSCODER_D] = _CHICKEN_TRANS_D))
-
#define _MTL_CHICKEN_TRANS_A 0x604e0
#define _MTL_CHICKEN_TRANS_B 0x614e0
#define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
_MTL_CHICKEN_TRANS_A, \
_MTL_CHICKEN_TRANS_B)
-
+#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* ADL/DG2 */
#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
--
2.39.2
next prev parent reply other threads:[~2023-03-20 20:34 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 20:33 [Intel-gfx] [PATCH 0/6] drm/i915/vrr: Allow fastset to enable/disable VRR Ville Syrjala
2023-03-20 20:33 ` [Intel-gfx] [PATCH 1/6] drm/i915: Generalize planes_{enabling, disabling}() Ville Syrjala
2023-04-05 7:31 ` Golani, Mitulkumar Ajitkumar
2023-03-20 20:33 ` [Intel-gfx] [PATCH 2/6] drm/i915/vrr: Eliminate redundant function arguments Ville Syrjala
2023-04-05 6:58 ` Golani, Mitulkumar Ajitkumar
2023-03-20 20:33 ` Ville Syrjala [this message]
2023-04-05 7:05 ` [Intel-gfx] [PATCH 3/6] drm/i915/vrr: Make delayed vblank operational in VRR mode on adl/dg2 Golani, Mitulkumar Ajitkumar
2023-03-20 20:33 ` [Intel-gfx] [PATCH 4/6] drm/i915/vrr: Tell intel_crtc_update_active_timings() about VRR explicitly Ville Syrjala
2023-04-05 7:10 ` Golani, Mitulkumar Ajitkumar
2023-03-20 20:33 ` [Intel-gfx] [PATCH 5/6] drm/i915/vrr: Relocate VRR enable/disable Ville Syrjala
2023-03-21 13:56 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-03-27 20:05 ` Golani, Mitulkumar Ajitkumar
2023-04-11 5:41 ` Ville Syrjälä
2023-04-12 7:45 ` Ville Syrjälä
2023-04-12 14:14 ` Golani, Mitulkumar Ajitkumar
2023-04-12 14:16 ` Golani, Mitulkumar Ajitkumar
2023-04-12 15:05 ` Ville Syrjälä
2023-04-12 14:11 ` Golani, Mitulkumar Ajitkumar
2023-04-12 14:20 ` Ville Syrjälä
2023-03-20 20:33 ` [Intel-gfx] [PATCH 6/6] drm/i915/vrr: Allow VRR to be toggled during fastsets Ville Syrjala
2023-04-05 7:27 ` Golani, Mitulkumar Ajitkumar
2023-03-21 12:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/vrr: Allow fastset to enable/disable VRR Patchwork
2023-03-21 12:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-21 12:50 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-21 13:09 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-03-21 15:34 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/vrr: Allow fastset to enable/disable VRR (rev2) Patchwork
2023-03-21 15:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: " Patchwork
2023-03-21 15:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-21 15:34 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-21 15:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-21 21:07 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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