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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Do/Es3MsOnNrFWt1HlWIuiH3LYG52Kc1QUGUTvbfh1IL5qC92xw8WMYmg3fm?= =?us-ascii?Q?KpMaVGvhs5gWpq0KVhCrS3GBGzgxqdd8W31TQF5K87ylUfKUdLbz9NoSQXV6?= =?us-ascii?Q?HQQiUYd8YNVanNHWBHguB2TfOTZGeCnWR8yn6Flk4DF12BEwyIALDbGYjU4W?= =?us-ascii?Q?7xmW0ie2QXmu+c16grW7Zk8Ay3MVUx25SEHJssJLh8OKwZ8xTCLaOJ9+3ogG?= =?us-ascii?Q?7/aUawj90obhqY41ymMhbh5T1XmCMXcFf5A7l15Uo0c1i6kgK9iasFwbsAHy?= =?us-ascii?Q?6lXI6HLndKVhJG4IC7WLHUvIgpmG/KGtfRjlWfm9PiZH3Fe2KIWxhfR4yxAY?= =?us-ascii?Q?kF2ikBXzQEL5VR8HQRU1ExqitgWe3pTf2V8Q+VBYb2lZ9OaNW10vXi4U9Uds?= =?us-ascii?Q?83CoQA1zVOudUiEE53Mk8gX5psKZheWxWfMiJ3rNnbtLwVGqELGnECV50oQM?= =?us-ascii?Q?QfRQn93lz1O778bPnWCnw8j/52p1lm+xF10UEM58W4ZI1KBN1ClYoCm7N3py?= =?us-ascii?Q?ikZvf9a3aoPgyVKXTLgISTgSG57ZBBfUj+mCvgkDbKTz0NbwVw60rYrGXU85?= =?us-ascii?Q?h7rejEkbBRsFNrsGQg3WwzJMBxehRgukP7urQuIvRZuD583o4l3woUlk+gLU?= =?us-ascii?Q?XregLb4qJQo7SopcLrbWedunyE2oTSBDLZ4EDl+z+0JArzAWnnG6iHJzRWB4?= =?us-ascii?Q?R3qhZ09nJu8CDmDg1kcnHi97zdZPtaLNnwIPl3bd6oMF49tCuhV4Uzke9OfA?= =?us-ascii?Q?G8RaT8vdUk1mWnBGM+kV8w1rG3i4OPf+PKUoeiYUVRyo90CyW68fQ5djH/OV?= =?us-ascii?Q?ptPJTsRXHNH1i9XUw6p3NiGNF15v4GTvLybAe1k8u+uAwgNcddxATVvcqZty?= =?us-ascii?Q?v6Y+FkDNtop3fGP3gKX9VGfL1OPBJZEeAqRFvra+zh5pO7tzeQbL7DtarLED?= =?us-ascii?Q?E5jBgnAdkABV8IUMf2z0fBGoRIJfs3DAetvvEgKQnG5xvmjKMKq9xzjqKcVa?= =?us-ascii?Q?48+7hbUgt6xambEXG6ZZaQl7RkDmHDFCMBrTPXmh9fcxzarE8VKonnnOBj6x?= =?us-ascii?Q?+S0gpeN+U2vbq+x182tk7BRuP7wnwrwJow94IAjlzF3lwMiBFOhvjYijHsvz?= =?us-ascii?Q?OKs9gF0UYPlk8RZARluUXJwuAnWeRhp0apZus17ZkyHy3e+3/KJ1sLbtHw4x?= =?us-ascii?Q?a1EqaB2cDqLGLTJL+mGB1Hi1S2KmDEAGMRo/7H1GIVEfyWviMs/qa9wIROly?= =?us-ascii?Q?UYNfFCKn3TvKGB8Us2RBVB1uAyLE2NTnb0ZUfS/vR3kNfcbAxP7h6atnBiJE?= =?us-ascii?Q?ve96FkR7suk2ZPRxn4V4whgBFaoIZDXqHfmaSA5W2cCds91eQGcjB5zn6TMu?= =?us-ascii?Q?ulYJ9ZHqFSTGPdCdIoa+YlD7jLa4xOKdbvaVQDwCsdNhq3uPpLKe5u1Brk5z?= =?us-ascii?Q?B40jxq8mOhI0CIqbhxVLunjen3K/vVn9rDZR42ItP/aAExFBInpcKbN69r+e?= =?us-ascii?Q?L0rIXZgUOOXpQ7qJ/nkUX9Z4VBa8zMnKZA/oyrw6yagFGvzGJaanOTuriNYq?= =?us-ascii?Q?JNraEbXVbwFden7MW1+lm9x28dOUsXwq9+3sLaI/YqKnQrONFgOsqnuR67xc?= =?us-ascii?Q?rQ=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: ecb3bdf7-aec3-471d-767e-08db2a69e779 X-MS-Exchange-CrossTenant-AuthSource: DS7PR11MB7859.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Mar 2023 00:10:54.9299 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kmVkJpx9uA6GAwQnkRiDg+StxV1p8fGdyVf3XLA5l6M1qd58tF4aGhtEoNb8hedgmqhSrLSIXP7BffcJkkiX925p2nXRlqZghIUlGC+4A3s= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR11MB8096 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH] drm/i915: Make IRQ reset and postinstall multi-gt aware X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni , dri-devel@lists.freedesktop.org, Andi Shyti Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Mar 22, 2023 at 12:20:09AM +0100, Andi Shyti wrote: > From: Paulo Zanoni > > In multitile systems IRQ need to be reset and enabled per GT. At the moment we're not enabling multi-tile support on any platforms yet. Xe_HP SDV has pretty much already served its purpose as an early Xe_HP test platform, and most PVC effort is refocusing on the Xe KMD right now. Note that we don't want/need changes like this on non-tile multi-gt platforms like MTL. The interrupt registers you're accessing here are sgunit registers so there's only ever a single copy of the register on such platforms; looping around and processing the same register two times in a row doesn't accomplish anything that just processing them a single time doesn't. Matt > > Signed-off-by: Paulo Zanoni > Cc: Tvrtko Ursulin > Signed-off-by: Andi Shyti > --- > drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++---------- > 1 file changed, 18 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 31271c30a8cf4..ee4530ec14de3 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2762,14 +2762,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv) > { > struct intel_gt *gt = to_gt(dev_priv); > struct intel_uncore *uncore = gt->uncore; > + unsigned int i; > > dg1_master_intr_disable(dev_priv->uncore.regs); > > - gen11_gt_irq_reset(gt); > - gen11_display_irq_reset(dev_priv); > + for_each_gt(gt, dev_priv, i) { > + gen11_gt_irq_reset(gt); > > - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); > - GEN3_IRQ_RESET(uncore, GEN8_PCU_); > + uncore = gt->uncore; > + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); > + GEN3_IRQ_RESET(uncore, GEN8_PCU_); > + } > + > + gen11_display_irq_reset(dev_priv); > } > > void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, > @@ -3423,13 +3428,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) > > static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) > { > - struct intel_gt *gt = to_gt(dev_priv); > - struct intel_uncore *uncore = gt->uncore; > u32 gu_misc_masked = GEN11_GU_MISC_GSE; > + struct intel_gt *gt; > + unsigned int i; > > - gen11_gt_irq_postinstall(gt); > + for_each_gt(gt, dev_priv, i) { > + gen11_gt_irq_postinstall(gt); > > - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); > + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked, > + gu_misc_masked); > + } > > if (HAS_DISPLAY(dev_priv)) { > icp_irq_postinstall(dev_priv); > @@ -3438,8 +3446,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) > GEN11_DISPLAY_IRQ_ENABLE); > } > > - dg1_master_intr_enable(uncore->regs); > - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); > + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs); > + intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR); > } > > static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) > -- > 2.39.2 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation