From: "Jouni Högander" <jouni.hogander@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v4 2/5] drm/i915/psr: Implement Wa_14015648006
Date: Wed, 22 Mar 2023 12:22:01 +0200 [thread overview]
Message-ID: <20230322102204.116056-3-jouni.hogander@intel.com> (raw)
In-Reply-To: <20230322102204.116056-1-jouni.hogander@intel.com>
PSR WM optimization should be disabled based on any wm level being
disabled. Also same WA should be applied for ICL as well.
Bspec: 71580
v3
- Split patch
v2
- set/clear chicken bit in post_plane_update
- apply for ICL as well
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++++++-
drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++--
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c32bfba06ca1..60504c390408 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1152,6 +1152,7 @@ struct intel_crtc_state {
bool has_psr2;
bool enable_psr2_sel_fetch;
bool req_psr2_sdp_prior_scanline;
+ bool wm_level_disabled;
u32 dc3co_exitline;
u16 su_y_granularity;
struct drm_dp_vsc_sdp psr_vsc;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index e66677e0554b..dfac546d983b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1347,8 +1347,9 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
/*
* Wa_16013835468
+ * Wa_14015648006
*/
- if (DISPLAY_VER(dev_priv) >= 12)
+ if (DISPLAY_VER(dev_priv) >= 11)
intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
wa_16013835468_bit_get(intel_dp), 0);
@@ -1929,6 +1930,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
/*
* Wa_16013835468
+ * Wa_14015648006
*/
static void wm_optimization_wa(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
@@ -1936,6 +1938,11 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
bool set_wa_bit = false;
+ /* Wa_14015648006 */
+ if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ IS_DISPLAY_VER(dev_priv, 11, 13))
+ set_wa_bit |= crtc_state->wm_level_disabled;
+
/* Wa_16013835468 */
if (DISPLAY_VER(dev_priv) >= 12)
set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start !=
@@ -1978,6 +1985,7 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
/*
* Wa_16013835468
+ * Wa_14015648006
*/
wm_optimization_wa(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 50a9a6adbe32..afb751c024ba 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2273,9 +2273,12 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
return level;
/*
- * FIXME PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
+ * PSR needs to toggle LATENCY_REPORTING_REMOVED_PIPE_*
* based on whether we're limited by the vblank duration.
- *
+ */
+ crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
+
+ /*
* FIXME also related to skl+ w/a 1136 (also unimplemented as of
* now) perhaps?
*/
--
2.34.1
next prev parent reply other threads:[~2023-03-22 10:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-22 10:21 [Intel-gfx] [PATCH v4 0/5] High refresh rate PSR fixes Jouni Högander
2023-03-22 10:22 ` [Intel-gfx] [PATCH v4 1/5] drm/i915/psr: Modify/fix Wa_16013835468 and prepare for Wa_14015648006 Jouni Högander
2023-03-22 10:22 ` Jouni Högander [this message]
2023-03-22 10:22 ` [Intel-gfx] [PATCH v4 3/5] drm/i915/psr: Add helpers for block count number handling Jouni Högander
2023-03-22 10:22 ` [Intel-gfx] [PATCH v4 4/5] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
2023-03-22 10:22 ` [Intel-gfx] [PATCH v4 5/5] drm/i915/psr: Implement Display WA #1136 Jouni Högander
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