From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D907C77B6C for ; Fri, 31 Mar 2023 10:19:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C73610F1C0; Fri, 31 Mar 2023 10:18:59 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2185B10F1B5 for ; Fri, 31 Mar 2023 10:18:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680257922; x=1711793922; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u6PoOrHoS9kLHPMhAtesE0vsUdV4iVYLihtAqQtNgxw=; b=Gh017g5DLAiBDCF2qskUJoEH6DoOIuQDTmuTw2eLLWJgoJy1uJ3LG769 WqiGAavR63VaFX5aRSJ+BOSTIrdu5zOnjDe9n05bHAlFJFtZ/TbJgprZm 0B29/7tKoH0j5A5H8tixikPk3Jkt88lyS9TH4f8fgM/6OzM0BJ09UM8wM azknoFZe5kKEdIxL/V+S2Qi6vABjNljSohjvRPUmZA9oJd2XxObrMPvJk EsP3Bc2zhhfwyvirgZ02JnvZMnGwBdQSHLMmMbOAx7ePBnvHOPAJmnkf2 zcxpy1Zo/Wpaxib0lMJo6kt25UwOvSUzDNyqns2n2MvV1xR2mf0424nMb w==; X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="340141801" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="340141801" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2023 03:18:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10665"; a="796068366" X-IronPort-AV: E=Sophos;i="5.98,307,1673942400"; d="scan'208";a="796068366" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Mar 2023 03:18:39 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Fri, 31 Mar 2023 15:46:12 +0530 Message-Id: <20230331101613.936776-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230331101613.936776-1-ankit.k.nautiyal@intel.com> References: <20230331101613.936776-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH 12/13] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a wrapper function to check dp_downstream clock/bandwidth constraints. Based on whether the sink supports FRL/TMDS the wrapper calls the appropriate FRL/TMDS functions. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++-------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 73988e697a0a..63f3f6ff2cad 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1051,6 +1051,18 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock, return MODE_OK; } +static enum drm_mode_status +intel_dp_hdmi_bw_check(struct intel_dp *intel_dp, + int target_clock, int bpc, + enum intel_output_format sink_format, + bool is_frl) +{ + if (is_frl) + return intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); + + return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, sink_format, true); +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -1060,42 +1072,23 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; enum intel_output_format sink_format = intel_dp_sink_format(connector, mode); + bool is_frl = intel_dp->dfp.pcon_max_frl_bw ? true : false; + int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw check */ - /* If PCON supports FRL MODE, check FRL bandwidth constraints */ - if (intel_dp->dfp.pcon_max_frl_bw) { - /* Assume 8bpc for the HDMI2.1 FRL BW check */ - status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); - if (status != MODE_OK) { - if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - !connector->base.ycbcr_420_allowed || - !drm_mode_is_420_also(info, mode)) - return status; - - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); - if (status != MODE_OK) - return status; - } - - return MODE_OK; - } - - if (intel_dp->dfp.max_dotclock && + if (!is_frl && intel_dp->dfp.max_dotclock && target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); + status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl); if (status != MODE_OK) { if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || !connector->base.ycbcr_420_allowed || !drm_mode_is_420_also(info, mode)) return status; + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); + status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl); if (status != MODE_OK) return status; } -- 2.25.1