From: Chris Wilson <chris@chris-wilson.co.uk>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Jani Nikula <jani.nikula@intel.com>,
Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH] drm/i915: drop buggy write to FDI_RX_CHICKEN register
Date: Thu, 15 Nov 2012 10:42:02 +0000 [thread overview]
Message-ID: <275ffc$7dta74@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <1352911659-11757-1-git-send-email-daniel.vetter@ffwll.ch>
On Wed, 14 Nov 2012 17:47:39 +0100, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Jani Nikula noticed that the parentheses are wrong and we & the bit
> with the register address instead of the read-back value. He sent a
> patch to correct that.
>
> On second look, we write the same register in the previous line, and
> the w/a seems to be to set FDI_RX_PHASE_SYNC_POINTER_OVR to enable the
> logic, then keep always set FDI_RX_PHASE_SYNC_POINTER_OVR and toggle
> ~FDI_RX_PHASE_SYNC_POINTER_EN before/after enabling the pc transcoder.
>
> So the right things seems to be to simply kill the 2nd write.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Looks sane(r).
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-11-15 10:42 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-14 16:47 [PATCH] drm/i915: drop buggy write to FDI_RX_CHICKEN register Daniel Vetter
2012-11-15 10:42 ` Chris Wilson [this message]
2012-11-15 13:22 ` Daniel Vetter
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