From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 14/14] drm/i915: Sort EHL/JSL PCI IDs
Date: Thu, 24 Sep 2020 01:04:52 +0000 [thread overview]
Message-ID: <2d27a9a317644ce9be085ae78cc41699@intel.com> (raw)
In-Reply-To: <20200716172106.2656-15-ville.syrjala@linux.intel.com>
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 14/14] drm/i915: Sort EHL/JSL PCI IDs
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Sort the EHL/JSL PCI IDs numerically. Some order seems better than
> randomness.
>
> Cc: Alexei Podtelezhnikov <apodtele@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> include/drm/i915_pciids.h | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 45da1b45c01e..880ffe8571e8 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -585,16 +585,16 @@
> /* EHL/JSL */
> #define INTEL_EHL_IDS(info) \
> INTEL_VGA_DEVICE(0x4500, info), \
> - INTEL_VGA_DEVICE(0x4571, info), \
> - INTEL_VGA_DEVICE(0x4551, info), \
> INTEL_VGA_DEVICE(0x4541, info), \
> - INTEL_VGA_DEVICE(0x4E71, info), \
> - INTEL_VGA_DEVICE(0x4557, info), \
> + INTEL_VGA_DEVICE(0x4551, info), \
> INTEL_VGA_DEVICE(0x4555, info), \
> - INTEL_VGA_DEVICE(0x4E61, info), \
> - INTEL_VGA_DEVICE(0x4E57, info), \
> + INTEL_VGA_DEVICE(0x4557, info), \
> + INTEL_VGA_DEVICE(0x4571, info), \
> + INTEL_VGA_DEVICE(0x4E51, info), \
> INTEL_VGA_DEVICE(0x4E55, info), \
> - INTEL_VGA_DEVICE(0x4E51, info)
> + INTEL_VGA_DEVICE(0x4E57, info), \
> + INTEL_VGA_DEVICE(0x4E61, info), \
> + INTEL_VGA_DEVICE(0x4E71, info)
>
> /* TGL */
> #define INTEL_TGL_12_IDS(info) \
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-09-24 1:04 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-16 17:20 [Intel-gfx] [PATCH 00/14] drm/i915: PCI ID cleanup Ville Syrjala
2020-07-16 17:20 ` [Intel-gfx] [PATCH 01/14] drm/i915: Update Haswell PCI IDs Ville Syrjala
2020-09-23 23:46 ` Srivatsa, Anusha
2020-07-16 17:20 ` [Intel-gfx] [PATCH 02/14] drm/i915: Reclassify SKL 0x192a as GT3 Ville Syrjala
2020-07-16 17:20 ` [Intel-gfx] [PATCH 03/14] drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT Ville Syrjala
2020-09-24 0:32 ` Srivatsa, Anusha
2020-07-16 17:20 ` [Intel-gfx] [PATCH 04/14] drm/i915: Add SKL GT1.5 PCI IDs Ville Syrjala
2020-09-24 0:37 ` Srivatsa, Anusha
2020-09-24 10:46 ` Ville Syrjälä
2020-09-24 17:54 ` Srivatsa, Anusha
2020-07-16 17:20 ` [Intel-gfx] [PATCH 05/14] drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments Ville Syrjala
2020-09-24 0:40 ` Srivatsa, Anusha
2020-07-16 17:20 ` [Intel-gfx] [PATCH 06/14] drm/i915: Ocd the HSW PCI ID hex numbers Ville Syrjala
2020-09-24 0:42 ` Srivatsa, Anusha
2020-07-16 17:20 ` [Intel-gfx] [PATCH 07/14] drm/i915: Sort HSW PCI IDs Ville Syrjala
2020-09-24 0:44 ` Srivatsa, Anusha
2020-07-16 17:21 ` [Intel-gfx] [PATCH 08/14] drm/i915: Sort SKL " Ville Syrjala
2020-09-24 0:49 ` Srivatsa, Anusha
2020-09-24 10:50 ` Ville Syrjälä
2020-07-16 17:21 ` [Intel-gfx] [PATCH 09/14] drm/i915: Sort KBL " Ville Syrjala
2020-09-24 0:50 ` Srivatsa, Anusha
2020-07-16 17:21 ` [Intel-gfx] [PATCH 10/14] drm/i915: Sort CML " Ville Syrjala
2020-09-24 0:53 ` Srivatsa, Anusha
2020-07-16 17:21 ` [Intel-gfx] [PATCH 11/14] drm/i915: Sort CFL " Ville Syrjala
2020-09-24 0:55 ` Srivatsa, Anusha
2020-07-16 17:21 ` [Intel-gfx] [PATCH 12/14] drm/i915: Sort CNL " Ville Syrjala
2020-09-24 0:59 ` Srivatsa, Anusha
2020-07-16 17:21 ` [Intel-gfx] [PATCH 13/14] drm/i915: Sort ICL " Ville Syrjala
2020-09-24 1:01 ` Srivatsa, Anusha
2020-10-23 23:55 ` Lucas De Marchi
2020-07-16 17:21 ` [Intel-gfx] [PATCH 14/14] drm/i915: Sort EHL/JSL " Ville Syrjala
2020-09-24 1:04 ` Srivatsa, Anusha [this message]
2020-07-16 18:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: PCI ID cleanup Patchwork
2020-07-16 18:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-07-16 19:51 ` [Intel-gfx] [PATCH 00/14] " Alexei Podtelezhnikov
2020-07-16 23:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2d27a9a317644ce9be085ae78cc41699@intel.com \
--to=anusha.srivatsa@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).