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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2
Date: Tue, 21 Mar 2023 16:14:57 +0000	[thread overview]
Message-ID: <3949ac3ef5e631323813faac33053d144d02b810.camel@intel.com> (raw)
In-Reply-To: <ZBnQmxYHDiii0FGn@intel.com>

On Tue, 2023-03-21 at 17:43 +0200, Ville Syrjälä wrote:
> On Mon, Mar 20, 2023 at 06:59:44PM +0200, Jouni Högander wrote:
> > Ensure vblank >= psr2 vblank
> > where
> > Psr2 vblank = PSR2_CTL Block Count Number maximum line count.
> > 
> > Bspec: 71580, 49274
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 1050d777a108..1b40d9c73c18 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -958,6 +958,14 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> >                 return false;
> >         }
> >  
> > +       /* Vblank >= PSR2_CTL Block Count Number maximum line count
> > */
> > +       if (crtc_state->hw.adjusted_mode.crtc_vblank_end -
> > +           crtc_state->hw.adjusted_mode.crtc_vblank_start < 12) {
> 
> Why 12? Shouldn't it be based on the wake_lines/BLOCK_COUNT_NUM
> stuff?

I took this directly from Bspec. I think your suggestions make sense. I
will experiment them and come back on this.

> 
> 
> If so I would suggest we try someting like this:
> 
> psr2_block_count_lines()
> {
>         return ...wake_lines... ? 12 : 8;
> }
> 
> psr2_block_count()
> {
>         return psr2_block_count_lines() / 4;
> }
> 
> if (vblank_lengh < psr2_block_count_lines())
>         fail;
> 
> if (psr_block_count() > 2)
>         val |= BLOCK_COUNT_NUM_3;
> else
>         val |= BLOCK_COUNT_NUM_2;
> 
> > +               drm_dbg_kms(&dev_priv->drm,
> > +                           "PSR2 not enabled, too short vblank
> > time\n");
> > +               return false;
> > +       }
> > +
> >         if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> >                 if (!intel_psr2_sel_fetch_config_valid(intel_dp,
> > crtc_state) &&
> >                     !HAS_PSR_HW_TRACKING(dev_priv)) {
> > -- 
> > 2.34.1
> 


  reply	other threads:[~2023-03-21 16:17 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-20 16:59 [Intel-gfx] [PATCH v3 0/4] High refresh rate PSR fixes Jouni Högander
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Unify pre/post hooks Jouni Högander
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Fix Wa_16013835468 and Wa_14015648006 Jouni Högander
2023-03-21 15:34   ` Ville Syrjälä
2023-03-21 15:57     ` Hogander, Jouni
2023-03-21 16:19       ` Ville Syrjälä
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 3/4] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
2023-03-21 15:43   ` Ville Syrjälä
2023-03-21 16:14     ` Hogander, Jouni [this message]
2023-03-21 16:29       ` Ville Syrjälä
2023-03-21 16:41       ` Ville Syrjälä
2023-03-20 16:59 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/psr: Implement Display WA #1136 Jouni Högander
2023-03-21  5:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for High refresh rate PSR fixes (rev3) Patchwork
2023-03-21  5:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-21  5:24 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-21  5:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-21  9:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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