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dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 885796EE5F; Thu, 27 May 2021 10:22:21 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA0156EE5C; Thu, 27 May 2021 10:22:19 +0000 (UTC) IronPort-SDR: v3UP0Nq9AD262HC2MxfuYQ1H1SYYLr4MyNaPWHy1lf8kc/FsTpe9hP1Zh+YSPzsq72RIURWdei VvHsly0SddQg== X-IronPort-AV: E=McAfee;i="6200,9189,9996"; a="199659559" X-IronPort-AV: E=Sophos;i="5.82,334,1613462400"; d="scan'208";a="199659559" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2021 03:22:19 -0700 IronPort-SDR: GabBH7TXNyR6z0rC3m7bcUPmghmdih0AgU1O4ujV3vnwy7LV1YihlSA8gMkD/9y8Ct3MayAu6i JkCvuKPWGARg== X-IronPort-AV: E=Sophos;i="5.82,334,1613462400"; d="scan'208";a="547745264" Received: from amoses-mobl1.ger.corp.intel.com (HELO [10.213.211.53]) ([10.213.211.53]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2021 03:22:18 -0700 To: Daniel Vetter References: <20210525135508.244659-1-tejaskumarx.surendrakumar.upadhyay@intel.com> <20210525135508.244659-2-tejaskumarx.surendrakumar.upadhyay@intel.com> <8cf2c5f4-87a3-ce6b-150c-65fa054586a4@linux.intel.com> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc Message-ID: <59d2eee9-35c1-01fc-c226-50ad98aadb99@linux.intel.com> Date: Thu, 27 May 2021 11:22:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH 1/1] Let userspace know if they can trust timeslicing by including it as part of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, DRI Development , mahesh.meena@intel.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 27/05/2021 11:13, Daniel Vetter wrote: > On Wed, May 26, 2021 at 11:20:13AM +0100, Tvrtko Ursulin wrote: >> >> On 25/05/2021 15:47, Daniel Vetter wrote: >>> On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote: >>>> >>>> + dri-devel as per process >>>> >>>> On 25/05/2021 14:55, Tejas Upadhyay wrote: >>>>> v2: Only declare timeslicing if we can safely preempt userspace. >>>> >>>> Commit message got butchered up somehow so you'll need to fix that at some >>>> point. >>>> >>>> Regards, >>>> >>>> Tvrtko >>>> >>>>> Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing") >>>>> Signed-off-by: Chris Wilson >>>>> Cc: Tvrtko Ursulin >>>>> Reviewed-by: Tvrtko Ursulin >>>>> --- >>>>> drivers/gpu/drm/i915/gt/intel_engine_user.c | 1 + >>>>> include/uapi/drm/i915_drm.h | 1 + >>>>> 2 files changed, 2 insertions(+) >>>>> >>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>> index 3cca7ea2d6ea..12d165566ed2 100644 >>>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c >>>>> @@ -98,6 +98,7 @@ static void set_scheduler_caps(struct drm_i915_private *i915) >>>>> MAP(HAS_PREEMPTION, PREEMPTION), >>>>> MAP(HAS_SEMAPHORES, SEMAPHORES), >>>>> MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS), >>>>> + MAP(TIMESLICE_BIT, TIMESLICING), >>>>> #undef MAP >>>>> }; >>>>> struct intel_engine_cs *engine; >>>>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h >>>>> index c2c7759b7d2e..af2212d6113c 100644 >>>>> --- a/include/uapi/drm/i915_drm.h >>>>> +++ b/include/uapi/drm/i915_drm.h >>>>> @@ -572,6 +572,7 @@ typedef struct drm_i915_irq_wait { >>>>> #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) >>>>> #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) >>>>> #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) >>>>> +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5) >>> >>> Since this is uapi I think we should at least have some nice kerneldoc >>> that explains what exactly this is, what for (link to userspace) and all >>> that. Ideally also minimally filing in the gaps in our uapi docs for stuff >>> this references. >> >> IIUC there is no userspace apart from IGT needing it not to fail scheduling >> tests on ADL. >> >> Current tests use "has preemption + has semaphores" as a proxy to answer the >> "does the kernel support timeslicing" question. This stops working with the >> Guc backend because GuC decided not to support semaphores (for reasons yet >> unknown, see other thread), so explicit "has timeslicing" flag is needed in >> order for tests to know that GuC is supposed to support timeslicing, even if >> it doesn't use semaphores for inter-ring synchronisation. > > Since this if for igt only: Cant we do just extend the check in igt with > an || GEN >= 12? I really hope that our future hw will continue to support > timeslicing ... Not the gen 12 check, but possible I think. Explicit feature test would be better, but if definitely not allowed then along the lines of: has_timeslicing = (has_preemption && has_semaphores) || uses_guc_submission; Regards, Tvrtko > Also if it's not there yet, a shared helper to check for that (like we're > adding for relocations and stuff like that right now). > -Daniel > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx