From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Matthew Auld <matthew.auld@intel.com>, intel-gfx@lists.freedesktop.org
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
dri-devel@lists.freedesktop.org,
"Kenneth Graunke" <kenneth@whitecape.org>,
"Daniel Vetter" <daniel.vetter@ffwll.ch>
Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/uapi: reject set_domain for discrete
Date: Fri, 16 Jul 2021 15:52:46 +0100 [thread overview]
Message-ID: <70159117-ca97-667a-3e9b-82125bf309df@linux.intel.com> (raw)
In-Reply-To: <20210715101536.2606307-5-matthew.auld@intel.com>
On 15/07/2021 11:15, Matthew Auld wrote:
> The CPU domain should be static for discrete, and on DG1 we don't need
> any flushing since everything is already coherent, so really all this
> does is an object wait, for which we have an ioctl. Longer term the
> desired caching should be an immutable creation time property for the
> BO, which can be set with something like gem_create_ext.
>
> One other user is iris + userptr, which uses the set_domain to probe all
> the pages to check if the GUP succeeds, however we now have a PROBE
> flag for this purpose.
>
> v2: add some more kernel doc, also add the implicit rules with caching
>
> Suggested-by: Daniel Vetter <daniel@ffwll.ch>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
> include/uapi/drm/i915_drm.h | 19 +++++++++++++++++++
> 2 files changed, 22 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> index 43004bef55cb..b684a62bf3b0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> @@ -490,6 +490,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
> u32 write_domain = args->write_domain;
> int err;
>
> + if (IS_DGFX(to_i915(dev)))
> + return -ENODEV;
> +
> /* Only handle setting domains to types used by the CPU. */
> if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
> return -EINVAL;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 2e4112bf4d38..04ce310e7ee6 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -901,6 +901,25 @@ struct drm_i915_gem_mmap_offset {
> * - I915_GEM_DOMAIN_GTT: Mappable aperture domain
> *
> * All other domains are rejected.
> + *
> + * Note that for discrete, starting from DG1, this is no longer supported, and
> + * is instead rejected. On such platforms the CPU domain is effectively static,
> + * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
> + * which can't be set explicitly and instead depends on the object placements,
> + * as per the below.
> + *
> + * Implicit caching rules, starting from DG1:
> + *
> + * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
> + * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
> + * mapped as write-combined only.
A note about write-combine buffer? I guess saying it is userspace
responsibility to do it and how.
> + *
> + * - Everything else is always allocated and mapped as write-back, with the
> + * guarantee that everything is also coherent with the GPU.
Haven't been following this so just a question on this one - it is not
considered interesting to offer non-coherent modes, or even write
combine, with system memory buffers, for a specific reason?
Regards,
Tvrtko
> + *
> + * Note that this is likely to change in the future again, where we might need
> + * more flexibility on future devices, so making this all explicit as part of a
> + * new &drm_i915_gem_create_ext extension is probable.
> */
> struct drm_i915_gem_set_domain {
> /** @handle: Handle for the object. */
>
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next prev parent reply other threads:[~2021-07-16 14:52 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-15 10:15 [Intel-gfx] [PATCH 0/4] Some DG1 uAPI cleanup Matthew Auld
2021-07-15 10:15 ` [Intel-gfx] [PATCH 1/4] drm/i915/uapi: reject caching ioctls for discrete Matthew Auld
2021-07-15 10:15 ` [Intel-gfx] [PATCH 2/4] drm/i915/uapi: convert drm_i915_gem_userptr to kernel doc Matthew Auld
2021-07-15 12:09 ` Maarten Lankhorst
2021-07-15 10:15 ` [Intel-gfx] [PATCH 3/4] drm/i915/userptr: Probe existence of backing struct pages upon creation Matthew Auld
2021-07-15 10:33 ` Tvrtko Ursulin
2021-07-15 11:07 ` Daniel Vetter
2021-07-15 11:27 ` Tvrtko Ursulin
2021-07-15 18:21 ` Kenneth Graunke
2021-07-15 19:18 ` Jason Ekstrand
2021-07-16 8:20 ` Tvrtko Ursulin
2021-07-16 14:50 ` Daniel Vetter
2021-07-15 11:09 ` Matthew Auld
2021-07-15 11:33 ` Tvrtko Ursulin
2021-07-16 14:36 ` Tvrtko Ursulin
2021-07-21 19:18 ` Kenneth Graunke
2021-07-21 19:21 ` Kenneth Graunke
2021-07-21 20:27 ` Jason Ekstrand
2021-07-22 8:43 ` Matthew Auld
2021-07-22 13:29 ` Jason Ekstrand
2021-07-15 10:15 ` [Intel-gfx] [PATCH 4/4] drm/i915/uapi: reject set_domain for discrete Matthew Auld
2021-07-16 14:52 ` Tvrtko Ursulin [this message]
2021-07-16 15:23 ` Jason Ekstrand
2021-07-19 9:00 ` Tvrtko Ursulin
2021-07-19 9:09 ` Matthew Auld
2021-07-19 19:57 ` Jason Ekstrand
2021-07-16 19:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Some DG1 uAPI cleanup Patchwork
2021-07-17 1:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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