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* [Intel-gfx] [PATCH 00/37] Introduce DG1
@ 2020-05-21  0:37 Lucas De Marchi
  2020-05-21  0:37 ` [Intel-gfx] [PATCH 01/37] drm/i915/rkl: Add DPLL4 support Lucas De Marchi
                   ` (40 more replies)
  0 siblings, 41 replies; 56+ messages in thread
From: Lucas De Marchi @ 2020-05-21  0:37 UTC (permalink / raw)
  To: intel-gfx; +Cc: fernando.pacheco, Matthew Auld

DG1 is a gen12 dgfx platform. This is the first batch of patches to
support it. It also depends on some in-flight patches adding RKL. In
order for this series to be compiled, I'm including them here.

While converting some of these patches to the current
intel_uncore/intel_de APIs I thought it could be useful to return the
previous value. The patch for that is included here, but I ended up
not using and it can be dropped if there is no interest.

Abdiel Janulgue (2):
  drm/i915/dg1: add initial DG-1 definitions
  drm/i915/dg1: Add DG1 PCI IDs

Aditya Swarup (4):
  drm/i915/dg1: Add DPLL macros for DG1
  drm/i915/dg1: Add and setup DPLLs for DG1
  drm/i915/dg1: Enable DPLL for DG1
  drm/i915/dg1: Enable first 2 ports for DG1

Anusha Srivatsa (1):
  drm/i915/dg1: Remove SHPD_FILTER_CNT register programming

Clinton A Taylor (1):
  drm/i915/dg1: invert HPD pins

Fernando Pacheco (2):
  drm/i915/dg1: Handle GRF/IC ECC error irq
  drm/i915/dg1: Log counter on SLM ECC error

Lucas De Marchi (9):
  drm/i915/rkl: provide port/phy mapping for vbt
  drm/i915: make intel_{uncore,de}_rmw() more useful
  drm/i915/dg1: Add fake PCH
  drm/i915/dg1: Define MOCS table for DG1
  drm/i915/dg1: add support for the master unit interrupt
  drm/i915/dg1: add hpd interrupt handling
  drm/i915/dg1: gmbus pin mapping
  drm/i915/dg1: map/unmap pll clocks
  drm/i915/dg1: enable PORT C/D aka D/E

Matt Atwood (1):
  drm/i915/dg1: Load DMC

Matt Roper (12):
  drm/i915/rkl: Add DPLL4 support
  drm/i915/rkl: Add DDC pin mapping
  drm/i915/rkl: Setup ports/phys
  drm/i915/rkl: Handle HTI
  drm/i915/rkl: Handle comp master/slave relationships for PHYs
  drm/i915/rkl: Add initial workarounds
  drm/i915/dg1: Initialize RAWCLK properly
  drm/i915/dg1: Wait for pcode/uncore handshake at startup
  drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
  drm/i915/dg1: Update comp master/slave relationships for PHYs
  drm/i915/dg1: Update voltage swing tables for DP
  drm/i915/dg1: provide port/phy mapping for vbt

Matthew Auld (1):
  drm/i915: add pcie snoop flag

Stuart Summers (2):
  drm/i915: Add has_master_unit_irq flag
  drm/i915/dg1: Add initial DG1 workarounds

Uma Shankar (1):
  drm/i915/dg1: Add DG1 power wells

Venkata Sandeep Dhanalakota (1):
  drm/i915/dg1: Increase mmio size to 4MB

 drivers/gpu/drm/i915/display/intel_bios.c     |  78 ++++--
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  15 ++
 .../gpu/drm/i915/display/intel_combo_phy.c    |  28 +-
 drivers/gpu/drm/i915/display/intel_csr.c      |  19 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 126 ++++++++-
 drivers/gpu/drm/i915/display/intel_de.h       |   4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  94 ++++++-
 .../drm/i915/display/intel_display_power.c    | 206 ++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 117 ++++++--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  18 ++
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  15 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |  29 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |   5 +-
 drivers/gpu/drm/i915/gem/i915_gem_userptr.c   |   3 +-
 drivers/gpu/drm/i915/gt/intel_mocs.c          |  39 ++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 159 ++++++++---
 drivers/gpu/drm/i915/i915_debugfs.c           |   4 +
 drivers/gpu/drm/i915/i915_drv.c               |   3 +
 drivers/gpu/drm/i915/i915_drv.h               |  13 +
 drivers/gpu/drm/i915/i915_irq.c               | 249 +++++++++++++++++-
 drivers/gpu/drm/i915/i915_pci.c               |  16 +-
 drivers/gpu/drm/i915/i915_reg.h               | 110 +++++++-
 drivers/gpu/drm/i915/intel_device_info.c      |   1 +
 drivers/gpu/drm/i915/intel_device_info.h      |   3 +
 drivers/gpu/drm/i915/intel_pch.c              |   6 +
 drivers/gpu/drm/i915/intel_pch.h              |   4 +
 drivers/gpu/drm/i915/intel_pm.c               |  17 +-
 drivers/gpu/drm/i915/intel_sideband.c         |  15 ++
 drivers/gpu/drm/i915/intel_sideband.h         |   2 +
 drivers/gpu/drm/i915/intel_uncore.c           |   4 +
 drivers/gpu/drm/i915/intel_uncore.h           |  10 +-
 include/drm/i915_pciids.h                     |   4 +
 32 files changed, 1285 insertions(+), 131 deletions(-)

-- 
2.26.2

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^ permalink raw reply	[flat|nested] 56+ messages in thread

end of thread, other threads:[~2020-05-26 18:10 UTC | newest]

Thread overview: 56+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-21  0:37 [Intel-gfx] [PATCH 00/37] Introduce DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 01/37] drm/i915/rkl: Add DPLL4 support Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 02/37] drm/i915/rkl: Add DDC pin mapping Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 03/37] drm/i915/rkl: Setup ports/phys Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 04/37] drm/i915/rkl: provide port/phy mapping for vbt Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 05/37] drm/i915/rkl: Handle HTI Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 06/37] drm/i915/rkl: Handle comp master/slave relationships for PHYs Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 07/37] drm/i915/rkl: Add initial workarounds Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 08/37] drm/i915: make intel_{uncore, de}_rmw() more useful Lucas De Marchi
2020-05-21 17:24   ` Souza, Jose
2020-05-21 17:30     ` Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 09/37] drm/i915: Add has_master_unit_irq flag Lucas De Marchi
2020-05-26 18:10   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 10/37] drm/i915: add pcie snoop flag Lucas De Marchi
2020-05-21  8:15   ` Chris Wilson
2020-05-21  0:37 ` [Intel-gfx] [PATCH 11/37] drm/i915/dg1: add initial DG-1 definitions Lucas De Marchi
2020-05-26 17:34   ` Souza, Jose
2020-05-26 17:51     ` Lucas De Marchi
2020-05-26 18:02       ` Souza, Jose
2020-05-26 17:51   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 12/37] drm/i915/dg1: Add DG1 PCI IDs Lucas De Marchi
2020-05-26 17:35   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 13/37] drm/i915/dg1: Add fake PCH Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 14/37] drm/i915/dg1: Initialize RAWCLK properly Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 15/37] drm/i915/dg1: Define MOCS table for DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 16/37] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 17/37] drm/i915/dg1: Increase mmio size to 4MB Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 18/37] drm/i915/dg1: add support for the master unit interrupt Lucas De Marchi
2020-05-26 18:02   ` Souza, Jose
2020-05-21  0:37 ` [Intel-gfx] [PATCH 19/37] drm/i915/dg1: Wait for pcode/uncore handshake at startup Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 20/37] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 21/37] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 22/37] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 23/37] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 24/37] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 25/37] drm/i915/dg1: gmbus pin mapping Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 26/37] drm/i915/dg1: Handle GRF/IC ECC error irq Lucas De Marchi
2020-05-21  8:19   ` Chris Wilson
2020-05-21  0:37 ` [Intel-gfx] [PATCH 27/37] drm/i915/dg1: Log counter on SLM ECC error Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 28/37] drm/i915/dg1: Enable first 2 ports for DG1 Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 29/37] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 30/37] drm/i915/dg1: Update comp master/slave relationships for PHYs Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 31/37] drm/i915/dg1: Update voltage swing tables for DP Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 32/37] drm/i915/dg1: provide port/phy mapping for vbt Lucas De Marchi
2020-05-21  0:37 ` [Intel-gfx] [PATCH 33/37] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 34/37] drm/i915/dg1: enable PORT C/D aka D/E Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 35/37] drm/i915/dg1: Load DMC Lucas De Marchi
2020-05-26 17:42   ` Souza, Jose
2020-05-26 17:49     ` Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 36/37] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-05-21  0:38 ` [Intel-gfx] [PATCH 37/37] drm/i915/dg1: Remove SHPD_FILTER_CNT register programming Lucas De Marchi
2020-05-26 17:44   ` Souza, Jose
2020-05-21  1:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-05-21  1:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-05-21  1:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-21 18:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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