From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence Date: Wed, 13 Apr 2011 22:37:50 +0100 Message-ID: <849307$cfb25f@azsmga001.ch.intel.com> References: <1302640318-23165-1-git-send-email-chris@chris-wilson.co.uk> <1302640318-23165-27-git-send-email-chris@chris-wilson.co.uk> <20110413193702.GH3660@viiv.ffwll.ch> <20110413205825.GP3660@viiv.ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id B6D809E74D for ; Wed, 13 Apr 2011 14:38:07 -0700 (PDT) In-Reply-To: <20110413205825.GP3660@viiv.ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 13 Apr 2011 22:58:26 +0200, Daniel Vetter wrote: > Just add a small comment in the commit msg that it essentially disables > that optimization, in case somebody bisects a performance regression to > this. Noted. But a bisect will never land here. Because I've left something out of this patch series until gem_stress is my friend... In applying this fix for a corruption bug, we do lose the ability to detect the earliest end of GPU fenced access, thus disabling the inherent optimization. -Chris -- Chris Wilson, Intel Open Source Technology Centre