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From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Andy Whitcroft <apw@canonical.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 29/30] drm/i915: Track fence setup separately from fenced object lifetime
Date: Wed, 13 Apr 2011 22:56:57 +0100
Message-ID: <849307$cfbct3@azsmga001.ch.intel.com> (raw)
In-Reply-To: <20110413204222.GK3660@viiv.ffwll.ch>

On Wed, 13 Apr 2011 22:42:23 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Apr 12, 2011 at 09:31:57PM +0100, Chris Wilson wrote:
> > This fixes a bookkeeping error causing an OOPS whilst waiting for an
> > object to finish using a fence. Now we can simply wait for the fence to
> > be written independent of the objects currently inhabiting it (past,
> > present and future).
> > 
> > A large amount of the change is to delay updating the information about
> > the fence on bo until after we successfully write, or queue the write to,
> > the register. This avoids the complication of undoing a partial change
> > should we fail in pipelining the change.
> > 
> > Cc: Andy Whitcroft <apw@canonical.com>
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> I think that r-b is stale ;-) Still holds though for the general idea. A
> few nitpicks below.

Meh, reviewers are fickle. I'm pretty sure I have not changed the code
from since the last time I put it in front of you. Much. ;-)

> On general comment: I think we should get completely rid of
> last_fenced_ring. There should be no way an object can change rings
> without being at least completely flushed (or even going through the
> inactive list).  Maybe that's for a separate patch but I'm slightly uneasy
> with the fact that we don't seem to systematically clear last_fenced_ring
> _anywhere_.

Ah. That was to make sure you were paying attention. last_fenced_seqno was
the guard.

last_fenced_ring is the complexity that holds it all together sadly. Every
time I try to eliminate it, I keep coming back to it as the cleanest
solution.

> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index ca14a86..1949048 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -1731,6 +1731,8 @@ i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
> >  	i915_gem_object_move_off_active(obj);
> >  	obj->fenced_gpu_access = false;
> >  
> > +	obj->last_fenced_seqno = 0;
> > +
> 
> I think we could move that to move_off_active where last_rendering_seqno
> is being reset. Would be slightly more consistent. Resetting
> last_fenced_ring together with last_fenced_seqno probably makes sens, too.

Right, the choice of setting last_fenced_seqno to 0 in move_off_active() or
move_to_inactive() doesn't impact upon flush_fence.

> > @@ -2675,47 +2661,43 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
> >  	if (reg == NULL)
> >  		return -ENOSPC;
> >  
> > -	ret = i915_gem_object_flush_fence(obj, pipelined);
> > -	if (ret)
> > -		return ret;
> > -
> > -	if (reg->obj) {
> > -		struct drm_i915_gem_object *old = reg->obj;
> > -
> > +	if ((old = reg->obj)) {
> 
> Argh. Can you move the assignment out?

Must remember to use this trick of point in eyesores to distract from the
rest of the code!

> > @@ -2732,7 +2714,31 @@ update:
> >  		ret = i830_write_fence_reg(obj, pipelined, regnum);
> >  		break;
> >  	}
> > +	if (ret)
> > +		goto err;
> > +
> > +	if (pipelined) {
> > +		reg->setup_seqno = i915_gem_next_request_seqno(pipelined);
> > +		reg->setup_ring = pipelined;
> > +		if (old) {
> > +			old->last_fenced_ring = pipelined;
> > +			old->last_fenced_seqno = reg->setup_seqno;
> > +		}
> 
> This looks superfluous. flush_fence should take care of this either
> directly or via flush_ring -> process_flushing_list -> move_to_active.
> If it's just paranoia, can this be converted to a WARN_ON? Or is this
> closing a gap I'm not seeing?

Oh, this is absolutely vital. Too tired, and this is definitely one that
has to be explained whilst fresh.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

  reply index

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-04-12 20:31 i915 next Chris Wilson
2011-04-12 20:31 ` [PATCH 01/30] drm/i915: Split the crtc_mode_set function along HAS_PCH_SPLIT() lines Chris Wilson
2011-04-12 20:31 ` [PATCH 02/30] drm/i915: Move the vblank pre/post modeset to the common crtc_mode_set Chris Wilson
2011-04-12 20:31 ` [PATCH 03/30] drm/i915: Remove the PCH paths from the pre-Ironlake crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 04/30] drm/i915: Drop the eDP paths from the pre-Ironlake crtc_mode_set Chris Wilson
2011-04-12 20:31 ` [PATCH 05/30] drm/i915: Drop the remaining bit of Ironlake code from i9xx_crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 06/30] drm/i915: Drop non-HAS_PCH_SPLIT() code from ironlake_crtc_mode_set() Chris Wilson
2011-04-12 20:31 ` [PATCH 07/30] drm/i915: Drop remaining pre-Ironlake " Chris Wilson
2011-04-12 20:31 ` [PATCH 08/30] drm/i915: Clean up leftover DPLL and LVDS register choice from pch split Chris Wilson
2011-04-12 20:31 ` [PATCH 09/30] drm/i915: Fold the DPLL limit defines into the structs that use them Chris Wilson
2011-04-12 20:31 ` [PATCH 10/30] drm/i915: fix ilk rc6 teardown locking Chris Wilson
2011-04-12 20:31 ` [PATCH 11/30] drm/1915: ringbuffer wait for idle function Chris Wilson
2011-04-12 20:31 ` [PATCH 12/30] drm/i915: fix rc6 initialization on Ironlake Chris Wilson
2011-04-12 20:31 ` [PATCH 13/30] drm/i915: re-enable rc6 for ironlake Chris Wilson
2011-04-12 20:31 ` [PATCH 14/30] drm/i915: use i915_enable_rc6 on SNB too Chris Wilson
2011-04-12 20:31 ` [PATCH 15/30] drm/i915: Rename agp_type to cache_level Chris Wilson
2011-04-13 15:57   ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 16/30] drm/i915: Mark the cursor and the overlay as being part of the display planes Chris Wilson
2011-04-13 16:00   ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 17/30] drm/i915: Do not clflush snooped objects Chris Wilson
2011-04-13 16:04   ` Daniel Vetter
2011-04-13 17:34     ` Chris Wilson
2011-04-13 20:47       ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 18/30] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-13 18:59   ` Daniel Vetter
2011-04-13 19:21     ` Chris Wilson
2011-04-13 22:27     ` [PATCH 1/3] drm/i915: Introduce i915_gem_object_finish_gpu() Chris Wilson
2011-04-13 22:27       ` [PATCH 2/3] drm/i915: Introduce i915_gem_object_finish_gtt() Chris Wilson
2011-04-13 22:27       ` [PATCH 3/3] drm/i915: Add an interface to dynamically change the cache level Chris Wilson
2011-04-12 20:31 ` [PATCH 19/30] drm/i915: Use the uncached domain for the display planes v2 Chris Wilson
2011-04-12 20:31 ` [PATCH 20/30] drm/i915: Use the CPU domain for snooped pwrites Chris Wilson
2011-04-12 20:31 ` [PATCH 21/30] drm/i915: Redirect GTT mappings to the CPU page if cache-coherent Chris Wilson
2011-04-13 15:57   ` Eric Anholt
2011-04-13 16:19     ` Chris Wilson
2011-04-13 18:35     ` [PATCH] " Chris Wilson
2011-04-13 19:13       ` Daniel Vetter
2011-04-13 19:47         ` Chris Wilson
2011-04-13 20:26         ` [PATCH] drm/i915: Prevent mmap access through the GTT of snooped pages Chris Wilson
2011-04-13 20:51           ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 22/30] drm/i915: Use the LLC mode on gen6 for everything but display Chris Wilson
2011-04-13 19:15   ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 23/30] drm/i915: Cache GT fifo count for SandyBridge Chris Wilson
2011-04-14  2:21   ` Ben Widawsky
2011-04-14  4:48     ` Ben Widawsky
2011-04-12 20:31 ` [PATCH 24/30] drm/i915: Refactor pwrite/pread to use single copy of get_user_pages Chris Wilson
2011-04-13 15:59   ` Eric Anholt
2011-04-13 17:24     ` Chris Wilson
2011-04-13 19:35       ` Eric Anholt
2011-04-13 19:26   ` Daniel Vetter
2011-04-13 19:56     ` Chris Wilson
2011-04-13 20:56       ` Daniel Vetter
2011-04-14 23:23       ` Ben Widawsky
2011-04-15  9:48         ` Paul Menzel
2011-04-16  8:03           ` Chris Wilson
2011-04-12 20:31 ` [PATCH 25/30] drm/i915: s/addr & ~PAGE_MASK/offset_in_page(addr)/ Chris Wilson
2011-04-12 20:31 ` [PATCH 26/30] drm/i915: Maintain fenced gpu access until we flush the fence Chris Wilson
2011-04-13 19:37   ` Daniel Vetter
2011-04-13 20:15     ` Chris Wilson
2011-04-13 20:58       ` Daniel Vetter
2011-04-13 21:37         ` Chris Wilson
2011-04-12 20:31 ` [PATCH 27/30] drm/i915: Invalidate fenced read domains upon flush Chris Wilson
2011-04-13 19:43   ` Daniel Vetter
2011-04-13 20:38     ` Chris Wilson
2011-04-13 21:02       ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 28/30] drm/i915: Pass the fence register number to be written Chris Wilson
2011-04-13 19:48   ` Daniel Vetter
2011-04-12 20:31 ` [PATCH 29/30] drm/i915: Track fence setup separately from fenced object lifetime Chris Wilson
2011-04-13 20:42   ` Daniel Vetter
2011-04-13 21:56     ` Chris Wilson [this message]
2011-04-12 20:31 ` [PATCH 30/30] drm/i915: Only print out the actual number of fences for i915_error_state Chris Wilson
2011-04-13  7:26 ` i915 next Chris Wilson

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