From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1C1AC433E1 for ; Tue, 2 Jun 2020 09:08:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B2A2F207D5 for ; Tue, 2 Jun 2020 09:08:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B2A2F207D5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 45E8389916; Tue, 2 Jun 2020 09:08:13 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C68389916 for ; Tue, 2 Jun 2020 09:08:12 +0000 (UTC) IronPort-SDR: hviBoI87/ylhv34ncvMUfmYJCF87UkFWG7LMKJC46WBjmNhacbZ0PGfeNR8ffre11fK/GfR8SY hHSuZMbpenYA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2020 02:08:11 -0700 IronPort-SDR: u8+P14YRNMVcg3hEHrtEvPnK7lP4HO3pmnIo236ZBreo41tL0akoWyLAChl0Ut0Y0Ttj7aEIGM llh/J5+YzR9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,463,1583222400"; d="scan'208";a="268636571" Received: from gaia.fi.intel.com ([10.237.72.192]) by orsmga003.jf.intel.com with ESMTP; 02 Jun 2020 02:08:10 -0700 Received: by gaia.fi.intel.com (Postfix, from userid 1000) id 97BD15C2C64; Tue, 2 Jun 2020 12:05:42 +0300 (EEST) From: Mika Kuoppala To: Chris Wilson , intel-gfx@lists.freedesktop.org In-Reply-To: <20200601072446.19548-3-chris@chris-wilson.co.uk> References: <20200601072446.19548-1-chris@chris-wilson.co.uk> <20200601072446.19548-3-chris@chris-wilson.co.uk> Date: Tue, 02 Jun 2020 12:05:42 +0300 Message-ID: <874krtj0rd.fsf@gaia.fi.intel.com> MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH 03/36] drm/i915/gt: Move legacy context wa to intel_workarounds X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Chris Wilson writes: > Use the central mechanism for recording and verifying that we restore > the w/a for the older devices as well. > > Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala > --- > .../gpu/drm/i915/gt/intel_ring_submission.c | 28 ----------------- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 31 +++++++++++++++++++ > 2 files changed, 31 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 96881cd8b17b..d9c1701061b9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -429,32 +429,6 @@ static void reset_finish(struct intel_engine_cs *engine) > { > } > > -static int rcs_resume(struct intel_engine_cs *engine) > -{ > - struct drm_i915_private *i915 = engine->i915; > - struct intel_uncore *uncore = engine->uncore; > - > - /* > - * Disable CONSTANT_BUFFER before it is loaded from the context > - * image. For as it is loaded, it is executed and the stored > - * address may no longer be valid, leading to a GPU hang. > - * > - * This imposes the requirement that userspace reload their > - * CONSTANT_BUFFER on every batch, fortunately a requirement > - * they are already accustomed to from before contexts were > - * enabled. > - */ > - if (IS_GEN(i915, 4)) > - intel_uncore_write(uncore, ECOSKPD, > - _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE)); > - > - if (IS_GEN_RANGE(i915, 6, 7)) > - intel_uncore_write(uncore, INSTPM, > - _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); > - > - return xcs_resume(engine); > -} > - > static void reset_cancel(struct intel_engine_cs *engine) > { > struct i915_request *request; > @@ -1139,8 +1113,6 @@ static void setup_rcs(struct intel_engine_cs *engine) > > if (IS_HASWELL(i915)) > engine->emit_bb_start = hsw_emit_bb_start; > - > - engine->resume = rcs_resume; > } > > static void setup_vcs(struct intel_engine_cs *engine) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index fa1e15657663..94d66a9d760d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -199,6 +199,18 @@ wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) > #define WA_SET_FIELD_MASKED(addr, mask, value) \ > wa_write_masked_or(wal, (addr), 0, _MASKED_FIELD((mask), (value))) > > +static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, > + struct i915_wa_list *wal) > +{ > + WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); > +} > + > +static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, > + struct i915_wa_list *wal) > +{ > + WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); > +} > + > static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, > struct i915_wa_list *wal) > { > @@ -638,6 +650,10 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, > chv_ctx_workarounds_init(engine, wal); > else if (IS_BROADWELL(i915)) > bdw_ctx_workarounds_init(engine, wal); > + else if (IS_GEN(i915, 7)) > + gen7_ctx_workarounds_init(engine, wal); > + else if (IS_GEN(i915, 6)) > + gen6_ctx_workarounds_init(engine, wal); > else if (INTEL_GEN(i915) < 8) > return; > else > @@ -1583,6 +1599,21 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > 0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH), > /* XXX bit doesn't stick on Broadwater */ > IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH); > + > + if (IS_GEN(i915, 4)) > + /* > + * Disable CONSTANT_BUFFER before it is loaded from the context > + * image. For as it is loaded, it is executed and the stored > + * address may no longer be valid, leading to a GPU hang. > + * > + * This imposes the requirement that userspace reload their > + * CONSTANT_BUFFER on every batch, fortunately a requirement > + * they are already accustomed to from before contexts were > + * enabled. > + */ > + wa_add(wal, ECOSKPD, > + 0, _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE), > + 0 /* XXX bit doesn't stick on Broadwater */); > } > > static void > -- > 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx