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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Jesse Barnes <jbarnes@virtuousgeek.org>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 20/22] drm/i915: add Punit read/write routines for VLV
Date: Tue, 05 Feb 2013 19:44:48 +0200
Message-ID: <87boby3ban.fsf@intel.com> (raw)
In-Reply-To: <1359809786-26434-21-git-send-email-jbarnes@virtuousgeek.org>

On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Slightly different than other platforms.

I'll do more review later, just pointing out an obvious bug below.

BR,
Jani.


>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |    2 ++
>  drivers/gpu/drm/i915/i915_reg.h |   22 ++++++++++++
>  drivers/gpu/drm/i915/intel_pm.c |   74 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 98 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 34f01a9..60eee7d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1749,6 +1749,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
>  
>  int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
>  int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
> +int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
>  
>  #define __i915_read(x, y) \
>  	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e13f34..7325b7a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4335,6 +4335,28 @@
>  #define GEN6_PCODE_DATA				0x138128
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  
> +#define VLV_IOSF_DOORBELL_REQ			0x182100
> +#define   IOSF_DEVFN_SHIFT			24
> +#define   IOSF_OPCODE_SHIFT			16
> +#define   IOSF_PORT_SHIFT			8
> +#define   IOSF_BYTE_ENABLES_SHIFT		4
> +#define   IOSF_BAR_SHIFT			1
> +#define   IOSF_SB_BUSY				(1<<0)
> +#define   IOSF_PORT_PUNIT			0x4
> +#define VLV_IOSF_DATA				0x182104
> +#define VLV_IOSF_ADDR				0x182108
> +
> +#define PUNIT_REG_GPU_LFM			0xd3
> +#define PUNIT_REG_GPU_FREQ_REQ			0xd4
> +#define PUNIT_REG_GPU_FREQ_STS			0xd8
> +#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
> +
> +#define PUNIT_OPCODE_REG_READ			6
> +#define PUNIT_OPCODE_REG_WRITE			7
> +
> +#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
> +#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
> +
>  #define GEN6_GT_CORE_STATUS		0x138060
>  #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
>  #define   GEN6_RCn_MASK			7
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7d812ba..bb97309 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4356,3 +4356,77 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>  
>  	return 0;
>  }
> +
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
> +{
> +	u32 cmd, devfn, opcode, port, be, bar;
> +
> +	bar = 0;
> +	be = 0xf;
> +	port = IOSF_PORT_PUNIT;
> +	opcode = PUNIT_OPCODE_REG_READ;
> +	devfn = 16;
> +
> +	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> +		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |

Should be (be << IOSF_BYTE_ENABLES_SHIFT).

> +		(bar << IOSF_BAR_SHIFT);
> +
> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> +	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
> +		DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
> +		return -EAGAIN;
> +	}
> +
> +	I915_WRITE(VLV_IOSF_ADDR, addr);
> +	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
> +
> +	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
> +		     500)) {
> +		DRM_ERROR("timeout waiting for pcode read (%d) to finish\n",
> +			  addr);
> +		return -ETIMEDOUT;
> +	}
> +
> +	*val = I915_READ(VLV_IOSF_DATA);
> +	I915_WRITE(VLV_IOSF_DATA, 0);
> +
> +	return 0;
> +}
> +
> +int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
> +{
> +	u32 cmd, devfn, opcode, port, be, bar;
> +
> +	bar = 0;
> +	be = 0xf;
> +	port = IOSF_PORT_PUNIT;
> +	opcode = PUNIT_OPCODE_REG_WRITE;
> +	devfn = 16;
> +
> +	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> +		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |

Ditto.

The obvious copy-pasting makes me note the read/write functions are
roughly the same... would it make sense to have a static common routine
behind the interface functions? Just add opcode parameter, and do *val =
I915_READ(VLV_IOSF_DATA) and I915_WRITE(VLV_IOSF_DATA, *val) depending
on that.

> +		(bar << IOSF_BAR_SHIFT);
> +
> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> +	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
> +		DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
> +		return -EAGAIN;
> +	}
> +
> +	I915_WRITE(VLV_IOSF_ADDR, addr);
> +	I915_WRITE(VLV_IOSF_DATA, val);
> +	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
> +
> +	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
> +		     500)) {
> +		DRM_ERROR("timeout waiting for pcode write (%d) to finish\n",
> +			  addr);
> +		return -ETIMEDOUT;
> +	}
> +
> +	I915_WRITE(VLV_IOSF_DATA, 0);
> +
> +	return 0;
> +}
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply index

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-02-02 12:56 Updated VLV patchset Jesse Barnes
2013-02-02 12:56 ` [PATCH 01/22] drm/i915: add more VLV IDs Jesse Barnes
2013-02-02 17:30   ` Rodrigo Vivi
2013-02-02 17:35     ` Jesse Barnes
2013-02-02 12:56 ` [PATCH 02/22] drm/i915: remove VLV MSI IRQ hack Jesse Barnes
2013-02-02 12:56 ` [PATCH 03/22] drm/i915: add UCGCTL4 to display reg check on VLV Jesse Barnes
2013-02-06 12:53   ` Jani Nikula
2013-02-06 13:08     ` Jani Nikula
2013-02-02 12:56 ` [PATCH 04/22] drm/i915: implement WaGTEnableMiFlush " Jesse Barnes
2013-02-05 15:31   ` Ville Syrjälä
2013-02-02 12:56 ` [PATCH 05/22] drm/i915: enable force wake, disable LLC " Jesse Barnes
2013-02-05 15:33   ` Ville Syrjälä
2013-02-06 11:35   ` Jani Nikula
2013-02-02 12:56 ` [PATCH 06/22] drm/i915: add power context allocation and setup " Jesse Barnes
2013-02-05 18:01   ` Ville Syrjälä
2013-02-05 18:14     ` Jesse Barnes
2013-02-06 13:06   ` Jani Nikula
2013-02-02 12:56 ` [PATCH 07/22] drm/i915: new register for IS_DISPLAYREG Jesse Barnes
2013-02-06 13:11   ` Jani Nikula
2013-02-02 12:56 ` [PATCH 08/22] drm/i915: allow force wake on VLV Jesse Barnes
2013-02-02 12:56 ` [PATCH 09/22] drm/i915: more clock gating disables " Jesse Barnes
2013-02-02 12:56 ` [PATCH 10/22] drm/i915: don't init LVDS " Jesse Barnes
2013-02-06 13:19   ` Jani Nikula
2013-02-06 13:34     ` Daniel Vetter
2013-03-06 14:27     ` Daniel Vetter
2013-02-02 12:56 ` [PATCH 11/22] drm/i915: fixup port enumeration " Jesse Barnes
2013-02-02 12:56 ` [PATCH 12/22] drm/i915: Fix VLV hdmi limits Jesse Barnes
2013-02-02 12:56 ` [PATCH 13/22] drm/i915: update DPIO constants for VLV Jesse Barnes
2013-02-02 12:56 ` [PATCH 14/22] drm/i915: add HMDI workarounds on VLV Jesse Barnes
2013-02-02 12:56 ` [PATCH 15/22] drm/i915: move DPIO init to init and resume, not unload Jesse Barnes
2013-02-02 12:56 ` [PATCH 16/22] drm/i915: VLV hack: Disable wm for VLV Jesse Barnes
2013-02-02 12:56 ` [PATCH 17/22] drm/i915: VLV hack: force DP to report connected Jesse Barnes
2013-02-02 12:56 ` [PATCH 18/22] drm/i915: add flush control reg to IS_DISPLAYREG check Jesse Barnes
2013-02-02 12:56 ` [PATCH 19/22] drm/i915: use gen6 stolen check on VLV Jesse Barnes
2013-02-02 12:56 ` [PATCH 20/22] drm/i915: add Punit read/write routines for VLV Jesse Barnes
2013-02-05 17:44   ` Jani Nikula [this message]
2013-02-02 12:56 ` [PATCH 21/22] drm/i915: add media well to VLV force wake routines Jesse Barnes
2013-02-02 12:56 ` [PATCH 22/22] drm/i915: turbo & RC6 support for VLV Jesse Barnes

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