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* [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf
@ 2020-02-13 14:04 Stanislav Lisovskiy
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 1/3] drm/i915: Ensure no conflicts with BIOS when updating Dbuf Stanislav Lisovskiy
                   ` (6 more replies)
  0 siblings, 7 replies; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-13 14:04 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

There are three existing issues, causing possible screen
corruptions, being addressed with those patch series.
They should go hand in hand, otherwise magic is not working.

Jani Nikula (1):
  drm/i915/dsc: force full modeset whenever DSC is enabled at probe

Stanislav Lisovskiy (1):
  drm/i915: Ensure no conflicts with BIOS when updating Dbuf

Ville Syrjälä (1):
  drm/i915: Force state->modeset=true when distrust_bios_wm==true

 drivers/gpu/drm/i915/display/intel_display.c  | 32 +++++++++++++++++++
 .../drm/i915/display/intel_display_power.c    |  6 ++--
 2 files changed, 36 insertions(+), 2 deletions(-)

-- 
2.24.1.485.gad05a3d8e5

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^ permalink raw reply	[flat|nested] 14+ messages in thread

* [Intel-gfx] [PATCH v1 1/3] drm/i915: Ensure no conflicts with BIOS when updating Dbuf
  2020-02-13 14:04 [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf Stanislav Lisovskiy
@ 2020-02-13 14:04 ` Stanislav Lisovskiy
  2020-02-13 20:25   ` Matt Roper
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 2/3] drm/i915/dsc: force full modeset whenever DSC is enabled at probe Stanislav Lisovskiy
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-13 14:04 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

TGL BIOS seems to enable both DBuf slices ocasionally, depending
how many displays are connected, while i915 according to BSpec
was powering on S1 DBuf slice, until a modeset was done.

This was causing a brief flash during the boot as we were
disabling slice, previously used by BIOS with that.

To prevent this, now we are ensuring tht we are enabling
_at least_ one slice, but if there are more, let's not
power them off.

Fixes: ff2cd8635e41 ("drm/i915: Correctly map DBUF slices to pipes")
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 53056def5414..b9a9cbad8a03 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4470,11 +4470,13 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
 
 static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
 {
+	skl_ddb_get_hw_state(dev_priv);
 	/*
-	 * Just power up 1 slice, we will
+	 * Just power up at least 1 slice, we will
 	 * figure out later which slices we have and what we need.
 	 */
-	icl_dbuf_slices_update(dev_priv, BIT(DBUF_S1));
+	icl_dbuf_slices_update(dev_priv, dev_priv->enabled_dbuf_slices_mask |
+			       BIT(DBUF_S1));
 }
 
 static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
-- 
2.24.1.485.gad05a3d8e5

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^ permalink raw reply	[flat|nested] 14+ messages in thread

* [Intel-gfx] [PATCH v1 2/3] drm/i915/dsc: force full modeset whenever DSC is enabled at probe
  2020-02-13 14:04 [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf Stanislav Lisovskiy
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 1/3] drm/i915: Ensure no conflicts with BIOS when updating Dbuf Stanislav Lisovskiy
@ 2020-02-13 14:04 ` Stanislav Lisovskiy
  2020-02-13 20:56   ` Matt Roper
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 3/3] drm/i915: Force state->modeset=true when distrust_bios_wm==true Stanislav Lisovskiy
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-13 14:04 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

From: Jani Nikula <jani.nikula@intel.com>

We lack full state readout of DSC config, which may lead to DSC enable
using a config that's all zeros, failing spectacularly. Force full
modeset and thus compute config at probe to get a sane state, until we
implement DSC state readout. Any fastset that did appear to work with
DSC at probe, worked by coincidence. [1] is an example of a change that
triggered the issue on TGL DSI DSC.

[1] http://patchwork.freedesktop.org/patch/msgid/20200212150102.7600-1-ville.syrjala@linux.intel.com

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 61ba1f2256a0..1e3f2cc27db8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17828,6 +17828,24 @@ static int intel_initial_commit(struct drm_device *dev)
 			 * have readout for pipe gamma enable.
 			 */
 			crtc_state->uapi.color_mgmt_changed = true;
+
+			/*
+			 * FIXME hack to force full modeset when DSC is being
+			 * used.
+			 *
+			 * As long as we do not have full state readout and
+			 * config comparison of crtc_state->dsc, we have no way
+			 * to ensure reliable fastset. Remove once we have
+			 * readout for DSC.
+			 */
+			if (crtc_state->dsc.compression_enable) {
+				ret = drm_atomic_add_affected_connectors(state,
+									 &crtc->base);
+				if (ret)
+					goto out;
+				crtc_state->uapi.mode_changed = true;
+				drm_dbg_kms(dev, "Force full modeset for DSC\n");
+			}
 		}
 	}
 
-- 
2.24.1.485.gad05a3d8e5

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [Intel-gfx] [PATCH v1 3/3] drm/i915: Force state->modeset=true when distrust_bios_wm==true
  2020-02-13 14:04 [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf Stanislav Lisovskiy
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 1/3] drm/i915: Ensure no conflicts with BIOS when updating Dbuf Stanislav Lisovskiy
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 2/3] drm/i915/dsc: force full modeset whenever DSC is enabled at probe Stanislav Lisovskiy
@ 2020-02-13 14:04 ` Stanislav Lisovskiy
  2020-02-13 21:08   ` Matt Roper
  2020-02-13 16:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix modeset transitions related to DBuf Patchwork
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 14+ messages in thread
From: Stanislav Lisovskiy @ 2020-02-13 14:04 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently when we load the driver we set distrust_bios_wm=true, which
will cause active_pipe_changes to get flagged even when we're not
toggling any pipes on/off. The reason being that we want to fully
redistribute the dbuf among the active pipes and ignore whatever
state the firmware left behind.

Unfortunately when the code flags active_pipe_changes it doesn't
set state->modeset to true, which means the hardware dbuf state
won't actually get updated. Hence the hardware and software
states go out of sync, which can result in planes trying to use a
disabled dbuf slice. Suprisingly that only seems to corrupt the
display rather than making the whole display engine keel over.

Let's fix this for now by flagging state->modeset whenever
distrust_bios_wm is set.

Eventually we'll likely want to rip out all of this mess and
introduce proper statye tracking for dbuf. But that requires
more work. Toss in a FIXME to that effect.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: ff2cd8635e41 ("drm/i915: Correctly map DBUF slices to pipes")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1e3f2cc27db8..df47b2fdfa38 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15027,6 +15027,20 @@ static int intel_atomic_check(struct drm_device *dev,
 	if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
 		any_ms = true;
 
+	/*
+	 * distrust_bios_wm will force a full dbuf recomputation
+	 * but the hardware state will only get updated accordingly
+	 * if state->modeset==true. Hence distrust_bios_wm==true &&
+	 * state->modeset==false is an invalid combination which
+	 * would cause the hardware and software dbuf state to get
+	 * out of sync. We must prevent that.
+	 *
+	 * FIXME clean up this mess and introduce better
+	 * state tracking for dbuf.
+	 */
+	if (dev_priv->wm.distrust_bios_wm)
+		any_ms = true;
+
 	if (any_ms) {
 		ret = intel_modeset_checks(state);
 		if (ret)
-- 
2.24.1.485.gad05a3d8e5

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix modeset transitions related to DBuf
  2020-02-13 14:04 [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf Stanislav Lisovskiy
                   ` (2 preceding siblings ...)
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 3/3] drm/i915: Force state->modeset=true when distrust_bios_wm==true Stanislav Lisovskiy
@ 2020-02-13 16:39 ` Patchwork
  2020-02-13 17:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-02-13 16:39 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Fix modeset transitions related to DBuf
URL   : https://patchwork.freedesktop.org/series/73414/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2ec3cae3ec8f drm/i915: Ensure no conflicts with BIOS when updating Dbuf
20b3246d036d drm/i915/dsc: force full modeset whenever DSC is enabled at probe
-:14: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#14: 
[1] http://patchwork.freedesktop.org/patch/msgid/20200212150102.7600-1-ville.syrjala@linux.intel.com

total: 0 errors, 1 warnings, 0 checks, 24 lines checked
26edb118d8a4 drm/i915: Force state->modeset=true when distrust_bios_wm==true

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^ permalink raw reply	[flat|nested] 14+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for Fix modeset transitions related to DBuf
  2020-02-13 14:04 [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf Stanislav Lisovskiy
                   ` (3 preceding siblings ...)
  2020-02-13 16:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix modeset transitions related to DBuf Patchwork
@ 2020-02-13 17:10 ` " Patchwork
  2020-02-15 12:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  2020-02-15 18:27 ` [Intel-gfx] [PATCH v1 0/3] " Jani Nikula
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-02-13 17:10 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Fix modeset transitions related to DBuf
URL   : https://patchwork.freedesktop.org/series/73414/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7932 -> Patchwork_16559
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/index.html

Known issues
------------

  Here are the changes found in Patchwork_16559 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_parallel@contexts:
    - fi-byt-n2820:       [PASS][1] -> [FAIL][2] ([i915#694])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/fi-byt-n2820/igt@gem_exec_parallel@contexts.html

  
#### Possible fixes ####

  * igt@gem_exec_parallel@fds:
    - fi-byt-n2820:       [TIMEOUT][3] ([fdo#112271] / [i915#1084]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/fi-byt-n2820/igt@gem_exec_parallel@fds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/fi-byt-n2820/igt@gem_exec_parallel@fds.html

  
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694


Participating hosts (44 -> 42)
------------------------------

  Additional (8): fi-hsw-peppy fi-skl-6770hq fi-bwr-2160 fi-gdg-551 fi-skl-lmem fi-bsw-nick fi-skl-6600u fi-kbl-r 
  Missing    (10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-kbl-8809g fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7932 -> Patchwork_16559

  CI-20190529: 20190529
  CI_DRM_7932: da6301c2a1bda78897e67fb22e011c1574b7c6a2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5439: ed1f7d96d4d5d4565bcd3adb3a23b2002a25419e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16559: 26edb118d8a4d148c4bd28316ff3093b67a39b9d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

26edb118d8a4 drm/i915: Force state->modeset=true when distrust_bios_wm==true
20b3246d036d drm/i915/dsc: force full modeset whenever DSC is enabled at probe
2ec3cae3ec8f drm/i915: Ensure no conflicts with BIOS when updating Dbuf

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/index.html
_______________________________________________
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^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH v1 1/3] drm/i915: Ensure no conflicts with BIOS when updating Dbuf
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 1/3] drm/i915: Ensure no conflicts with BIOS when updating Dbuf Stanislav Lisovskiy
@ 2020-02-13 20:25   ` Matt Roper
  0 siblings, 0 replies; 14+ messages in thread
From: Matt Roper @ 2020-02-13 20:25 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: jani.nikula, intel-gfx

On Thu, Feb 13, 2020 at 04:04:10PM +0200, Stanislav Lisovskiy wrote:
> TGL BIOS seems to enable both DBuf slices ocasionally, depending
> how many displays are connected, while i915 according to BSpec
> was powering on S1 DBuf slice, until a modeset was done.
> 
> This was causing a brief flash during the boot as we were
> disabling slice, previously used by BIOS with that.
> 
> To prevent this, now we are ensuring tht we are enabling
> _at least_ one slice, but if there are more, let's not
> power them off.
> 
> Fixes: ff2cd8635e41 ("drm/i915: Correctly map DBUF slices to pipes")
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 53056def5414..b9a9cbad8a03 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4470,11 +4470,13 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
>  
>  static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
>  {
> +	skl_ddb_get_hw_state(dev_priv);

Might want to add a blank line here to make it visually easier to read.

>  	/*
> -	 * Just power up 1 slice, we will
> +	 * Just power up at least 1 slice, we will

You might want to say "at least slice S1" since if the BIOS were to
initialize only S2, that wouldn't be sufficient for us (according to the
bspec).

>  	 * figure out later which slices we have and what we need.
>  	 */
> -	icl_dbuf_slices_update(dev_priv, BIT(DBUF_S1));
> +	icl_dbuf_slices_update(dev_priv, dev_priv->enabled_dbuf_slices_mask |
> +			       BIT(DBUF_S1));

We could potentially avoid some unnecessary work by checking whether
what we read back above was already good enough or not.

        if (!(dev_priv->enabled_dbuf_slices_mask & BIT(DBUF_S1)))
                icl_dbuf_slices_update(...)

But either way,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

>  }
>  
>  static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> -- 
> 2.24.1.485.gad05a3d8e5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH v1 2/3] drm/i915/dsc: force full modeset whenever DSC is enabled at probe
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 2/3] drm/i915/dsc: force full modeset whenever DSC is enabled at probe Stanislav Lisovskiy
@ 2020-02-13 20:56   ` Matt Roper
  2020-02-13 21:03     ` Jani Nikula
  0 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2020-02-13 20:56 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: jani.nikula, intel-gfx

On Thu, Feb 13, 2020 at 04:04:11PM +0200, Stanislav Lisovskiy wrote:
> From: Jani Nikula <jani.nikula@intel.com>
> 
> We lack full state readout of DSC config, which may lead to DSC enable
> using a config that's all zeros, failing spectacularly. Force full
> modeset and thus compute config at probe to get a sane state, until we
> implement DSC state readout. Any fastset that did appear to work with
> DSC at probe, worked by coincidence. [1] is an example of a change that
> triggered the issue on TGL DSI DSC.
> 
> [1] http://patchwork.freedesktop.org/patch/msgid/20200212150102.7600-1-ville.syrjala@linux.intel.com
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Should this be

Fixes: fbacb15ea814 ("drm/i915/dsc: add basic hardware state readout support")

since that's where we added the basic readout with a FIXME to add more
later?

I don't know the specifics of DSC and what state we need, but the
approach here seems reasonable.

Acked-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 61ba1f2256a0..1e3f2cc27db8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -17828,6 +17828,24 @@ static int intel_initial_commit(struct drm_device *dev)
>  			 * have readout for pipe gamma enable.
>  			 */
>  			crtc_state->uapi.color_mgmt_changed = true;
> +
> +			/*
> +			 * FIXME hack to force full modeset when DSC is being
> +			 * used.
> +			 *
> +			 * As long as we do not have full state readout and
> +			 * config comparison of crtc_state->dsc, we have no way
> +			 * to ensure reliable fastset. Remove once we have
> +			 * readout for DSC.
> +			 */
> +			if (crtc_state->dsc.compression_enable) {
> +				ret = drm_atomic_add_affected_connectors(state,
> +									 &crtc->base);
> +				if (ret)
> +					goto out;
> +				crtc_state->uapi.mode_changed = true;
> +				drm_dbg_kms(dev, "Force full modeset for DSC\n");
> +			}
>  		}
>  	}
>  
> -- 
> 2.24.1.485.gad05a3d8e5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH v1 2/3] drm/i915/dsc: force full modeset whenever DSC is enabled at probe
  2020-02-13 20:56   ` Matt Roper
@ 2020-02-13 21:03     ` Jani Nikula
  2020-02-13 21:06       ` Matt Roper
  0 siblings, 1 reply; 14+ messages in thread
From: Jani Nikula @ 2020-02-13 21:03 UTC (permalink / raw)
  To: Matt Roper, Stanislav Lisovskiy; +Cc: intel-gfx

On Thu, 13 Feb 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Thu, Feb 13, 2020 at 04:04:11PM +0200, Stanislav Lisovskiy wrote:
>> From: Jani Nikula <jani.nikula@intel.com>
>> 
>> We lack full state readout of DSC config, which may lead to DSC enable
>> using a config that's all zeros, failing spectacularly. Force full
>> modeset and thus compute config at probe to get a sane state, until we
>> implement DSC state readout. Any fastset that did appear to work with
>> DSC at probe, worked by coincidence. [1] is an example of a change that
>> triggered the issue on TGL DSI DSC.
>> 
>> [1] http://patchwork.freedesktop.org/patch/msgid/20200212150102.7600-1-ville.syrjala@linux.intel.com
>> 
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Should this be
>
> Fixes: fbacb15ea814 ("drm/i915/dsc: add basic hardware state readout support")
>
> since that's where we added the basic readout with a FIXME to add more
> later?

That added some readout and checks, but the problem existed before them
too.

BR,
Jani.



>
> I don't know the specifics of DSC and what state we need, but the
> approach here seems reasonable.
>
> Acked-by: Matt Roper <matthew.d.roper@intel.com>
>
>> ---
>>  drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++++
>>  1 file changed, 18 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 61ba1f2256a0..1e3f2cc27db8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -17828,6 +17828,24 @@ static int intel_initial_commit(struct drm_device *dev)
>>  			 * have readout for pipe gamma enable.
>>  			 */
>>  			crtc_state->uapi.color_mgmt_changed = true;
>> +
>> +			/*
>> +			 * FIXME hack to force full modeset when DSC is being
>> +			 * used.
>> +			 *
>> +			 * As long as we do not have full state readout and
>> +			 * config comparison of crtc_state->dsc, we have no way
>> +			 * to ensure reliable fastset. Remove once we have
>> +			 * readout for DSC.
>> +			 */
>> +			if (crtc_state->dsc.compression_enable) {
>> +				ret = drm_atomic_add_affected_connectors(state,
>> +									 &crtc->base);
>> +				if (ret)
>> +					goto out;
>> +				crtc_state->uapi.mode_changed = true;
>> +				drm_dbg_kms(dev, "Force full modeset for DSC\n");
>> +			}
>>  		}
>>  	}
>>  
>> -- 
>> 2.24.1.485.gad05a3d8e5
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH v1 2/3] drm/i915/dsc: force full modeset whenever DSC is enabled at probe
  2020-02-13 21:03     ` Jani Nikula
@ 2020-02-13 21:06       ` Matt Roper
  2020-02-13 21:21         ` Jani Nikula
  0 siblings, 1 reply; 14+ messages in thread
From: Matt Roper @ 2020-02-13 21:06 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Thu, Feb 13, 2020 at 11:03:29PM +0200, Jani Nikula wrote:
> On Thu, 13 Feb 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
> > On Thu, Feb 13, 2020 at 04:04:11PM +0200, Stanislav Lisovskiy wrote:
> >> From: Jani Nikula <jani.nikula@intel.com>
> >> 
> >> We lack full state readout of DSC config, which may lead to DSC enable
> >> using a config that's all zeros, failing spectacularly. Force full
> >> modeset and thus compute config at probe to get a sane state, until we
> >> implement DSC state readout. Any fastset that did appear to work with
> >> DSC at probe, worked by coincidence. [1] is an example of a change that
> >> triggered the issue on TGL DSI DSC.
> >> 
> >> [1] http://patchwork.freedesktop.org/patch/msgid/20200212150102.7600-1-ville.syrjala@linux.intel.com
> >> 
> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> >> Cc: stable@vger.kernel.org
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >
> > Should this be
> >
> > Fixes: fbacb15ea814 ("drm/i915/dsc: add basic hardware state readout support")
> >
> > since that's where we added the basic readout with a FIXME to add more
> > later?
> 
> That added some readout and checks, but the problem existed before them
> too.

Right, but that's as far back as we can go with a fix, right?  Since
before that we don't even read out enough to know that compression is
enabled?


Matt

> 
> BR,
> Jani.
> 
> 
> 
> >
> > I don't know the specifics of DSC and what state we need, but the
> > approach here seems reasonable.
> >
> > Acked-by: Matt Roper <matthew.d.roper@intel.com>
> >
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++++
> >>  1 file changed, 18 insertions(+)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 61ba1f2256a0..1e3f2cc27db8 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -17828,6 +17828,24 @@ static int intel_initial_commit(struct drm_device *dev)
> >>  			 * have readout for pipe gamma enable.
> >>  			 */
> >>  			crtc_state->uapi.color_mgmt_changed = true;
> >> +
> >> +			/*
> >> +			 * FIXME hack to force full modeset when DSC is being
> >> +			 * used.
> >> +			 *
> >> +			 * As long as we do not have full state readout and
> >> +			 * config comparison of crtc_state->dsc, we have no way
> >> +			 * to ensure reliable fastset. Remove once we have
> >> +			 * readout for DSC.
> >> +			 */
> >> +			if (crtc_state->dsc.compression_enable) {
> >> +				ret = drm_atomic_add_affected_connectors(state,
> >> +									 &crtc->base);
> >> +				if (ret)
> >> +					goto out;
> >> +				crtc_state->uapi.mode_changed = true;
> >> +				drm_dbg_kms(dev, "Force full modeset for DSC\n");
> >> +			}
> >>  		}
> >>  	}
> >>  
> >> -- 
> >> 2.24.1.485.gad05a3d8e5
> >> 
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH v1 3/3] drm/i915: Force state->modeset=true when distrust_bios_wm==true
  2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 3/3] drm/i915: Force state->modeset=true when distrust_bios_wm==true Stanislav Lisovskiy
@ 2020-02-13 21:08   ` Matt Roper
  0 siblings, 0 replies; 14+ messages in thread
From: Matt Roper @ 2020-02-13 21:08 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: jani.nikula, intel-gfx

On Thu, Feb 13, 2020 at 04:04:12PM +0200, Stanislav Lisovskiy wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently when we load the driver we set distrust_bios_wm=true, which
> will cause active_pipe_changes to get flagged even when we're not
> toggling any pipes on/off. The reason being that we want to fully
> redistribute the dbuf among the active pipes and ignore whatever
> state the firmware left behind.
> 
> Unfortunately when the code flags active_pipe_changes it doesn't
> set state->modeset to true, which means the hardware dbuf state
> won't actually get updated. Hence the hardware and software
> states go out of sync, which can result in planes trying to use a
> disabled dbuf slice. Suprisingly that only seems to corrupt the
> display rather than making the whole display engine keel over.
> 
> Let's fix this for now by flagging state->modeset whenever
> distrust_bios_wm is set.
> 
> Eventually we'll likely want to rip out all of this mess and
> introduce proper statye tracking for dbuf. But that requires
> more work. Toss in a FIXME to that effect.
> 
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Fixes: ff2cd8635e41 ("drm/i915: Correctly map DBUF slices to pipes")
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1e3f2cc27db8..df47b2fdfa38 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15027,6 +15027,20 @@ static int intel_atomic_check(struct drm_device *dev,
>  	if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
>  		any_ms = true;
>  
> +	/*
> +	 * distrust_bios_wm will force a full dbuf recomputation
> +	 * but the hardware state will only get updated accordingly
> +	 * if state->modeset==true. Hence distrust_bios_wm==true &&
> +	 * state->modeset==false is an invalid combination which
> +	 * would cause the hardware and software dbuf state to get
> +	 * out of sync. We must prevent that.
> +	 *
> +	 * FIXME clean up this mess and introduce better
> +	 * state tracking for dbuf.
> +	 */
> +	if (dev_priv->wm.distrust_bios_wm)
> +		any_ms = true;
> +
>  	if (any_ms) {
>  		ret = intel_modeset_checks(state);
>  		if (ret)
> -- 
> 2.24.1.485.gad05a3d8e5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH v1 2/3] drm/i915/dsc: force full modeset whenever DSC is enabled at probe
  2020-02-13 21:06       ` Matt Roper
@ 2020-02-13 21:21         ` Jani Nikula
  0 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2020-02-13 21:21 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Thu, 13 Feb 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Thu, Feb 13, 2020 at 11:03:29PM +0200, Jani Nikula wrote:
>> On Thu, 13 Feb 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
>> > On Thu, Feb 13, 2020 at 04:04:11PM +0200, Stanislav Lisovskiy wrote:
>> >> From: Jani Nikula <jani.nikula@intel.com>
>> >> 
>> >> We lack full state readout of DSC config, which may lead to DSC enable
>> >> using a config that's all zeros, failing spectacularly. Force full
>> >> modeset and thus compute config at probe to get a sane state, until we
>> >> implement DSC state readout. Any fastset that did appear to work with
>> >> DSC at probe, worked by coincidence. [1] is an example of a change that
>> >> triggered the issue on TGL DSI DSC.
>> >> 
>> >> [1] http://patchwork.freedesktop.org/patch/msgid/20200212150102.7600-1-ville.syrjala@linux.intel.com
>> >> 
>> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> >> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> >> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
>> >> Cc: stable@vger.kernel.org
>> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >
>> > Should this be
>> >
>> > Fixes: fbacb15ea814 ("drm/i915/dsc: add basic hardware state readout support")
>> >
>> > since that's where we added the basic readout with a FIXME to add more
>> > later?
>> 
>> That added some readout and checks, but the problem existed before them
>> too.
>
> Right, but that's as far back as we can go with a fix, right?  Since
> before that we don't even read out enough to know that compression is
> enabled?

Ah, that's right. Any fixes predating that commit would have to be
different. Perhaps we'll just settle for this. ;)

Thanks,
Jani.



>
>
> Matt
>
>> 
>> BR,
>> Jani.
>> 
>> 
>> 
>> >
>> > I don't know the specifics of DSC and what state we need, but the
>> > approach here seems reasonable.
>> >
>> > Acked-by: Matt Roper <matthew.d.roper@intel.com>
>> >
>> >> ---
>> >>  drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++++
>> >>  1 file changed, 18 insertions(+)
>> >> 
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> >> index 61ba1f2256a0..1e3f2cc27db8 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> >> @@ -17828,6 +17828,24 @@ static int intel_initial_commit(struct drm_device *dev)
>> >>  			 * have readout for pipe gamma enable.
>> >>  			 */
>> >>  			crtc_state->uapi.color_mgmt_changed = true;
>> >> +
>> >> +			/*
>> >> +			 * FIXME hack to force full modeset when DSC is being
>> >> +			 * used.
>> >> +			 *
>> >> +			 * As long as we do not have full state readout and
>> >> +			 * config comparison of crtc_state->dsc, we have no way
>> >> +			 * to ensure reliable fastset. Remove once we have
>> >> +			 * readout for DSC.
>> >> +			 */
>> >> +			if (crtc_state->dsc.compression_enable) {
>> >> +				ret = drm_atomic_add_affected_connectors(state,
>> >> +									 &crtc->base);
>> >> +				if (ret)
>> >> +					goto out;
>> >> +				crtc_state->uapi.mode_changed = true;
>> >> +				drm_dbg_kms(dev, "Force full modeset for DSC\n");
>> >> +			}
>> >>  		}
>> >>  	}
>> >>  
>> >> -- 
>> >> 2.24.1.485.gad05a3d8e5
>> >> 
>> >> _______________________________________________
>> >> Intel-gfx mailing list
>> >> Intel-gfx@lists.freedesktop.org
>> >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> 
>> -- 
>> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for Fix modeset transitions related to DBuf
  2020-02-13 14:04 [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf Stanislav Lisovskiy
                   ` (4 preceding siblings ...)
  2020-02-13 17:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-02-15 12:33 ` " Patchwork
  2020-02-15 18:27 ` [Intel-gfx] [PATCH v1 0/3] " Jani Nikula
  6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2020-02-15 12:33 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Fix modeset transitions related to DBuf
URL   : https://patchwork.freedesktop.org/series/73414/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7932_full -> Patchwork_16559_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_16559_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#112080]) +8 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb4/igt@gem_busy@busy-vcs1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb3/igt@gem_busy@busy-vcs1.html

  * igt@gem_close_race@basic-threads:
    - shard-hsw:          [PASS][3] -> [INCOMPLETE][4] ([i915#61] / [i915#694] / [i915#816])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-hsw7/igt@gem_close_race@basic-threads.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-hsw1/igt@gem_close_race@basic-threads.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#110841])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_schedule@pi-distinct-iova-bsd:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([i915#677])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb5/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html

  * igt@gem_exec_schedule@preempt-other-bsd:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#112146])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb3/igt@gem_exec_schedule@preempt-other-bsd.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb2/igt@gem_exec_schedule@preempt-other-bsd.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][11] -> [FAIL][12] ([i915#454])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb2/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          [PASS][13] -> [FAIL][14] ([i915#117] / [i915#133])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-glk8/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-glk1/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#79])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-tglb:         [PASS][17] -> [FAIL][18] ([i915#488])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-tglb3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-tglb8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([i915#79])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][21] -> [DMESG-WARN][22] ([i915#180])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +3 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#108145]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#109441]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_psr@suspend:
    - shard-skl:          [PASS][31] -> [INCOMPLETE][32] ([i915#198])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-skl7/igt@kms_psr@suspend.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-skl8/igt@kms_psr@suspend.html

  * igt@perf@short-reads:
    - shard-hsw:          [PASS][33] -> [TIMEOUT][34] ([fdo#112271] / [i915#51])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-hsw1/igt@perf@short-reads.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-hsw6/igt@perf@short-reads.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#109276]) +17 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb1/igt@prime_busy@hang-bsd2.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb8/igt@prime_busy@hang-bsd2.html

  
#### Possible fixes ####

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][37] ([fdo#110854]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb5/igt@gem_exec_balancer@smoke.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb2/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@pi-common-bsd:
    - shard-iclb:         [SKIP][39] ([i915#677]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [SKIP][41] ([fdo#112146]) -> [PASS][42] +5 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-apl:          [FAIL][43] ([i915#644]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-apl7/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-kbl:          [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_pm_rpm@cursor-dpms:
    - shard-iclb:         [INCOMPLETE][47] ([i915#189]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb2/igt@i915_pm_rpm@cursor-dpms.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb7/igt@i915_pm_rpm@cursor-dpms.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - shard-tglb:         [FAIL][51] ([i915#1172]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-tglb6/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-tglb6/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-random:
    - shard-tglb:         [FAIL][53] ([fdo#111703]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html

  * igt@kms_flip_tiling@flip-to-y-tiled:
    - shard-tglb:         [DMESG-FAIL][55] ([i915#402]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-tglb7/igt@kms_flip_tiling@flip-to-y-tiled.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-tglb2/igt@kms_flip_tiling@flip-to-y-tiled.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
    - shard-skl:          [FAIL][57] ([i915#49]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite:
    - shard-tglb:         [SKIP][59] ([i915#668]) -> [PASS][60] +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-tglb3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-tglb8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite.html

  * {igt@kms_hdr@bpc-switch-suspend}:
    - shard-skl:          [FAIL][61] ([i915#1188]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane@plane-panning-top-left-pipe-a-planes:
    - shard-tglb:         [FAIL][63] ([i915#1171]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-tglb6/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-tglb6/igt@kms_plane@plane-panning-top-left-pipe-a-planes.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][65] ([fdo#109642] / [fdo#111068]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [SKIP][67] ([fdo#109441]) -> [PASS][68] +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][69] ([i915#31]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-apl8/igt@kms_setmode@basic.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-apl4/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-skl:          [INCOMPLETE][71] ([i915#69]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-skl2/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-skl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@perf_pmu@busy-start-vcs1:
    - shard-iclb:         [SKIP][73] ([fdo#112080]) -> [PASS][74] +13 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb3/igt@perf_pmu@busy-start-vcs1.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb2/igt@perf_pmu@busy-start-vcs1.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][75] ([fdo#109276]) -> [PASS][76] +15 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv-switch:
    - shard-iclb:         [FAIL][77] ([IGT#28]) -> [SKIP][78] ([fdo#112080])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html

  * igt@runner@aborted:
    - shard-hsw:          [FAIL][79] ([i915#974]) -> ([FAIL][80], [FAIL][81]) ([i915#694] / [i915#974])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7932/shard-hsw5/igt@runner@aborted.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-hsw5/igt@runner@aborted.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/shard-hsw1/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#117]: https://gitlab.freedesktop.org/drm/intel/issues/117
  [i915#1171]: https://gitlab.freedesktop.org/drm/intel/issues/1171
  [i915#1172]: https://gitlab.freedesktop.org/drm/intel/issues/1172
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#133]: https://gitlab.freedesktop.org/drm/intel/issues/133
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#488]: https://gitlab.freedesktop.org/drm/intel/issues/488
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
  [i915#974]: https://gitlab.freedesktop.org/drm/intel/issues/974


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7932 -> Patchwork_16559

  CI-20190529: 20190529
  CI_DRM_7932: da6301c2a1bda78897e67fb22e011c1574b7c6a2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5439: ed1f7d96d4d5d4565bcd3adb3a23b2002a25419e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16559: 26edb118d8a4d148c4bd28316ff3093b67a39b9d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16559/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf
  2020-02-13 14:04 [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf Stanislav Lisovskiy
                   ` (5 preceding siblings ...)
  2020-02-15 12:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-02-15 18:27 ` " Jani Nikula
  6 siblings, 0 replies; 14+ messages in thread
From: Jani Nikula @ 2020-02-15 18:27 UTC (permalink / raw)
  To: Stanislav Lisovskiy, intel-gfx

On Thu, 13 Feb 2020, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> There are three existing issues, causing possible screen
> corruptions, being addressed with those patch series.
> They should go hand in hand, otherwise magic is not working.

Pushed the series, thanks for the patches, reviews and acks.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, back to index

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-13 14:04 [Intel-gfx] [PATCH v1 0/3] Fix modeset transitions related to DBuf Stanislav Lisovskiy
2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 1/3] drm/i915: Ensure no conflicts with BIOS when updating Dbuf Stanislav Lisovskiy
2020-02-13 20:25   ` Matt Roper
2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 2/3] drm/i915/dsc: force full modeset whenever DSC is enabled at probe Stanislav Lisovskiy
2020-02-13 20:56   ` Matt Roper
2020-02-13 21:03     ` Jani Nikula
2020-02-13 21:06       ` Matt Roper
2020-02-13 21:21         ` Jani Nikula
2020-02-13 14:04 ` [Intel-gfx] [PATCH v1 3/3] drm/i915: Force state->modeset=true when distrust_bios_wm==true Stanislav Lisovskiy
2020-02-13 21:08   ` Matt Roper
2020-02-13 16:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix modeset transitions related to DBuf Patchwork
2020-02-13 17:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-02-15 12:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-02-15 18:27 ` [Intel-gfx] [PATCH v1 0/3] " Jani Nikula

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