From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jani Nikula <jani.nikula@linux.intel.com>
Subject: Re: [PATCH 03/22] drm/i915: add UCGCTL4 to display reg
	check on VLV
Date: Wed, 06 Feb 2013 15:08:40 +0200
Message-ID: <87txppoahz.fsf@intel.com>
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To: Jesse Barnes <jbarnes@virtuousgeek.org>, intel-gfx@lists.freedesktop.org
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On Wed, 06 Feb 2013, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>> Add a few regs needed for various clock gating init purposes and make
>> sure they don't fall into the display offset range on VLV.
>
> GEN7_UCGCTL4 needs to be fixed in i915_reg.h after IS_DISPLAYREG
> removal.

Strike that. The whole patch can be dropped since it's not a display
reg.

>
>>
>> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c |    1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 69d0637..13b9b4f 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1208,6 +1208,7 @@ static bool IS_DISPLAYREG(u32 reg)
>>  	case GEN7_HALF_SLICE_CHICKEN1:
>>  	case GEN6_MBCTL:
>>  	case GEN6_UCGCTL2:
>> +	case GEN7_UCGCTL4:
>>  		return false;
>>  	default:
>>  		break;
>> -- 
>> 1.7.9.5
>>
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