From mboxrd@z Thu Jan  1 00:00:00 1970
From: Eric Anholt <eric@anholt.net>
Subject: Re: [PATCH 1/2] drm/i915: flush DC writes cached in l3$
	on gen7
Date: Thu, 26 Jul 2012 10:25:45 -0700
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Daniel Vetter <daniel.vetter@ffwll.ch> writes:

> We don't yet use this, but now that we start to look into putting that
> l3$ we better set the associated flush bit, too.
>
> Also add the only other missing PIPE_CONTROL bit #define.

Reviewed-by: Eric Anholt <eric@anholt.net>

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