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* [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/
@ 2020-03-14 12:20 Chris Wilson
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 2/7] drm/i915/gt: Pull restoration of GGTT fences underneath the GT Chris Wilson
                   ` (9 more replies)
  0 siblings, 10 replies; 15+ messages in thread
From: Chris Wilson @ 2020-03-14 12:20 UTC (permalink / raw)
  To: intel-gfx

Since the fence registers control HW detiling throught the GGTT
aperture, make them a part of the intel_ggtt under gt/

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/Makefile                 |  2 +-
 drivers/gpu/drm/i915/gt/intel_ggtt.c          |  2 +-
 .../intel_ggtt_fencing.c}                     | 27 +++++++------------
 .../intel_ggtt_fencing.h}                     |  9 +++----
 drivers/gpu/drm/i915/gt/intel_gtt.h           |  2 +-
 drivers/gpu/drm/i915/gt/intel_reset.c         |  2 +-
 drivers/gpu/drm/i915/gvt/aperture_gm.c        |  2 +-
 drivers/gpu/drm/i915/i915_drv.c               |  6 ++---
 drivers/gpu/drm/i915/i915_drv.h               |  1 -
 drivers/gpu/drm/i915/i915_gem.c               |  2 +-
 drivers/gpu/drm/i915/i915_vma.h               |  1 -
 drivers/gpu/drm/i915/selftests/i915_gem.c     |  2 +-
 12 files changed, 24 insertions(+), 34 deletions(-)
 rename drivers/gpu/drm/i915/{i915_gem_fence_reg.c => gt/intel_ggtt_fencing.c} (97%)
 rename drivers/gpu/drm/i915/{i915_gem_fence_reg.h => gt/intel_ggtt_fencing.h} (92%)

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9f887a86e555..1b2ed963179c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -92,6 +92,7 @@ gt-y += \
 	gt/intel_engine_pool.o \
 	gt/intel_engine_user.o \
 	gt/intel_ggtt.o \
+	gt/intel_ggtt_fencing.o \
 	gt/intel_gt.o \
 	gt/intel_gt_irq.o \
 	gt/intel_gt_pm.o \
@@ -153,7 +154,6 @@ i915-y += \
 	  i915_buddy.o \
 	  i915_cmd_parser.o \
 	  i915_gem_evict.o \
-	  i915_gem_fence_reg.o \
 	  i915_gem_gtt.o \
 	  i915_gem.o \
 	  i915_globals.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index aed498a0d032..a7b72fa569a7 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -65,7 +65,7 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
 					      ggtt->mappable_end);
 	}
 
-	i915_ggtt_init_fences(ggtt);
+	intel_ggtt_init_fences(ggtt);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
similarity index 97%
rename from drivers/gpu/drm/i915/i915_gem_fence_reg.c
rename to drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index d152b648c73c..94af75673a58 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -233,16 +233,9 @@ static int fence_update(struct i915_fence_reg *fence,
 	int ret;
 
 	if (vma) {
-		if (!i915_vma_is_map_and_fenceable(vma))
-			return -EINVAL;
-
-		if (drm_WARN(&uncore->i915->drm,
-			     !i915_gem_object_get_stride(vma->obj) ||
-			     !i915_gem_object_get_tiling(vma->obj),
-			     "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
-			     i915_gem_object_get_stride(vma->obj),
-			     i915_gem_object_get_tiling(vma->obj)))
-			return -EINVAL;
+		GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
+		GEM_BUG_ON(!i915_gem_object_get_stride(vma->obj) ||
+			   !i915_gem_object_get_tiling(vma->obj));
 
 		ret = i915_vma_sync(vma);
 		if (ret)
@@ -276,7 +269,7 @@ static int fence_update(struct i915_fence_reg *fence,
 	/*
 	 * We only need to update the register itself if the device is awake.
 	 * If the device is currently powered down, we will defer the write
-	 * to the runtime resume, see i915_gem_restore_fences().
+	 * to the runtime resume, see intel_ggtt_restore_fences().
 	 *
 	 * This only works for removing the fence register, on acquisition
 	 * the caller must hold the rpm wakeref. The fence register must
@@ -487,14 +480,14 @@ void i915_unreserve_fence(struct i915_fence_reg *fence)
 }
 
 /**
- * i915_gem_restore_fences - restore fence state
+ * intel_ggtt_restore_fences - restore fence state
  * @ggtt: Global GTT
  *
  * Restore the hw fence state to match the software tracking again, to be called
  * after a gpu reset and on resume. Note that on runtime suspend we only cancel
  * the fences, to be reacquired by the user later.
  */
-void i915_gem_restore_fences(struct i915_ggtt *ggtt)
+void intel_ggtt_restore_fences(struct i915_ggtt *ggtt)
 {
 	int i;
 
@@ -746,7 +739,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
  * bit 17 of its physical address and therefore being interpreted differently
  * by the GPU.
  */
-static void i915_gem_swizzle_page(struct page *page)
+static void swizzle_page(struct page *page)
 {
 	char temp[64];
 	char *vaddr;
@@ -791,7 +784,7 @@ i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
 	for_each_sgt_page(page, sgt_iter, pages) {
 		char new_bit_17 = page_to_phys(page) >> 17;
 		if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) {
-			i915_gem_swizzle_page(page);
+			swizzle_page(page);
 			set_page_dirty(page);
 		}
 		i++;
@@ -836,7 +829,7 @@ i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
 	}
 }
 
-void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
+void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
 {
 	struct drm_i915_private *i915 = ggtt->vm.i915;
 	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
@@ -875,7 +868,7 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
 	}
 	ggtt->num_fences = num_fences;
 
-	i915_gem_restore_fences(ggtt);
+	intel_ggtt_restore_fences(ggtt);
 }
 
 void intel_gt_init_swizzling(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
similarity index 92%
rename from drivers/gpu/drm/i915/i915_gem_fence_reg.h
rename to drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
index 7bd521cd7cd7..3b3eb5bf1b75 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __I915_FENCE_REG_H__
-#define __I915_FENCE_REG_H__
+#ifndef __INTEL_GGTT_FENCING_H__
+#define __INTEL_GGTT_FENCING_H__
 
 #include <linux/list.h>
 #include <linux/types.h>
@@ -53,18 +53,17 @@ struct i915_fence_reg {
 	bool dirty;
 };
 
-/* i915_gem_fence_reg.c */
 struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt);
 void i915_unreserve_fence(struct i915_fence_reg *fence);
 
-void i915_gem_restore_fences(struct i915_ggtt *ggtt);
+void intel_ggtt_restore_fences(struct i915_ggtt *ggtt);
 
 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
 				       struct sg_table *pages);
 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
 					 struct sg_table *pages);
 
-void i915_ggtt_init_fences(struct i915_ggtt *ggtt);
+void intel_ggtt_init_fences(struct i915_ggtt *ggtt);
 
 void intel_gt_init_swizzling(struct intel_gt *gt);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index b3116fe8d180..ce6ff9d3a350 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -26,7 +26,7 @@
 #include <drm/drm_mm.h>
 
 #include "gt/intel_reset.h"
-#include "i915_gem_fence_reg.h"
+#include "gt/intel_ggtt_fencing.h"
 #include "i915_selftest.h"
 #include "i915_vma_types.h"
 
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 8b170c1876b3..9a15bdf31c7f 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -750,7 +750,7 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 	for_each_engine(engine, gt, id)
 		__intel_engine_reset(engine, stalled_mask & engine->mask);
 
-	i915_gem_restore_fences(gt->ggtt);
+	intel_ggtt_restore_fences(gt->ggtt);
 
 	return err;
 }
diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index 8b13f091cee2..0d6d59871308 100644
--- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
+++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
@@ -35,7 +35,7 @@
  */
 
 #include "i915_drv.h"
-#include "i915_gem_fence_reg.h"
+#include "gt/intel_ggtt_fencing.h"
 #include "gvt.h"
 
 static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 82d9df15b22b..832140f4ea3d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1288,7 +1288,7 @@ static int i915_drm_resume(struct drm_device *dev)
 		drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
 
 	i915_ggtt_resume(&dev_priv->ggtt);
-	i915_gem_restore_fences(&dev_priv->ggtt);
+	intel_ggtt_restore_fences(&dev_priv->ggtt);
 
 	intel_csr_ucode_resume(dev_priv);
 
@@ -1606,7 +1606,7 @@ static int intel_runtime_suspend(struct device *kdev)
 
 		intel_gt_runtime_resume(&dev_priv->gt);
 
-		i915_gem_restore_fences(&dev_priv->ggtt);
+		intel_ggtt_restore_fences(&dev_priv->ggtt);
 
 		enable_rpm_wakeref_asserts(rpm);
 
@@ -1687,7 +1687,7 @@ static int intel_runtime_resume(struct device *kdev)
 	 * we can do is to hope that things will still work (and disable RPM).
 	 */
 	intel_gt_runtime_resume(&dev_priv->gt);
-	i915_gem_restore_fences(&dev_priv->ggtt);
+	intel_ggtt_restore_fences(&dev_priv->ggtt);
 
 	/*
 	 * On VLV/CHV display interrupts are part of the display
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1f5b9a584f71..ddd5b40cbbbc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -92,7 +92,6 @@
 #include "intel_wopcm.h"
 
 #include "i915_gem.h"
-#include "i915_gem_fence_reg.h"
 #include "i915_gem_gtt.h"
 #include "i915_gpu_error.h"
 #include "i915_perf_types.h"
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ca5420012a22..2c53be0bd9fd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1156,7 +1156,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 		/* Minimal basic recovery for KMS */
 		ret = i915_ggtt_enable_hw(dev_priv);
 		i915_ggtt_resume(&dev_priv->ggtt);
-		i915_gem_restore_fences(&dev_priv->ggtt);
+		intel_ggtt_restore_fences(&dev_priv->ggtt);
 		intel_init_clock_gating(dev_priv);
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index e1ced1df13e1..2764c277326f 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -33,7 +33,6 @@
 #include "gem/i915_gem_object.h"
 
 #include "i915_gem_gtt.h"
-#include "i915_gem_fence_reg.h"
 
 #include "i915_active.h"
 #include "i915_request.h"
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c
index 623759b73bb4..7ea517a21e0b 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -125,7 +125,7 @@ static void pm_resume(struct drm_i915_private *i915)
 	 */
 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
 		i915_ggtt_resume(&i915->ggtt);
-		i915_gem_restore_fences(&i915->ggtt);
+		intel_ggtt_restore_fences(&i915->ggtt);
 
 		i915_gem_resume(i915);
 	}
-- 
2.20.1

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH 2/7] drm/i915/gt: Pull restoration of GGTT fences underneath the GT
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
@ 2020-03-14 12:20 ` Chris Wilson
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 3/7] drm/i915: Remove manual save/resume of fence register state Chris Wilson
                   ` (8 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-03-14 12:20 UTC (permalink / raw)
  To: intel-gfx

Make the GT responsible for restoring its fence when it wakes up from
suspend.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c      | 2 ++
 drivers/gpu/drm/i915/gt/intel_gt_pm.c     | 1 +
 drivers/gpu/drm/i915/i915_drv.c           | 4 ----
 drivers/gpu/drm/i915/i915_gem.c           | 1 -
 drivers/gpu/drm/i915/selftests/i915_gem.c | 2 --
 5 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index a7b72fa569a7..bde4f64a41f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1195,6 +1195,8 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
 
 	if (INTEL_GEN(ggtt->vm.i915) >= 8)
 		setup_private_pat(ggtt->vm.gt->uncore);
+
+	intel_ggtt_restore_fences(ggtt);
 }
 
 static struct scatterlist *
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 8b653c0f5e5f..2e40400d1ecd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -324,6 +324,7 @@ int intel_gt_runtime_resume(struct intel_gt *gt)
 {
 	GT_TRACE(gt, "\n");
 	intel_gt_init_swizzling(gt);
+	intel_ggtt_restore_fences(gt->ggtt);
 
 	return intel_uc_runtime_resume(&gt->uc);
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 832140f4ea3d..48ba37e35bea 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1288,7 +1288,6 @@ static int i915_drm_resume(struct drm_device *dev)
 		drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
 
 	i915_ggtt_resume(&dev_priv->ggtt);
-	intel_ggtt_restore_fences(&dev_priv->ggtt);
 
 	intel_csr_ucode_resume(dev_priv);
 
@@ -1606,8 +1605,6 @@ static int intel_runtime_suspend(struct device *kdev)
 
 		intel_gt_runtime_resume(&dev_priv->gt);
 
-		intel_ggtt_restore_fences(&dev_priv->ggtt);
-
 		enable_rpm_wakeref_asserts(rpm);
 
 		return ret;
@@ -1687,7 +1684,6 @@ static int intel_runtime_resume(struct device *kdev)
 	 * we can do is to hope that things will still work (and disable RPM).
 	 */
 	intel_gt_runtime_resume(&dev_priv->gt);
-	intel_ggtt_restore_fences(&dev_priv->ggtt);
 
 	/*
 	 * On VLV/CHV display interrupts are part of the display
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2c53be0bd9fd..762b50b08d73 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1156,7 +1156,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 		/* Minimal basic recovery for KMS */
 		ret = i915_ggtt_enable_hw(dev_priv);
 		i915_ggtt_resume(&dev_priv->ggtt);
-		intel_ggtt_restore_fences(&dev_priv->ggtt);
 		intel_init_clock_gating(dev_priv);
 	}
 
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c
index 7ea517a21e0b..88d400b9df88 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
@@ -125,8 +125,6 @@ static void pm_resume(struct drm_i915_private *i915)
 	 */
 	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
 		i915_ggtt_resume(&i915->ggtt);
-		intel_ggtt_restore_fences(&i915->ggtt);
-
 		i915_gem_resume(i915);
 	}
 }
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH 3/7] drm/i915: Remove manual save/resume of fence register state
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 2/7] drm/i915/gt: Pull restoration of GGTT fences underneath the GT Chris Wilson
@ 2020-03-14 12:20 ` Chris Wilson
  2020-03-16  7:14   ` Mika Kuoppala
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 4/7] drm/i915/gt: Allocate i915_fence_reg array Chris Wilson
                   ` (7 subsequent siblings)
  9 siblings, 1 reply; 15+ messages in thread
From: Chris Wilson @ 2020-03-14 12:20 UTC (permalink / raw)
  To: intel-gfx

Since we always reload the fence register state on runtime resume,
having it explicitly in the S0ix resume code is redundant. Indeed, it
is not even being used!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ddd5b40cbbbc..a7ea1d855359 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -539,7 +539,6 @@ struct i915_suspend_saved_registers {
 	u32 saveSWF0[16];
 	u32 saveSWF1[16];
 	u32 saveSWF3[3];
-	u64 saveFENCE[I915_MAX_NUM_FENCES];
 	u32 savePCH_PORT_HOTPLUG;
 	u16 saveGCDGMBUS;
 };
-- 
2.20.1

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^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH 4/7] drm/i915/gt: Allocate i915_fence_reg array
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 2/7] drm/i915/gt: Pull restoration of GGTT fences underneath the GT Chris Wilson
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 3/7] drm/i915: Remove manual save/resume of fence register state Chris Wilson
@ 2020-03-14 12:20 ` Chris Wilson
  2020-03-16  7:29   ` Mika Kuoppala
  2020-03-16 11:20   ` Mika Kuoppala
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 5/7] drm/i915/gt: Store the fence details on the fence Chris Wilson
                   ` (6 subsequent siblings)
  9 siblings, 2 replies; 15+ messages in thread
From: Chris Wilson @ 2020-03-14 12:20 UTC (permalink / raw)
  To: intel-gfx

Since the number of fence regs can vary dramactically between platforms,
allocate the array on demand so we don't waste as much space.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c         |  6 ++++--
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 10 ++++++++++
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h |  1 +
 drivers/gpu/drm/i915/gt/intel_gtt.h          |  5 +++--
 drivers/gpu/drm/i915/i915_vma.h              |  1 +
 5 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index bde4f64a41f7..8fcf14372d7a 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -698,11 +698,13 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
  */
 void i915_ggtt_driver_release(struct drm_i915_private *i915)
 {
+	struct i915_ggtt *ggtt = &i915->ggtt;
 	struct pagevec *pvec;
 
-	fini_aliasing_ppgtt(&i915->ggtt);
+	fini_aliasing_ppgtt(ggtt);
 
-	ggtt_cleanup_hw(&i915->ggtt);
+	intel_ggtt_fini_fences(ggtt);
+	ggtt_cleanup_hw(ggtt);
 
 	pvec = &i915->mm.wc_stash.pvec;
 	if (pvec->nr) {
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 94af75673a58..b6ba68c42546 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -857,6 +857,11 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
 	if (intel_vgpu_active(i915))
 		num_fences = intel_uncore_read(uncore,
 					       vgtif_reg(avail_rs.fence_num));
+	ggtt->fence_regs = kcalloc(num_fences,
+				   sizeof(*ggtt->fence_regs),
+				   GFP_KERNEL);
+	if (!ggtt->fence_regs)
+		num_fences = 0;
 
 	/* Initialize fence registers to zero */
 	for (i = 0; i < num_fences; i++) {
@@ -871,6 +876,11 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
 	intel_ggtt_restore_fences(ggtt);
 }
 
+void intel_ggtt_fini_fences(struct i915_ggtt *ggtt)
+{
+	kfree(ggtt->fence_regs);
+}
+
 void intel_gt_init_swizzling(struct intel_gt *gt)
 {
 	struct drm_i915_private *i915 = gt->i915;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
index 3b3eb5bf1b75..9850f6a85d2a 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
@@ -64,6 +64,7 @@ void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
 					 struct sg_table *pages);
 
 void intel_ggtt_init_fences(struct i915_ggtt *ggtt);
+void intel_ggtt_fini_fences(struct i915_ggtt *ggtt);
 
 void intel_gt_init_swizzling(struct intel_gt *gt);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index ce6ff9d3a350..d93ebdf3fa0e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -26,7 +26,6 @@
 #include <drm/drm_mm.h>
 
 #include "gt/intel_reset.h"
-#include "gt/intel_ggtt_fencing.h"
 #include "i915_selftest.h"
 #include "i915_vma_types.h"
 
@@ -135,6 +134,8 @@ typedef u64 gen8_pte_t;
 #define GEN8_PDE_IPS_64K BIT(11)
 #define GEN8_PDE_PS_2M   BIT(7)
 
+struct i915_fence_reg;
+
 #define for_each_sgt_daddr(__dp, __iter, __sgt) \
 	__for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
 
@@ -333,7 +334,7 @@ struct i915_ggtt {
 	u32 pin_bias;
 
 	unsigned int num_fences;
-	struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
+	struct i915_fence_reg *fence_regs;
 	struct list_head fence_list;
 
 	/**
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index 2764c277326f..b958ad07f212 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -30,6 +30,7 @@
 
 #include <drm/drm_mm.h>
 
+#include "gt/intel_ggtt_fencing.h"
 #include "gem/i915_gem_object.h"
 
 #include "i915_gem_gtt.h"
-- 
2.20.1

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH 5/7] drm/i915/gt: Store the fence details on the fence
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
                   ` (2 preceding siblings ...)
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 4/7] drm/i915/gt: Allocate i915_fence_reg array Chris Wilson
@ 2020-03-14 12:20 ` Chris Wilson
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 6/7] drm/i915/gt: Only wait for GPU activity before unbinding a GGTT fence Chris Wilson
                   ` (5 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-03-14 12:20 UTC (permalink / raw)
  To: intel-gfx

Make a copy of the object tiling parameters at the point of grabbing the
fence.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 18 ++++++++++--------
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h |  2 ++
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index b6ba68c42546..51984cee18b3 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -88,7 +88,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence,
 
 	val = 0;
 	if (vma) {
-		unsigned int stride = i915_gem_object_get_stride(vma->obj);
+		unsigned int stride = fence->stride;
 
 		GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 		GEM_BUG_ON(!IS_ALIGNED(vma->node.start, I965_FENCE_PAGE));
@@ -98,7 +98,7 @@ static void i965_write_fence_reg(struct i915_fence_reg *fence,
 		val = (vma->node.start + vma->fence_size - I965_FENCE_PAGE) << 32;
 		val |= vma->node.start;
 		val |= (u64)((stride / 128) - 1) << fence_pitch_shift;
-		if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
+		if (fence->tiling == I915_TILING_Y)
 			val |= BIT(I965_FENCE_TILING_Y_SHIFT);
 		val |= I965_FENCE_REG_VALID;
 	}
@@ -132,9 +132,9 @@ static void i915_write_fence_reg(struct i915_fence_reg *fence,
 
 	val = 0;
 	if (vma) {
-		unsigned int tiling = i915_gem_object_get_tiling(vma->obj);
+		unsigned int stride = fence->stride;
+		unsigned int tiling = fence->tiling;
 		bool is_y_tiled = tiling == I915_TILING_Y;
-		unsigned int stride = i915_gem_object_get_stride(vma->obj);
 
 		GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 		GEM_BUG_ON(vma->node.start & ~I915_FENCE_START_MASK);
@@ -172,7 +172,7 @@ static void i830_write_fence_reg(struct i915_fence_reg *fence,
 
 	val = 0;
 	if (vma) {
-		unsigned int stride = i915_gem_object_get_stride(vma->obj);
+		unsigned int stride = fence->stride;
 
 		GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
 		GEM_BUG_ON(vma->node.start & ~I830_FENCE_START_MASK);
@@ -181,7 +181,7 @@ static void i830_write_fence_reg(struct i915_fence_reg *fence,
 		GEM_BUG_ON(!IS_ALIGNED(vma->node.start, vma->fence_size));
 
 		val = vma->node.start;
-		if (i915_gem_object_get_tiling(vma->obj) == I915_TILING_Y)
+		if (fence->tiling == I915_TILING_Y)
 			val |= BIT(I830_FENCE_TILING_Y_SHIFT);
 		val |= I830_FENCE_SIZE_BITS(vma->fence_size);
 		val |= ilog2(stride / 128) << I830_FENCE_PITCH_SHIFT;
@@ -219,8 +219,6 @@ static void fence_write(struct i915_fence_reg *fence,
 	 * Access through the fenced region afterwards is
 	 * ordered by the posting reads whilst writing the registers.
 	 */
-
-	fence->dirty = false;
 }
 
 static int fence_update(struct i915_fence_reg *fence,
@@ -240,6 +238,10 @@ static int fence_update(struct i915_fence_reg *fence,
 		ret = i915_vma_sync(vma);
 		if (ret)
 			return ret;
+
+		fence->stride = i915_gem_object_get_stride(vma->obj);
+		fence->tiling = i915_gem_object_get_tiling(vma->obj);
+		WRITE_ONCE(fence->dirty, false);
 	}
 
 	old = xchg(&fence->vma, NULL);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
index 9850f6a85d2a..ad3acc9b7f37 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
@@ -51,6 +51,8 @@ struct i915_fence_reg {
 	 * command (such as BLT on gen2/3), as a "fence".
 	 */
 	bool dirty;
+	unsigned int stride;
+	unsigned int tiling;
 };
 
 struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt);
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH 6/7] drm/i915/gt: Only wait for GPU activity before unbinding a GGTT fence
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
                   ` (3 preceding siblings ...)
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 5/7] drm/i915/gt: Store the fence details on the fence Chris Wilson
@ 2020-03-14 12:20 ` Chris Wilson
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 7/7] drm/i915/gt: Make fence revocation unequivocal Chris Wilson
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-03-14 12:20 UTC (permalink / raw)
  To: intel-gfx

Only GPU activity via the GGTT fence is asynchronous, we know that we
control the CPU access directly, so we only need to wait for the GPU to
stop using the fence before we relinquish it.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 12 ++++++++----
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h |  3 +++
 drivers/gpu/drm/i915/i915_vma.c              |  4 ++++
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 51984cee18b3..f1ded8fbda3a 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -235,9 +235,12 @@ static int fence_update(struct i915_fence_reg *fence,
 		GEM_BUG_ON(!i915_gem_object_get_stride(vma->obj) ||
 			   !i915_gem_object_get_tiling(vma->obj));
 
-		ret = i915_vma_sync(vma);
-		if (ret)
-			return ret;
+		if (INTEL_GEN(fence_to_i915(fence)) < 4) {
+			/* implicit 'unfenced' GPU blits */
+			ret = i915_vma_sync(vma);
+			if (ret)
+				return ret;
+		}
 
 		fence->stride = i915_gem_object_get_stride(vma->obj);
 		fence->tiling = i915_gem_object_get_tiling(vma->obj);
@@ -247,7 +250,7 @@ static int fence_update(struct i915_fence_reg *fence,
 	old = xchg(&fence->vma, NULL);
 	if (old) {
 		/* XXX Ideally we would move the waiting to outside the mutex */
-		ret = i915_vma_sync(old);
+		ret = i915_active_wait(&fence->active);
 		if (ret) {
 			fence->vma = old;
 			return ret;
@@ -869,6 +872,7 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
 	for (i = 0; i < num_fences; i++) {
 		struct i915_fence_reg *fence = &ggtt->fence_regs[i];
 
+		i915_active_init(&fence->active, NULL, NULL);
 		fence->ggtt = ggtt;
 		fence->id = i;
 		list_add_tail(&fence->link, &ggtt->fence_list);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
index ad3acc9b7f37..1731cd039bb9 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
@@ -28,6 +28,8 @@
 #include <linux/list.h>
 #include <linux/types.h>
 
+#include "i915_active.h"
+
 struct drm_i915_gem_object;
 struct i915_ggtt;
 struct i915_vma;
@@ -41,6 +43,7 @@ struct i915_fence_reg {
 	struct i915_ggtt *ggtt;
 	struct i915_vma *vma;
 	atomic_t pin_count;
+	struct i915_active active;
 	int id;
 	/**
 	 * Whether the tiling parameters for the currently
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 5b3efb43a8ef..aedbd056fd45 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1214,6 +1214,10 @@ int i915_vma_move_to_active(struct i915_vma *vma,
 		dma_resv_add_shared_fence(vma->resv, &rq->fence);
 		obj->write_domain = 0;
 	}
+
+	if (flags & EXEC_OBJECT_NEEDS_FENCE && vma->fence)
+		i915_active_add_request(&vma->fence->active, rq);
+
 	obj->read_domains |= I915_GEM_GPU_DOMAINS;
 	obj->mm.dirty = true;
 
-- 
2.20.1

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH 7/7] drm/i915/gt: Make fence revocation unequivocal
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
                   ` (4 preceding siblings ...)
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 6/7] drm/i915/gt: Only wait for GPU activity before unbinding a GGTT fence Chris Wilson
@ 2020-03-14 12:20 ` Chris Wilson
  2020-03-16  7:02 ` [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Mika Kuoppala
                   ` (3 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-03-14 12:20 UTC (permalink / raw)
  To: intel-gfx

If we must revoke the fence because the VMA is no longer present, or
because the fence no longer applies, ensure that we do and convert it
into an error if we try but cannot.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 20 +++++++++++---------
 drivers/gpu/drm/i915/i915_gem.c              | 12 +++++-------
 drivers/gpu/drm/i915/i915_vma.c              |  4 +---
 drivers/gpu/drm/i915/i915_vma.h              |  2 +-
 4 files changed, 18 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index f1ded8fbda3a..125713f2d055 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -305,23 +305,25 @@ static int fence_update(struct i915_fence_reg *fence,
  *
  * This function force-removes any fence from the given object, which is useful
  * if the kernel wants to do untiled GTT access.
- *
- * Returns:
- *
- * 0 on success, negative error code on failure.
  */
-int i915_vma_revoke_fence(struct i915_vma *vma)
+void i915_vma_revoke_fence(struct i915_vma *vma)
 {
 	struct i915_fence_reg *fence = vma->fence;
+	intel_wakeref_t wakeref;
 
 	lockdep_assert_held(&vma->vm->mutex);
 	if (!fence)
-		return 0;
+		return;
+
+	GEM_BUG_ON(fence->vma != vma);
+	GEM_BUG_ON(!i915_active_is_idle(&fence->active));
+	GEM_BUG_ON(atomic_read(&fence->pin_count));
 
-	if (atomic_read(&fence->pin_count))
-		return -EBUSY;
+	WRITE_ONCE(fence->vma, NULL);
+	vma->fence = NULL;
 
-	return fence_update(fence, NULL);
+	with_intel_runtime_pm_if_in_use(fence_to_uncore(fence)->rpm, wakeref)
+		fence_write(fence, NULL);
 }
 
 static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 762b50b08d73..b0836fc47ae6 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -993,18 +993,16 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
 			return ERR_PTR(ret);
 	}
 
+	ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
+	if (ret)
+		return ERR_PTR(ret);
+
 	if (vma->fence && !i915_gem_object_is_tiled(obj)) {
 		mutex_lock(&ggtt->vm.mutex);
-		ret = i915_vma_revoke_fence(vma);
+		i915_vma_revoke_fence(vma);
 		mutex_unlock(&ggtt->vm.mutex);
-		if (ret)
-			return ERR_PTR(ret);
 	}
 
-	ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
-	if (ret)
-		return ERR_PTR(ret);
-
 	ret = i915_vma_wait_for_bind(vma);
 	if (ret) {
 		i915_vma_unpin(vma);
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index aedbd056fd45..df197b07ac99 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1280,9 +1280,7 @@ int __i915_vma_unbind(struct i915_vma *vma)
 		i915_vma_flush_writes(vma);
 
 		/* release the fence reg _after_ flushing */
-		ret = i915_vma_revoke_fence(vma);
-		if (ret)
-			return ret;
+		i915_vma_revoke_fence(vma);
 
 		/* Force a pagefault for domain tracking on next user access */
 		i915_vma_revoke_mmap(vma);
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index b958ad07f212..8ad1daabcd58 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -326,7 +326,7 @@ static inline struct page *i915_vma_first_page(struct i915_vma *vma)
  * True if the vma has a fence, false otherwise.
  */
 int __must_check i915_vma_pin_fence(struct i915_vma *vma);
-int __must_check i915_vma_revoke_fence(struct i915_vma *vma);
+void i915_vma_revoke_fence(struct i915_vma *vma);
 
 int __i915_vma_pin_fence(struct i915_vma *vma);
 
-- 
2.20.1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
                   ` (5 preceding siblings ...)
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 7/7] drm/i915/gt: Make fence revocation unequivocal Chris Wilson
@ 2020-03-16  7:02 ` Mika Kuoppala
  2020-03-16 15:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
                   ` (2 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Mika Kuoppala @ 2020-03-16  7:02 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Since the fence registers control HW detiling throught the GGTT
> aperture, make them a part of the intel_ggtt under gt/
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/Makefile                 |  2 +-
>  drivers/gpu/drm/i915/gt/intel_ggtt.c          |  2 +-
>  .../intel_ggtt_fencing.c}                     | 27 +++++++------------
>  .../intel_ggtt_fencing.h}                     |  9 +++----
>  drivers/gpu/drm/i915/gt/intel_gtt.h           |  2 +-
>  drivers/gpu/drm/i915/gt/intel_reset.c         |  2 +-
>  drivers/gpu/drm/i915/gvt/aperture_gm.c        |  2 +-
>  drivers/gpu/drm/i915/i915_drv.c               |  6 ++---
>  drivers/gpu/drm/i915/i915_drv.h               |  1 -
>  drivers/gpu/drm/i915/i915_gem.c               |  2 +-
>  drivers/gpu/drm/i915/i915_vma.h               |  1 -
>  drivers/gpu/drm/i915/selftests/i915_gem.c     |  2 +-
>  12 files changed, 24 insertions(+), 34 deletions(-)
>  rename drivers/gpu/drm/i915/{i915_gem_fence_reg.c => gt/intel_ggtt_fencing.c} (97%)
>  rename drivers/gpu/drm/i915/{i915_gem_fence_reg.h => gt/intel_ggtt_fencing.h} (92%)
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 9f887a86e555..1b2ed963179c 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -92,6 +92,7 @@ gt-y += \
>  	gt/intel_engine_pool.o \
>  	gt/intel_engine_user.o \
>  	gt/intel_ggtt.o \
> +	gt/intel_ggtt_fencing.o \
>  	gt/intel_gt.o \
>  	gt/intel_gt_irq.o \
>  	gt/intel_gt_pm.o \
> @@ -153,7 +154,6 @@ i915-y += \
>  	  i915_buddy.o \
>  	  i915_cmd_parser.o \
>  	  i915_gem_evict.o \
> -	  i915_gem_fence_reg.o \
>  	  i915_gem_gtt.o \
>  	  i915_gem.o \
>  	  i915_globals.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index aed498a0d032..a7b72fa569a7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -65,7 +65,7 @@ static int ggtt_init_hw(struct i915_ggtt *ggtt)
>  					      ggtt->mappable_end);
>  	}
>  
> -	i915_ggtt_init_fences(ggtt);
> +	intel_ggtt_init_fences(ggtt);
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> similarity index 97%
> rename from drivers/gpu/drm/i915/i915_gem_fence_reg.c
> rename to drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index d152b648c73c..94af75673a58 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -233,16 +233,9 @@ static int fence_update(struct i915_fence_reg *fence,
>  	int ret;
>  
>  	if (vma) {
> -		if (!i915_vma_is_map_and_fenceable(vma))
> -			return -EINVAL;
> -
> -		if (drm_WARN(&uncore->i915->drm,
> -			     !i915_gem_object_get_stride(vma->obj) ||
> -			     !i915_gem_object_get_tiling(vma->obj),
> -			     "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
> -			     i915_gem_object_get_stride(vma->obj),
> -			     i915_gem_object_get_tiling(vma->obj)))
> -			return -EINVAL;
> +		GEM_BUG_ON(!i915_vma_is_map_and_fenceable(vma));
> +		GEM_BUG_ON(!i915_gem_object_get_stride(vma->obj) ||
> +			   !i915_gem_object_get_tiling(vma->obj));
>  
>  		ret = i915_vma_sync(vma);
>  		if (ret)
> @@ -276,7 +269,7 @@ static int fence_update(struct i915_fence_reg *fence,
>  	/*
>  	 * We only need to update the register itself if the device is awake.
>  	 * If the device is currently powered down, we will defer the write
> -	 * to the runtime resume, see i915_gem_restore_fences().
> +	 * to the runtime resume, see intel_ggtt_restore_fences().
>  	 *
>  	 * This only works for removing the fence register, on acquisition
>  	 * the caller must hold the rpm wakeref. The fence register must
> @@ -487,14 +480,14 @@ void i915_unreserve_fence(struct i915_fence_reg *fence)
>  }
>  
>  /**
> - * i915_gem_restore_fences - restore fence state
> + * intel_ggtt_restore_fences - restore fence state
>   * @ggtt: Global GTT
>   *
>   * Restore the hw fence state to match the software tracking again, to be called
>   * after a gpu reset and on resume. Note that on runtime suspend we only cancel
>   * the fences, to be reacquired by the user later.
>   */
> -void i915_gem_restore_fences(struct i915_ggtt *ggtt)
> +void intel_ggtt_restore_fences(struct i915_ggtt *ggtt)
>  {
>  	int i;
>  
> @@ -746,7 +739,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
>   * bit 17 of its physical address and therefore being interpreted differently
>   * by the GPU.
>   */
> -static void i915_gem_swizzle_page(struct page *page)
> +static void swizzle_page(struct page *page)
>  {
>  	char temp[64];
>  	char *vaddr;
> @@ -791,7 +784,7 @@ i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
>  	for_each_sgt_page(page, sgt_iter, pages) {
>  		char new_bit_17 = page_to_phys(page) >> 17;
>  		if ((new_bit_17 & 0x1) != (test_bit(i, obj->bit_17) != 0)) {
> -			i915_gem_swizzle_page(page);
> +			swizzle_page(page);
>  			set_page_dirty(page);
>  		}
>  		i++;
> @@ -836,7 +829,7 @@ i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
>  	}
>  }
>  
> -void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
> +void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
>  {
>  	struct drm_i915_private *i915 = ggtt->vm.i915;
>  	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
> @@ -875,7 +868,7 @@ void i915_ggtt_init_fences(struct i915_ggtt *ggtt)
>  	}
>  	ggtt->num_fences = num_fences;
>  
> -	i915_gem_restore_fences(ggtt);
> +	intel_ggtt_restore_fences(ggtt);
>  }
>  
>  void intel_gt_init_swizzling(struct intel_gt *gt)
> diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
> similarity index 92%
> rename from drivers/gpu/drm/i915/i915_gem_fence_reg.h
> rename to drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
> index 7bd521cd7cd7..3b3eb5bf1b75 100644
> --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.h
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
> @@ -22,8 +22,8 @@
>   *
>   */
>  
> -#ifndef __I915_FENCE_REG_H__
> -#define __I915_FENCE_REG_H__
> +#ifndef __INTEL_GGTT_FENCING_H__
> +#define __INTEL_GGTT_FENCING_H__
>  
>  #include <linux/list.h>
>  #include <linux/types.h>
> @@ -53,18 +53,17 @@ struct i915_fence_reg {
>  	bool dirty;
>  };
>  
> -/* i915_gem_fence_reg.c */
>  struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt);
>  void i915_unreserve_fence(struct i915_fence_reg *fence);
>  
> -void i915_gem_restore_fences(struct i915_ggtt *ggtt);
> +void intel_ggtt_restore_fences(struct i915_ggtt *ggtt);
>  
>  void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
>  				       struct sg_table *pages);
>  void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
>  					 struct sg_table *pages);
>  
> -void i915_ggtt_init_fences(struct i915_ggtt *ggtt);
> +void intel_ggtt_init_fences(struct i915_ggtt *ggtt);
>  
>  void intel_gt_init_swizzling(struct intel_gt *gt);
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index b3116fe8d180..ce6ff9d3a350 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -26,7 +26,7 @@
>  #include <drm/drm_mm.h>
>  
>  #include "gt/intel_reset.h"
> -#include "i915_gem_fence_reg.h"
> +#include "gt/intel_ggtt_fencing.h"
>  #include "i915_selftest.h"
>  #include "i915_vma_types.h"
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 8b170c1876b3..9a15bdf31c7f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -750,7 +750,7 @@ static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
>  	for_each_engine(engine, gt, id)
>  		__intel_engine_reset(engine, stalled_mask & engine->mask);
>  
> -	i915_gem_restore_fences(gt->ggtt);
> +	intel_ggtt_restore_fences(gt->ggtt);
>  
>  	return err;
>  }
> diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c
> index 8b13f091cee2..0d6d59871308 100644
> --- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
> +++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
> @@ -35,7 +35,7 @@
>   */
>  
>  #include "i915_drv.h"
> -#include "i915_gem_fence_reg.h"
> +#include "gt/intel_ggtt_fencing.h"
>  #include "gvt.h"
>  
>  static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 82d9df15b22b..832140f4ea3d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1288,7 +1288,7 @@ static int i915_drm_resume(struct drm_device *dev)
>  		drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
>  
>  	i915_ggtt_resume(&dev_priv->ggtt);
> -	i915_gem_restore_fences(&dev_priv->ggtt);
> +	intel_ggtt_restore_fences(&dev_priv->ggtt);
>  
>  	intel_csr_ucode_resume(dev_priv);
>  
> @@ -1606,7 +1606,7 @@ static int intel_runtime_suspend(struct device *kdev)
>  
>  		intel_gt_runtime_resume(&dev_priv->gt);
>  
> -		i915_gem_restore_fences(&dev_priv->ggtt);
> +		intel_ggtt_restore_fences(&dev_priv->ggtt);
>  
>  		enable_rpm_wakeref_asserts(rpm);
>  
> @@ -1687,7 +1687,7 @@ static int intel_runtime_resume(struct device *kdev)
>  	 * we can do is to hope that things will still work (and disable RPM).
>  	 */
>  	intel_gt_runtime_resume(&dev_priv->gt);
> -	i915_gem_restore_fences(&dev_priv->ggtt);
> +	intel_ggtt_restore_fences(&dev_priv->ggtt);
>  
>  	/*
>  	 * On VLV/CHV display interrupts are part of the display
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1f5b9a584f71..ddd5b40cbbbc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -92,7 +92,6 @@
>  #include "intel_wopcm.h"
>  
>  #include "i915_gem.h"
> -#include "i915_gem_fence_reg.h"
>  #include "i915_gem_gtt.h"
>  #include "i915_gpu_error.h"
>  #include "i915_perf_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index ca5420012a22..2c53be0bd9fd 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1156,7 +1156,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>  		/* Minimal basic recovery for KMS */
>  		ret = i915_ggtt_enable_hw(dev_priv);
>  		i915_ggtt_resume(&dev_priv->ggtt);
> -		i915_gem_restore_fences(&dev_priv->ggtt);
> +		intel_ggtt_restore_fences(&dev_priv->ggtt);
>  		intel_init_clock_gating(dev_priv);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index e1ced1df13e1..2764c277326f 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -33,7 +33,6 @@
>  #include "gem/i915_gem_object.h"
>  
>  #include "i915_gem_gtt.h"
> -#include "i915_gem_fence_reg.h"
>  
>  #include "i915_active.h"
>  #include "i915_request.h"
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c
> index 623759b73bb4..7ea517a21e0b 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c
> @@ -125,7 +125,7 @@ static void pm_resume(struct drm_i915_private *i915)
>  	 */
>  	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
>  		i915_ggtt_resume(&i915->ggtt);
> -		i915_gem_restore_fences(&i915->ggtt);
> +		intel_ggtt_restore_fences(&i915->ggtt);
>  
>  		i915_gem_resume(i915);
>  	}
> -- 
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH 3/7] drm/i915: Remove manual save/resume of fence register state
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 3/7] drm/i915: Remove manual save/resume of fence register state Chris Wilson
@ 2020-03-16  7:14   ` Mika Kuoppala
  0 siblings, 0 replies; 15+ messages in thread
From: Mika Kuoppala @ 2020-03-16  7:14 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Since we always reload the fence register state on runtime resume,
> having it explicitly in the S0ix resume code is redundant. Indeed, it
> is not even being used!
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ddd5b40cbbbc..a7ea1d855359 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -539,7 +539,6 @@ struct i915_suspend_saved_registers {
>  	u32 saveSWF0[16];
>  	u32 saveSWF1[16];
>  	u32 saveSWF3[3];
> -	u64 saveFENCE[I915_MAX_NUM_FENCES];
>  	u32 savePCH_PORT_HOTPLUG;
>  	u16 saveGCDGMBUS;
>  };
> -- 
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH 4/7] drm/i915/gt: Allocate i915_fence_reg array
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 4/7] drm/i915/gt: Allocate i915_fence_reg array Chris Wilson
@ 2020-03-16  7:29   ` Mika Kuoppala
  2020-03-16 10:23     ` Chris Wilson
  2020-03-16 11:20   ` Mika Kuoppala
  1 sibling, 1 reply; 15+ messages in thread
From: Mika Kuoppala @ 2020-03-16  7:29 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Since the number of fence regs can vary dramactically between platforms,
> allocate the array on demand so we don't waste as much space.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/gt/intel_ggtt.c         |  6 ++++--
>  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 10 ++++++++++
>  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h |  1 +
>  drivers/gpu/drm/i915/gt/intel_gtt.h          |  5 +++--
>  drivers/gpu/drm/i915/i915_vma.h              |  1 +
>  5 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index bde4f64a41f7..8fcf14372d7a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -698,11 +698,13 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
>   */
>  void i915_ggtt_driver_release(struct drm_i915_private *i915)
>  {
> +	struct i915_ggtt *ggtt = &i915->ggtt;
>  	struct pagevec *pvec;
>  
> -	fini_aliasing_ppgtt(&i915->ggtt);
> +	fini_aliasing_ppgtt(ggtt);
>  
> -	ggtt_cleanup_hw(&i915->ggtt);
> +	intel_ggtt_fini_fences(ggtt);
> +	ggtt_cleanup_hw(ggtt);
>  
>  	pvec = &i915->mm.wc_stash.pvec;
>  	if (pvec->nr) {
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index 94af75673a58..b6ba68c42546 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -857,6 +857,11 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
>  	if (intel_vgpu_active(i915))
>  		num_fences = intel_uncore_read(uncore,
>  					       vgtif_reg(avail_rs.fence_num));
> +	ggtt->fence_regs = kcalloc(num_fences,
> +				   sizeof(*ggtt->fence_regs),
> +				   GFP_KERNEL);
> +	if (!ggtt->fence_regs)
> +		num_fences = 0;

So unlikely and easily shown in other debug flow that does
not warrant an err?

-Mika

>  
>  	/* Initialize fence registers to zero */
>  	for (i = 0; i < num_fences; i++) {
> @@ -871,6 +876,11 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
>  	intel_ggtt_restore_fences(ggtt);
>  }
>  
> +void intel_ggtt_fini_fences(struct i915_ggtt *ggtt)
> +{
> +	kfree(ggtt->fence_regs);
> +}
> +
>  void intel_gt_init_swizzling(struct intel_gt *gt)
>  {
>  	struct drm_i915_private *i915 = gt->i915;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
> index 3b3eb5bf1b75..9850f6a85d2a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
> @@ -64,6 +64,7 @@ void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
>  					 struct sg_table *pages);
>  
>  void intel_ggtt_init_fences(struct i915_ggtt *ggtt);
> +void intel_ggtt_fini_fences(struct i915_ggtt *ggtt);
>  
>  void intel_gt_init_swizzling(struct intel_gt *gt);
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index ce6ff9d3a350..d93ebdf3fa0e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -26,7 +26,6 @@
>  #include <drm/drm_mm.h>
>  
>  #include "gt/intel_reset.h"
> -#include "gt/intel_ggtt_fencing.h"
>  #include "i915_selftest.h"
>  #include "i915_vma_types.h"
>  
> @@ -135,6 +134,8 @@ typedef u64 gen8_pte_t;
>  #define GEN8_PDE_IPS_64K BIT(11)
>  #define GEN8_PDE_PS_2M   BIT(7)
>  
> +struct i915_fence_reg;
> +
>  #define for_each_sgt_daddr(__dp, __iter, __sgt) \
>  	__for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
>  
> @@ -333,7 +334,7 @@ struct i915_ggtt {
>  	u32 pin_bias;
>  
>  	unsigned int num_fences;
> -	struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
> +	struct i915_fence_reg *fence_regs;
>  	struct list_head fence_list;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index 2764c277326f..b958ad07f212 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -30,6 +30,7 @@
>  
>  #include <drm/drm_mm.h>
>  
> +#include "gt/intel_ggtt_fencing.h"
>  #include "gem/i915_gem_object.h"
>  
>  #include "i915_gem_gtt.h"
> -- 
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH 4/7] drm/i915/gt: Allocate i915_fence_reg array
  2020-03-16  7:29   ` Mika Kuoppala
@ 2020-03-16 10:23     ` Chris Wilson
  0 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-03-16 10:23 UTC (permalink / raw)
  To: Mika Kuoppala, intel-gfx

Quoting Mika Kuoppala (2020-03-16 07:29:36)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > Since the number of fence regs can vary dramactically between platforms,
> > allocate the array on demand so we don't waste as much space.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_ggtt.c         |  6 ++++--
> >  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 10 ++++++++++
> >  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h |  1 +
> >  drivers/gpu/drm/i915/gt/intel_gtt.h          |  5 +++--
> >  drivers/gpu/drm/i915/i915_vma.h              |  1 +
> >  5 files changed, 19 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > index bde4f64a41f7..8fcf14372d7a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > @@ -698,11 +698,13 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
> >   */
> >  void i915_ggtt_driver_release(struct drm_i915_private *i915)
> >  {
> > +     struct i915_ggtt *ggtt = &i915->ggtt;
> >       struct pagevec *pvec;
> >  
> > -     fini_aliasing_ppgtt(&i915->ggtt);
> > +     fini_aliasing_ppgtt(ggtt);
> >  
> > -     ggtt_cleanup_hw(&i915->ggtt);
> > +     intel_ggtt_fini_fences(ggtt);
> > +     ggtt_cleanup_hw(ggtt);
> >  
> >       pvec = &i915->mm.wc_stash.pvec;
> >       if (pvec->nr) {
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > index 94af75673a58..b6ba68c42546 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> > @@ -857,6 +857,11 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
> >       if (intel_vgpu_active(i915))
> >               num_fences = intel_uncore_read(uncore,
> >                                              vgtif_reg(avail_rs.fence_num));
> > +     ggtt->fence_regs = kcalloc(num_fences,
> > +                                sizeof(*ggtt->fence_regs),
> > +                                GFP_KERNEL);
> > +     if (!ggtt->fence_regs)
> > +             num_fences = 0;
> 
> So unlikely and easily shown in other debug flow that does
> not warrant an err?

Yeah, we get a warn already and it /should/ not be fatal. We should be
able to bring the display up.
-Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH 4/7] drm/i915/gt: Allocate i915_fence_reg array
  2020-03-14 12:20 ` [Intel-gfx] [PATCH 4/7] drm/i915/gt: Allocate i915_fence_reg array Chris Wilson
  2020-03-16  7:29   ` Mika Kuoppala
@ 2020-03-16 11:20   ` Mika Kuoppala
  1 sibling, 0 replies; 15+ messages in thread
From: Mika Kuoppala @ 2020-03-16 11:20 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Since the number of fence regs can vary dramactically between platforms,
> allocate the array on demand so we don't waste as much space.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_ggtt.c         |  6 ++++--
>  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 10 ++++++++++
>  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h |  1 +
>  drivers/gpu/drm/i915/gt/intel_gtt.h          |  5 +++--
>  drivers/gpu/drm/i915/i915_vma.h              |  1 +
>  5 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index bde4f64a41f7..8fcf14372d7a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -698,11 +698,13 @@ static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
>   */
>  void i915_ggtt_driver_release(struct drm_i915_private *i915)
>  {
> +	struct i915_ggtt *ggtt = &i915->ggtt;
>  	struct pagevec *pvec;
>  
> -	fini_aliasing_ppgtt(&i915->ggtt);
> +	fini_aliasing_ppgtt(ggtt);
>  
> -	ggtt_cleanup_hw(&i915->ggtt);
> +	intel_ggtt_fini_fences(ggtt);
> +	ggtt_cleanup_hw(ggtt);
>  
>  	pvec = &i915->mm.wc_stash.pvec;
>  	if (pvec->nr) {
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index 94af75673a58..b6ba68c42546 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -857,6 +857,11 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
>  	if (intel_vgpu_active(i915))
>  		num_fences = intel_uncore_read(uncore,
>  					       vgtif_reg(avail_rs.fence_num));
> +	ggtt->fence_regs = kcalloc(num_fences,
> +				   sizeof(*ggtt->fence_regs),
> +				   GFP_KERNEL);
> +	if (!ggtt->fence_regs)
> +		num_fences = 0;
>  
>  	/* Initialize fence registers to zero */
>  	for (i = 0; i < num_fences; i++) {
> @@ -871,6 +876,11 @@ void intel_ggtt_init_fences(struct i915_ggtt *ggtt)
>  	intel_ggtt_restore_fences(ggtt);
>  }
>  
> +void intel_ggtt_fini_fences(struct i915_ggtt *ggtt)
> +{
> +	kfree(ggtt->fence_regs);
> +}
> +
>  void intel_gt_init_swizzling(struct intel_gt *gt)
>  {
>  	struct drm_i915_private *i915 = gt->i915;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
> index 3b3eb5bf1b75..9850f6a85d2a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
> @@ -64,6 +64,7 @@ void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
>  					 struct sg_table *pages);
>  
>  void intel_ggtt_init_fences(struct i915_ggtt *ggtt);
> +void intel_ggtt_fini_fences(struct i915_ggtt *ggtt);
>  
>  void intel_gt_init_swizzling(struct intel_gt *gt);
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index ce6ff9d3a350..d93ebdf3fa0e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -26,7 +26,6 @@
>  #include <drm/drm_mm.h>
>  
>  #include "gt/intel_reset.h"
> -#include "gt/intel_ggtt_fencing.h"
>  #include "i915_selftest.h"
>  #include "i915_vma_types.h"
>  
> @@ -135,6 +134,8 @@ typedef u64 gen8_pte_t;
>  #define GEN8_PDE_IPS_64K BIT(11)
>  #define GEN8_PDE_PS_2M   BIT(7)
>  
> +struct i915_fence_reg;
> +
>  #define for_each_sgt_daddr(__dp, __iter, __sgt) \
>  	__for_each_sgt_daddr(__dp, __iter, __sgt, I915_GTT_PAGE_SIZE)
>  
> @@ -333,7 +334,7 @@ struct i915_ggtt {
>  	u32 pin_bias;
>  
>  	unsigned int num_fences;
> -	struct i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
> +	struct i915_fence_reg *fence_regs;
>  	struct list_head fence_list;
>  
>  	/**
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index 2764c277326f..b958ad07f212 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -30,6 +30,7 @@
>  
>  #include <drm/drm_mm.h>
>  
> +#include "gt/intel_ggtt_fencing.h"
>  #include "gem/i915_gem_object.h"
>  
>  #include "i915_gem_gtt.h"
> -- 
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 15+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915: Move GGTT fence registers under gt/
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
                   ` (6 preceding siblings ...)
  2020-03-16  7:02 ` [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Mika Kuoppala
@ 2020-03-16 15:47 ` Patchwork
  2020-03-16 16:06 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
  2020-03-16 16:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  9 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-03-16 15:47 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/7] drm/i915: Move GGTT fence registers under gt/
URL   : https://patchwork.freedesktop.org/series/74703/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
cfd159dc30dd drm/i915: Move GGTT fence registers under gt/
-:6: WARNING:TYPO_SPELLING: 'throught' may be misspelled - perhaps 'through'?
#6: 
Since the fence registers control HW detiling throught the GGTT

-:47: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#47: 
rename from drivers/gpu/drm/i915/i915_gem_fence_reg.c

total: 0 errors, 2 warnings, 0 checks, 205 lines checked
4e7c950ab87c drm/i915/gt: Pull restoration of GGTT fences underneath the GT
84d01acc1bc9 drm/i915: Remove manual save/resume of fence register state
9f9e340e8b4d drm/i915/gt: Allocate i915_fence_reg array
5003f815b7aa drm/i915/gt: Store the fence details on the fence
750dc9e7ceb3 drm/i915/gt: Only wait for GPU activity before unbinding a GGTT fence
9eeea4468363 drm/i915/gt: Make fence revocation unequivocal

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 15+ messages in thread

* [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/7] drm/i915: Move GGTT fence registers under gt/
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
                   ` (7 preceding siblings ...)
  2020-03-16 15:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
@ 2020-03-16 16:06 ` Patchwork
  2020-03-16 16:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  9 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-03-16 16:06 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/7] drm/i915: Move GGTT fence registers under gt/
URL   : https://patchwork.freedesktop.org/series/74703/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c
Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c
Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c
Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_reg.c
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 2
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function fence register handling ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1
WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function tiling swizzling details ./drivers/gpu/drm/i915/i915_gem_fence_reg.c' failed with return code 1

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 15+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/7] drm/i915: Move GGTT fence registers under gt/
  2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
                   ` (8 preceding siblings ...)
  2020-03-16 16:06 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2020-03-16 16:17 ` Patchwork
  9 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-03-16 16:17 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: series starting with [1/7] drm/i915: Move GGTT fence registers under gt/
URL   : https://patchwork.freedesktop.org/series/74703/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16972
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16972 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16972, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16972/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16972:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_tiled_fence_blits@basic:
    - fi-blb-e6850:       [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/fi-blb-e6850/igt@gem_tiled_fence_blits@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16972/fi-blb-e6850/igt@gem_tiled_fence_blits@basic.html

  
Known issues
------------

  Here are the changes found in Patchwork_16972 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@execlists:
    - fi-skl-lmem:        [PASS][3] -> [INCOMPLETE][4] ([i915#656])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/fi-skl-lmem/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16972/fi-skl-lmem/igt@i915_selftest@live@execlists.html
    - fi-icl-y:           [PASS][5] -> [DMESG-FAIL][6] ([fdo#108569])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/fi-icl-y/igt@i915_selftest@live@execlists.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16972/fi-icl-y/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@gem_contexts:
    - fi-cml-s:           [PASS][7] -> [DMESG-FAIL][8] ([i915#877])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16972/fi-cml-s/igt@i915_selftest@live@gem_contexts.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-cfl-8700k:       [INCOMPLETE][9] ([i915#656]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/fi-cfl-8700k/igt@i915_selftest@live@execlists.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16972/fi-cfl-8700k/igt@i915_selftest@live@execlists.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          [FAIL][11] ([i915#217]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16972/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
    - fi-kbl-7500u:       [FAIL][13] ([i915#323]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8137/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16972/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
  [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877


Participating hosts (48 -> 45)
------------------------------

  Additional (2): fi-skl-6770hq fi-tgl-dsi 
  Missing    (5): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8137 -> Patchwork_16972

  CI-20190529: 20190529
  CI_DRM_8137: 5786b5e77cc17a1b494b9bdf3c3f29eedc2e2e7d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5510: e100092d50105463f58db531fa953c70cc58bb10 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16972: 9eeea446836327fedf640ae8513c72a66c71dedf @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9eeea4468363 drm/i915/gt: Make fence revocation unequivocal
750dc9e7ceb3 drm/i915/gt: Only wait for GPU activity before unbinding a GGTT fence
5003f815b7aa drm/i915/gt: Store the fence details on the fence
9f9e340e8b4d drm/i915/gt: Allocate i915_fence_reg array
84d01acc1bc9 drm/i915: Remove manual save/resume of fence register state
4e7c950ab87c drm/i915/gt: Pull restoration of GGTT fences underneath the GT
cfd159dc30dd drm/i915: Move GGTT fence registers under gt/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16972/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2020-03-16 16:17 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-14 12:20 [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Chris Wilson
2020-03-14 12:20 ` [Intel-gfx] [PATCH 2/7] drm/i915/gt: Pull restoration of GGTT fences underneath the GT Chris Wilson
2020-03-14 12:20 ` [Intel-gfx] [PATCH 3/7] drm/i915: Remove manual save/resume of fence register state Chris Wilson
2020-03-16  7:14   ` Mika Kuoppala
2020-03-14 12:20 ` [Intel-gfx] [PATCH 4/7] drm/i915/gt: Allocate i915_fence_reg array Chris Wilson
2020-03-16  7:29   ` Mika Kuoppala
2020-03-16 10:23     ` Chris Wilson
2020-03-16 11:20   ` Mika Kuoppala
2020-03-14 12:20 ` [Intel-gfx] [PATCH 5/7] drm/i915/gt: Store the fence details on the fence Chris Wilson
2020-03-14 12:20 ` [Intel-gfx] [PATCH 6/7] drm/i915/gt: Only wait for GPU activity before unbinding a GGTT fence Chris Wilson
2020-03-14 12:20 ` [Intel-gfx] [PATCH 7/7] drm/i915/gt: Make fence revocation unequivocal Chris Wilson
2020-03-16  7:02 ` [Intel-gfx] [PATCH 1/7] drm/i915: Move GGTT fence registers under gt/ Mika Kuoppala
2020-03-16 15:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] " Patchwork
2020-03-16 16:06 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-16 16:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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