Updated VLV patchset

Updated VLV patchset

[Jesse Barnes]

With the new boards, we've been able to test a few more things.  This
set is still a WIP, but I wanted to get it out for review.  I also need
to do some additional testing when I get back from FOSDEM, but others
with VLV systems can try these out and let me know how it goes.

Thanks,
Jesse

[PATCH 01/22] drm/i915: add more VLV IDs

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 51e9c76..69d0637 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -387,6 +387,9 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 	INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
 	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
+	INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
 	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 	{0, 0, 0}
-- 
1.7.9.5

[PATCH 02/22] drm/i915: remove VLV MSI IRQ hack

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_irq.c |    8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6ba0573..f781ff0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1999,7 +1999,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	u32 enable_mask;
 	u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
 	u32 render_irqs;
-	u16 msid;
 
 	enable_mask = I915_DISPLAY_PORT_INTERRUPT;
 	enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
@@ -2018,13 +2017,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	dev_priv->pipestat[0] = 0;
 	dev_priv->pipestat[1] = 0;
 
-	/* Hack for broken MSIs on VLV */
-	pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
-	pci_read_config_word(dev->pdev, 0x98, &msid);
-	msid &= 0xff; /* mask out delivery bits */
-	msid |= (1<<14);
-	pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
-
 	I915_WRITE(PORT_HOTPLUG_EN, 0);
 	POSTING_READ(PORT_HOTPLUG_EN);
 
-- 
1.7.9.5

[PATCH 03/22] drm/i915: add UCGCTL4 to display reg check on VLV

[Jesse Barnes]

Add a few regs needed for various clock gating init purposes and make
sure they don't fall into the display offset range on VLV.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 69d0637..13b9b4f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1208,6 +1208,7 @@ static bool IS_DISPLAYREG(u32 reg)
 	case GEN7_HALF_SLICE_CHICKEN1:
 	case GEN6_MBCTL:
 	case GEN6_UCGCTL2:
+	case GEN7_UCGCTL4:
 		return false;
 	default:
 		break;
-- 
1.7.9.5

[PATCH 04/22] drm/i915: implement WaGTEnableMiFlush on VLV

[Jesse Barnes]

We don't generally use MI_FLUSH these days, but this bit may affect
other flushing logic, so set it to be safe.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2bd074a..5a9e26a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -511,6 +511,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
 			I915_WRITE(GFX_MODE_GEN7,
 				   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 				   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
+		if (IS_VALLEYVIEW(dev))
+			I915_WRITE(MI_MODE, I915_READ(MI_MODE) |
+				   _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE));
 	}
 
 	if (INTEL_INFO(dev)->gen >= 5) {
-- 
1.7.9.5

[PATCH 05/22] drm/i915: enable force wake, disable LLC on VLV

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 13b9b4f..b35b479 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -276,6 +276,8 @@ static const struct intel_device_info intel_valleyview_m_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.is_valleyview = 1,
+	.has_force_wake = 1,
+	.has_llc = 0,
 };
 
 static const struct intel_device_info intel_valleyview_d_info = {
@@ -285,6 +287,8 @@ static const struct intel_device_info intel_valleyview_d_info = {
 	.has_bsd_ring = 1,
 	.has_blt_ring = 1,
 	.is_valleyview = 1,
+	.has_force_wake = 1,
+	.has_llc = 0,
 };
 
 static const struct intel_device_info intel_haswell_d_info = {
-- 
1.7.9.5

[PATCH 06/22] drm/i915: add power context allocation and setup on VLV

[Jesse Barnes]

The Gunit has a separate reg for this, so allocate some stolen space for
the power context and initialize the reg.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h        |    2 ++
 drivers/gpu/drm/i915/i915_gem_stolen.c |   41 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h        |    1 +
 3 files changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f4ae73d..34f01a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -928,6 +928,8 @@ typedef struct drm_i915_private {
 	struct drm_mm_node *compressed_fb;
 	struct drm_mm_node *compressed_llb;
 
+	struct drm_mm_node *vlv_pctx;
+
 	unsigned long last_gpu_reset;
 
 	/* list of fbdev register on this device */
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f21ae17..ac11a41 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -171,11 +171,49 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev)
 	dev_priv->cfb_size = 0;
 }
 
+static void i915_setup_pctx(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_mm_node *pctx;
+	unsigned long pctx_paddr;
+	int pctx_size = 24*1024;
+
+	pctx = drm_mm_search_free(&dev_priv->mm.stolen, pctx_size, 4096, 0);
+	if (pctx)
+		pctx = drm_mm_get_block(pctx, pctx_size, 4096);
+	if (!pctx)
+		goto err;
+
+	pctx_paddr = dev_priv->mm.stolen_base + pctx->start;
+	if (!pctx_paddr)
+		goto err_free_pctx;
+
+	dev_priv->vlv_pctx = pctx;
+	I915_WRITE(VLV_PCBR, pctx_paddr);
+
+	return;
+
+err_free_pctx:
+	drm_mm_put_block(pctx);
+err:
+	DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
+}
+
+static void i915_cleanup_pctx(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(VLV_PCBR, 0);
+	drm_mm_put_block(dev_priv->vlv_pctx);
+}
+
 void i915_gem_cleanup_stolen(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	i915_gem_stolen_cleanup_compression(dev);
+	if (IS_VALLEYVIEW(dev) && i915_powersave)
+		i915_cleanup_pctx(dev);
 	drm_mm_takedown(&dev_priv->mm.stolen);
 }
 
@@ -193,6 +231,9 @@ int i915_gem_init_stolen(struct drm_device *dev)
 	/* Basic memrange allocator for stolen space */
 	drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->mm.gtt->stolen_size);
 
+	if (IS_VALLEYVIEW(dev) && i915_powersave)
+		i915_setup_pctx(dev);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 286bab3..c785750 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -561,6 +561,7 @@
 #define ISR		0x020ac
 #define VLV_GUNIT_CLOCK_GATE	0x182060
 #define   GCFG_DIS		(1<<8)
+#define VLV_PCBR	0x182120
 #define VLV_IIR_RW	0x182084
 #define VLV_IER		0x1820a0
 #define VLV_IIR		0x1820a4
-- 
1.7.9.5

[PATCH 07/22] drm/i915: new register for IS_DISPLAYREG

[Jesse Barnes]

From: Ben Widawsky <ben@bwidawsk.net>

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_drv.c |    7 +++----
 drivers/gpu/drm/i915/i915_reg.h |    1 +
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b35b479..28d5992 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1193,10 +1193,6 @@ static bool IS_DISPLAYREG(u32 reg)
 	    reg <= VLV_ISR)
 		return false;
 
-	if (reg == FORCEWAKE_VLV ||
-	    reg == FORCEWAKE_ACK_VLV)
-		return false;
-
 	if (reg == GEN6_GDRST)
 		return false;
 
@@ -1213,6 +1209,9 @@ static bool IS_DISPLAYREG(u32 reg)
 	case GEN6_MBCTL:
 	case GEN6_UCGCTL2:
 	case GEN7_UCGCTL4:
+	case FORCEWAKE_VLV:
+	case FORCEWAKE_ACK_VLV:
+	case VLV_GTLC_WAKE_CTRL:
 		return false;
 	default:
 		break;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c785750..7e13f34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4212,6 +4212,7 @@
 #define  FORCEWAKE_ACK_VLV			0x1300b4
 #define  FORCEWAKE_ACK_HSW			0x130044
 #define  FORCEWAKE_ACK				0x130090
+#define  VLV_GTLC_WAKE_CTRL			0x130090
 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
 #define   FORCEWAKE_KERNEL			0x1
 #define   FORCEWAKE_USER			0x2
-- 
1.7.9.5

[PATCH 08/22] drm/i915: allow force wake on VLV

[Jesse Barnes]

There's a separate bit in the Gunit to allow force wake control.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem.c |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ad98db5..fa12248 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3987,6 +3987,11 @@ int i915_gem_init(struct drm_device *dev)
 	int ret;
 
 	mutex_lock(&dev->struct_mutex);
+
+	if (IS_VALLEYVIEW(dev)) {
+		/* Make sure we can use force wake */
+		I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
+	}
 	i915_gem_init_global_gtt(dev);
 	ret = i915_gem_init_hw(dev);
 	mutex_unlock(&dev->struct_mutex);
-- 
1.7.9.5

[PATCH 09/22] drm/i915: more clock gating disables on VLV

[Jesse Barnes]

Disable a swath of clock gating bits pending further testing and
measurement.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_pm.c |   11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e8d416c..2820707 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3851,7 +3851,16 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
 	 * Disable clock gating on th GCFG unit to prevent a delay
 	 * in the reporting of vblank events.
 	 */
-	I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
+	I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
+
+	/* Need testing & additional review on newer hw */
+	I915_WRITE(0x9400, 0xffffffff);
+	I915_WRITE(0x9404, 0xffffffff);
+	I915_WRITE(0x9408, 0xffffffff);
+	I915_WRITE(0x940c, 0xffffffff);
+	I915_WRITE(0x9410, 0xffffffff);
+	I915_WRITE(0x9414, 0xffffffff);
+	I915_WRITE(0x9418, 0xffffffff);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)
-- 
1.7.9.5

[PATCH 10/22] drm/i915: don't init LVDS on VLV

[Jesse Barnes]

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_lvds.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 8c61876..feef18c 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -1024,6 +1024,9 @@ static bool intel_lvds_supported(struct drm_device *dev)
 	if (HAS_PCH_SPLIT(dev))
 		return true;
 
+	if (IS_VALLEYVIEW(dev))
+		return false;
+
 	/* Otherwise LVDS was only attached to mobile products,
 	 * except for the inglorious 830gm */
 	return IS_MOBILE(dev) && !IS_I830(dev);
-- 
1.7.9.5

[PATCH 11/22] drm/i915: fixup port enumeration on VLV

[Jesse Barnes]

From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>

Updated to reflect newer boards.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c8a9b7d..9f2f817 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8092,7 +8092,8 @@ static void intel_setup_outputs(struct drm_device *dev)
 		 * IMP : To route DP in PORT_B in VLV X0 board, make sure to remove the
 		 * jumper from J3K1
 		 */
-		intel_dp_init(dev, DP_B, PORT_B);
+		// Only for testing - Vijay
+		//intel_dp_init(dev, DP_B, PORT_B);
 
 		/*
 		 * To get HDMI output on VLV X0, comment the above line (intel_dp_init)
@@ -8101,13 +8102,13 @@ static void intel_setup_outputs(struct drm_device *dev)
 		 * IMP : To route HDMI in PORT_B in VLV X0 board, make sure to connect
 		 * the jumper in J3K1
 		 */
-		/* intel_hdmi_init(dev, SDVOB, PORT_B); */
+		intel_hdmi_init(dev, SDVOB, PORT_B);
 
 		/*
 		 * For VLV X0, the eDP is supported on PORT_C after rework.
 		 * Uncomment the following line if the board is reworked for eDP
 		 */
-		/* intel_dp_init(dev, DP_C, PORT_C); */
+		intel_dp_init(dev, DP_C, PORT_C);
 	} else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
 		bool found = false;
 
-- 
1.7.9.5

[PATCH 12/22] drm/i915: Fix VLV hdmi limits

[Jesse Barnes]

Fix the correct hdmi limits for VLV A0

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9f2f817..83d629d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -387,12 +387,12 @@ static const intel_limit_t intel_limits_vlv_dac = {
 };
 
 static const intel_limit_t intel_limits_vlv_hdmi = {
-	.dot = { .min = 20000, .max = 165000 },
-	.vco = { .min = 4000000, .max = 5994000},
-	.n = { .min = 1, .max = 7 },
+	.dot = { .min = 25000, .max = 180000 },
+	.vco = { .min = 4040000, .max = 5960000 },
+	.n = { .min = 1, .max = 5 },
 	.m = { .min = 60, .max = 300 }, /* guess */
 	.m1 = { .min = 2, .max = 3 },
-	.m2 = { .min = 11, .max = 156 },
+	.m2 = { .min = 15, .max = 149 },
 	.p = { .min = 10, .max = 30 },
 	.p1 = { .min = 2, .max = 3 },
 	.p2 = { .dot_limit = 270000,
-- 
1.7.9.5

[PATCH 13/22] drm/i915: update DPIO constants for VLV

[Jesse Barnes]

Separate bits for HDMI and DP.

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 83d629d..2bc8ce7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4307,15 +4307,26 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	mdiv |= DPIO_ENABLE_CALIBRATION;
 	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
 
-	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
+	//intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
 
 	pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
 		(3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
 		(7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
 		(5 << DPIO_CLK_BIAS_CTL_SHIFT);
-	intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
 
-	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
+	//intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
+	if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
+		intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), 0x0d770000);
+	else
+		// for DP/eDP. We'll not worry about VGA
+		intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), 0x0d740000);
+
+	intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01C00000);
+
+	//intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
+	intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f0051);
+
+	intel_dpio_write(dev_priv, 0x804C, 0x87871000);
 
 	dpll |= DPLL_VCO_ENABLE;
 	I915_WRITE(DPLL(pipe), dpll);
-- 
1.7.9.5

[PATCH 14/22] drm/i915: add HMDI workarounds on VLV

[Jesse Barnes]

Need to do some extra work at PLL disable time to allow HDMI to come
back up on the next mode set.
  v2: take dpio lock around update - jbarnes
      only do WA on VLV -jbarnes

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2bc8ce7..c0cb254 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1492,6 +1492,14 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	int reg;
 	u32 val;
 
+	if (IS_VALLEYVIEW(dev_priv->dev)) {
+		mutex_lock(&dev_priv->dpio_lock);
+		// Flicker WA for HDMI
+		intel_dpio_write(dev_priv, 0x8200, 0x00000000);
+		intel_dpio_write(dev_priv, 0x8204, 0x00e00060);
+		mutex_unlock(&dev_priv->dpio_lock);
+	}
+
 	/* Don't disable pipe A or pipe A PLLs if needed */
 	if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
 		return;
@@ -4299,6 +4307,12 @@ static void vlv_update_pll(struct drm_crtc *crtc,
 	 * In Valleyview PLL and program lane counter registers are exposed
 	 * through DPIO interface
 	 */
+
+	// program DD1 Tx lane resets sets to default
+	// WA for HDMI flicker issue
+	intel_dpio_write(dev_priv, 0x8200, 0x10080);
+	intel_dpio_write(dev_priv, 0x8204, 0x00600060);
+
 	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
 	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
 	mdiv |= ((bestn << DPIO_N_SHIFT));
-- 
1.7.9.5

[PATCH 15/22] drm/i915: move DPIO init to init and resume, not unload

[Jesse Barnes]

The GOP should do this for us once at boot time, but on resume and to
defend against the various BIOS versions, we init once at load time and
also in the resume path.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |    5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c0cb254..961ac69 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8556,6 +8556,8 @@ void intel_modeset_init_hw(struct drm_device *dev)
 
 	intel_init_clock_gating(dev);
 
+	vlv_init_dpio(dev);
+
 	mutex_lock(&dev->struct_mutex);
 	intel_enable_gt_powersave(dev);
 	mutex_unlock(&dev->struct_mutex);
@@ -8947,9 +8949,6 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
 	ironlake_teardown_rc6(dev);
 
-	if (IS_VALLEYVIEW(dev))
-		vlv_init_dpio(dev);
-
 	mutex_unlock(&dev->struct_mutex);
 
 	/* Disable the irq before mode object teardown, for the irq might
-- 
1.7.9.5

[PATCH 16/22] drm/i915: VLV hack: Disable wm for VLV

[Jesse Barnes]

From: Vijay Purushothaman <vijay.a.purushothaman@intel.com>

Pondicherry should take care in most cases.

Watermark update is causing driver crash with divide error. Look again.
For current usage, not needed.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2820707..7d812ba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4050,7 +4050,8 @@ void intel_init_pm(struct drm_device *dev)
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_VALLEYVIEW(dev)) {
-		dev_priv->display.update_wm = valleyview_update_wm;
+//		dev_priv->display.update_wm = valleyview_update_wm;
+		dev_priv->display.update_wm = NULL;
 		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm,
 		dev_priv->display.init_clock_gating =
 			valleyview_init_clock_gating;
-- 
1.7.9.5

[PATCH 17/22] drm/i915: VLV hack: force DP to report connected

[Jesse Barnes]

---
 drivers/gpu/drm/i915/intel_dp.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f4c8723..f346bab 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2399,6 +2399,10 @@ intel_dp_detect(struct drm_connector *connector, bool force)
 	else
 		status = g4x_dp_detect(intel_dp);
 
+	/* HOTPLUG Detect is not working even though it is enabled */
+	if (IS_VALLEYVIEW(connector->dev))
+		status = connector_status_connected;
+
 	if (status != connector_status_connected)
 		return status;
 
-- 
1.7.9.5

[PATCH 18/22] drm/i915: add flush control reg to IS_DISPLAYREG check

[Jesse Barnes]

With the PTE poking code pulled into i915, we need to make sure we don't
add the display offset to our TLB flush writes.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 28d5992..dde54b1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1212,6 +1212,7 @@ static bool IS_DISPLAYREG(u32 reg)
 	case FORCEWAKE_VLV:
 	case FORCEWAKE_ACK_VLV:
 	case VLV_GTLC_WAKE_CTRL:
+	case GFX_FLSH_CNTL_GEN6:
 		return false;
 	default:
 		break;
-- 
1.7.9.5

[PATCH 19/22] drm/i915: use gen6 stolen check on VLV

[Jesse Barnes]

It uses the same bit definitions.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eac2cec..3900b98 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -725,7 +725,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 	dev_priv->mm.gtt->gtt_total_entries =
 		gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);
-	if (INTEL_INFO(dev)->gen < 7)
+	if (INTEL_INFO(dev)->gen < 7 || IS_VALLEYVIEW(dev))
 		dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
 	else
 		dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl);
-- 
1.7.9.5

[PATCH 20/22] drm/i915: add Punit read/write routines for VLV

[Jesse Barnes]

Slightly different than other platforms.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 drivers/gpu/drm/i915/i915_reg.h |   22 ++++++++++++
 drivers/gpu/drm/i915/intel_pm.c |   74 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 98 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 34f01a9..60eee7d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1749,6 +1749,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
 
 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
 
 #define __i915_read(x, y) \
 	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e13f34..7325b7a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4335,6 +4335,28 @@
 #define GEN6_PCODE_DATA				0x138128
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 
+#define VLV_IOSF_DOORBELL_REQ			0x182100
+#define   IOSF_DEVFN_SHIFT			24
+#define   IOSF_OPCODE_SHIFT			16
+#define   IOSF_PORT_SHIFT			8
+#define   IOSF_BYTE_ENABLES_SHIFT		4
+#define   IOSF_BAR_SHIFT			1
+#define   IOSF_SB_BUSY				(1<<0)
+#define   IOSF_PORT_PUNIT			0x4
+#define VLV_IOSF_DATA				0x182104
+#define VLV_IOSF_ADDR				0x182108
+
+#define PUNIT_REG_GPU_LFM			0xd3
+#define PUNIT_REG_GPU_FREQ_REQ			0xd4
+#define PUNIT_REG_GPU_FREQ_STS			0xd8
+#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
+
+#define PUNIT_OPCODE_REG_READ			6
+#define PUNIT_OPCODE_REG_WRITE			7
+
+#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
+#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
+
 #define GEN6_GT_CORE_STATUS		0x138060
 #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
 #define   GEN6_RCn_MASK			7
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7d812ba..bb97309 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4356,3 +4356,77 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
 
 	return 0;
 }
+
+int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+{
+	u32 cmd, devfn, opcode, port, be, bar;
+
+	bar = 0;
+	be = 0xf;
+	port = IOSF_PORT_PUNIT;
+	opcode = PUNIT_OPCODE_REG_READ;
+	devfn = 16;
+
+	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
+		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |
+		(bar << IOSF_BAR_SHIFT);
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+		DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
+		return -EAGAIN;
+	}
+
+	I915_WRITE(VLV_IOSF_ADDR, addr);
+	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
+
+	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
+		     500)) {
+		DRM_ERROR("timeout waiting for pcode read (%d) to finish\n",
+			  addr);
+		return -ETIMEDOUT;
+	}
+
+	*val = I915_READ(VLV_IOSF_DATA);
+	I915_WRITE(VLV_IOSF_DATA, 0);
+
+	return 0;
+}
+
+int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+{
+	u32 cmd, devfn, opcode, port, be, bar;
+
+	bar = 0;
+	be = 0xf;
+	port = IOSF_PORT_PUNIT;
+	opcode = PUNIT_OPCODE_REG_WRITE;
+	devfn = 16;
+
+	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
+		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |
+		(bar << IOSF_BAR_SHIFT);
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
+		DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
+		return -EAGAIN;
+	}
+
+	I915_WRITE(VLV_IOSF_ADDR, addr);
+	I915_WRITE(VLV_IOSF_DATA, val);
+	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
+
+	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
+		     500)) {
+		DRM_ERROR("timeout waiting for pcode write (%d) to finish\n",
+			  addr);
+		return -ETIMEDOUT;
+	}
+
+	I915_WRITE(VLV_IOSF_DATA, 0);
+
+	return 0;
+}
-- 
1.7.9.5

[PATCH 21/22] drm/i915: add media well to VLV force wake routines

[Jesse Barnes]

We could split this out into a separate routine at some point as an
optimization.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    3 +++
 drivers/gpu/drm/i915/i915_reg.h |    3 +++
 drivers/gpu/drm/i915/intel_pm.c |    8 +++++++-
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index dde54b1..8440d28a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1211,7 +1211,10 @@ static bool IS_DISPLAYREG(u32 reg)
 	case GEN7_UCGCTL4:
 	case FORCEWAKE_VLV:
 	case FORCEWAKE_ACK_VLV:
+	case FORCEWAKE_MEDIA_VLV:
+	case FORCEWAKE_ACK_MEDIA_VLV:
 	case VLV_GTLC_WAKE_CTRL:
+	case VLV_GTLC_PW_STATUS:
 	case GFX_FLSH_CNTL_GEN6:
 		return false;
 	default:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7325b7a..39c6318 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4210,9 +4210,12 @@
 #define  FORCEWAKE				0xA18C
 #define  FORCEWAKE_VLV				0x1300b0
 #define  FORCEWAKE_ACK_VLV			0x1300b4
+#define  FORCEWAKE_MEDIA_VLV			0x1300b8
+#define  FORCEWAKE_ACK_MEDIA_VLV		0x1300bc
 #define  FORCEWAKE_ACK_HSW			0x130044
 #define  FORCEWAKE_ACK				0x130090
 #define  VLV_GTLC_WAKE_CTRL			0x130090
+#define  VLV_GTLC_PW_STATUS			0x130094
 #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
 #define   FORCEWAKE_KERNEL			0x1
 #define   FORCEWAKE_USER			0x2
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bb97309..36f019b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4260,10 +4260,15 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 		DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
 
 	I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
+	I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
 
 	if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
 			    FORCEWAKE_ACK_TIMEOUT_MS))
-		DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
+		DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
+
+	if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) & 1),
+			    FORCEWAKE_ACK_TIMEOUT_MS))
+		DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
 
 	__gen6_gt_wait_for_thread_c0(dev_priv);
 }
@@ -4271,6 +4276,7 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
+	I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
 	/* The below doubles as a POSTING_READ */
 	gen6_gt_check_fifodbg(dev_priv);
 }
-- 
1.7.9.5

[PATCH 22/22] drm/i915: turbo & RC6 support for VLV

[Jesse Barnes]

Uses slightly different interfaces than other platforms.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_pm.c |  148 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 144 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 36f019b..b7922b8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2372,6 +2372,47 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 	trace_intel_gpu_freq_change(val * 50);
 }
 
+void valleyview_set_rps(struct drm_device *dev, u8 val)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long timeout = jiffies + msecs_to_jiffies(100);
+	u32 limits = gen6_rps_limits(dev_priv, &val);
+	u32 pval;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+	WARN_ON(val > dev_priv->rps.max_delay);
+	WARN_ON(val < dev_priv->rps.min_delay);
+
+	if (val == dev_priv->rps.cur_delay)
+		return;
+
+	valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+
+	do {
+		valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+		if (time_after(jiffies, timeout)) {
+			DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
+			break;
+		}
+		udelay(10);
+	} while (pval & 1);
+
+	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+	if ((pval >> 8) != val)
+		DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
+			  val, pval >> 8);
+
+	/* Make sure we continue to get interrupts
+	 * until we hit the minimum or maximum frequencies.
+	 */
+	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
+
+	dev_priv->rps.cur_delay = val;
+
+	trace_intel_gpu_freq_change(val * 50);
+}
+
+
 static void gen6_disable_rps(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2615,6 +2656,100 @@ static void gen6_update_ring_freq(struct drm_device *dev)
 	}
 }
 
+static void valleyview_enable_rps(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_ring_buffer *ring;
+	u32 gtfifodbg, val;
+	int i;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	if ((gtfifodbg = I915_READ(GTFIFODBG))) {
+		DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
+		I915_WRITE(GTFIFODBG, gtfifodbg);
+	}
+
+	gen6_gt_force_wake_get(dev_priv);
+
+	I915_WRITE(GEN6_RC_SLEEP, 0);
+
+	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
+	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
+	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 0x19);
+
+	for_each_ring(ring, dev_priv, i)
+		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
+	I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
+
+	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+	I915_WRITE(GEN6_RP_UP_EI, 66000);
+	I915_WRITE(GEN6_RP_DOWN_EI, 350000);
+
+	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+	I915_WRITE(GEN6_RP_CONTROL,
+		   GEN6_RP_MEDIA_TURBO |
+		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		   GEN6_RP_MEDIA_IS_GFX |
+		   GEN6_RP_ENABLE |
+		   GEN6_RP_UP_BUSY_AVG |
+		   GEN6_RP_DOWN_IDLE_CONT);
+
+	/* allows RC6 residency counter to work */
+	I915_WRITE(0x138104, 0xffff00ff);
+	I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE);
+
+	valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
+	DRM_DEBUG_DRIVER("max GPU freq: %d\n", val);
+	dev_priv->rps.max_delay = val;
+
+	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+	DRM_DEBUG_DRIVER("min GPU freq: %d\n", val);
+	dev_priv->rps.min_delay = val;
+
+	valleyview_punit_read(dev_priv, PUNIT_FUSE_BUS2, &val);
+	DRM_DEBUG_DRIVER("max GPLL freq: %d\n", val);
+
+	valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
+	DRM_DEBUG_DRIVER("DDR speed: ");
+	if (((val >> 6) & 3) == 0) {
+		dev_priv->mem_freq = 800;
+		printk("800 MHz\n");
+	} else if (((val >> 6) & 3) == 1) {
+		printk("1066 MHz\n");
+		dev_priv->mem_freq = 1066;
+	} else if (((val >> 6) & 3) == 2) {
+		printk("1333 MHz\n");
+		dev_priv->mem_freq = 1333;
+	} else if (((val >> 6) & 3) == 3)
+		printk("invalid\n");
+	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 8 ? "yes" : "no");
+	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+
+	DRM_DEBUG_DRIVER("current GPU freq: %x\n", (val >> 8) & 0xff);
+	dev_priv->rps.cur_delay = (val >> 8) & 0xff;
+
+	val = 0xd500;
+	DRM_DEBUG_DRIVER("setting GPU freq to %d\n", (val >> 8) & 0xff);
+
+	valleyview_set_rps(dev_priv->dev, (val >> 8) & 0xff);
+
+	/* requires MSI enabled */
+	I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
+	spin_lock_irq(&dev_priv->rps.lock);
+	WARN_ON(dev_priv->rps.pm_iir != 0);
+	I915_WRITE(GEN6_PMIMR, 0);
+	spin_unlock_irq(&dev_priv->rps.lock);
+	/* enable all PM interrupts */
+	I915_WRITE(GEN6_PMINTRMSK, 0);
+
+	gen6_gt_force_wake_put(dev_priv);
+}
+
 void ironlake_teardown_rc6(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3341,7 +3476,7 @@ void intel_disable_gt_powersave(struct drm_device *dev)
 	if (IS_IRONLAKE_M(dev)) {
 		ironlake_disable_drps(dev);
 		ironlake_disable_rc6(dev);
-	} else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
+	} else if (INTEL_INFO(dev)->gen >= 6) {
 		cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 		mutex_lock(&dev_priv->rps.hw_lock);
 		gen6_disable_rps(dev);
@@ -3357,8 +3492,13 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 	struct drm_device *dev = dev_priv->dev;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
-	gen6_enable_rps(dev);
-	gen6_update_ring_freq(dev);
+
+	if (IS_VALLEYVIEW(dev)) {
+		valleyview_enable_rps(dev);
+	} else {
+		gen6_enable_rps(dev);
+		gen6_update_ring_freq(dev);
+	}
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
@@ -3370,7 +3510,7 @@ void intel_enable_gt_powersave(struct drm_device *dev)
 		ironlake_enable_drps(dev);
 		ironlake_enable_rc6(dev);
 		intel_init_emon(dev);
-	} else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
+	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {
 		/*
 		 * PCU communication is slow and this doesn't need to be
 		 * done at any specific time, so do this out of our fast path
-- 
1.7.9.5

Re: [PATCH 01/22] drm/i915: add more VLV IDs

[Rodrigo Vivi]

I was going to review them, but I couldn't find vlv ids at bspec.
where is the ids list?

On Sat, Feb 2, 2013 at 10:56 AM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |    3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 51e9c76..69d0637 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -387,6 +387,9 @@ static const struct pci_device_id pciidlist[] = {           /* aka */
>         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
>         INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
>         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
> +       INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
> +       INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
> +       INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
>         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
>         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
>         {0, 0, 0}
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 01/22] drm/i915: add more VLV IDs

[Jesse Barnes]

The IDs are off in the VLV doc sites, which are separate and internal
only atm.

Jesse

On Sat, 2 Feb 2013 15:30:59 -0200
Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:

> I was going to review them, but I couldn't find vlv ids at bspec.
> where is the ids list?
> 
> On Sat, Feb 2, 2013 at 10:56 AM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c |    3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 51e9c76..69d0637 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -387,6 +387,9 @@ static const struct pci_device_id pciidlist[] = {           /* aka */
> >         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
> >         INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
> >         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
> > +       INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
> > +       INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
> > +       INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
> >         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
> >         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
> >         {0, 0, 0}
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 

Re: [PATCH 04/22] drm/i915: implement WaGTEnableMiFlush on VLV

[Ville Syrjälä]

On Sat, Feb 02, 2013 at 01:56:08PM +0100, Jesse Barnes wrote:
> We don't generally use MI_FLUSH these days, but this bit may affect
> other flushing logic, so set it to be safe.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c |    3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 2bd074a..5a9e26a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -511,6 +511,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
>  			I915_WRITE(GFX_MODE_GEN7,
>  				   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
>  				   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
> +		if (IS_VALLEYVIEW(dev))
> +			I915_WRITE(MI_MODE, I915_READ(MI_MODE) |
> +				   _MASKED_BIT_ENABLE(MI_FLUSH_ENABLE));

Include a comment with the WA name?

Also this WA seems to be present since SNB. So should the check be for
'gen>=6' instead of VLV? Hmm. It seems that used to be the case actually
and then the WA was removed in commit:

 commit 8d79c3490aecfe6e51f0ba6f9780746fb1434954
 Author: Eric Anholt <eric@anholt.net>
 Date:   Thu Jan 19 10:50:05 2012 -0800

    drm/i915: Remove the MI_FLUSH_ENABLE setting.
    
    We have always been using the wrong bit -- it's bit 12.  However, the
    bit also doesn't do anything -- hardware has always accepted the
    MI_FLUSH command even when it was specced not to.
    
    Given that there is only one MI_FLUSH emitted in all of the driver
    stack on gen6+ (in i965_video.c of the 2d driver, and it should be
    using other code to do its flush instead), just remove the MI_FLUSH
    enable instead of trying to fix it.
    
    Signed-off-by: Eric Anholt <eric@anholt.net>
    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
    Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
    Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Looks like the wrong bit part was fixed at some point.

This patch needs to be refreshed anyway since the code was shuffled
around a bit.

>  	}
>  
>  	if (INTEL_INFO(dev)->gen >= 5) {
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 05/22] drm/i915: enable force wake, disable LLC on VLV

[Ville Syrjälä]

On Sat, Feb 02, 2013 at 01:56:09PM +0100, Jesse Barnes wrote:
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 13b9b4f..b35b479 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -276,6 +276,8 @@ static const struct intel_device_info intel_valleyview_m_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.is_valleyview = 1,
> +	.has_force_wake = 1,
> +	.has_llc = 0,
>  };
>  
>  static const struct intel_device_info intel_valleyview_d_info = {
> @@ -285,6 +287,8 @@ static const struct intel_device_info intel_valleyview_d_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.is_valleyview = 1,
> +	.has_force_wake = 1,
> +	.has_llc = 0,
>  };

It looks like we never set these flags to 0 explicitly. It's using
named initializers so the rest gets initialized to 0 anyway.

>  
>  static const struct intel_device_info intel_haswell_d_info = {
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 20/22] drm/i915: add Punit read/write routines for VLV

[Jani Nikula]

On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Slightly different than other platforms.

I'll do more review later, just pointing out an obvious bug below.

BR,
Jani.


>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |    2 ++
>  drivers/gpu/drm/i915/i915_reg.h |   22 ++++++++++++
>  drivers/gpu/drm/i915/intel_pm.c |   74 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 98 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 34f01a9..60eee7d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1749,6 +1749,8 @@ int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
>  
>  int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
>  int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
> +int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
>  
>  #define __i915_read(x, y) \
>  	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7e13f34..7325b7a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4335,6 +4335,28 @@
>  #define GEN6_PCODE_DATA				0x138128
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  
> +#define VLV_IOSF_DOORBELL_REQ			0x182100
> +#define   IOSF_DEVFN_SHIFT			24
> +#define   IOSF_OPCODE_SHIFT			16
> +#define   IOSF_PORT_SHIFT			8
> +#define   IOSF_BYTE_ENABLES_SHIFT		4
> +#define   IOSF_BAR_SHIFT			1
> +#define   IOSF_SB_BUSY				(1<<0)
> +#define   IOSF_PORT_PUNIT			0x4
> +#define VLV_IOSF_DATA				0x182104
> +#define VLV_IOSF_ADDR				0x182108
> +
> +#define PUNIT_REG_GPU_LFM			0xd3
> +#define PUNIT_REG_GPU_FREQ_REQ			0xd4
> +#define PUNIT_REG_GPU_FREQ_STS			0xd8
> +#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ		0xdc
> +
> +#define PUNIT_OPCODE_REG_READ			6
> +#define PUNIT_OPCODE_REG_WRITE			7
> +
> +#define PUNIT_FUSE_BUS2				0xf6 /* bits 47:40 */
> +#define PUNIT_FUSE_BUS1				0xf5 /* bits 55:48 */
> +
>  #define GEN6_GT_CORE_STATUS		0x138060
>  #define   GEN6_CORE_CPD_STATE_MASK	(7<<4)
>  #define   GEN6_RCn_MASK			7
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7d812ba..bb97309 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4356,3 +4356,77 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
>  
>  	return 0;
>  }
> +
> +int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
> +{
> +	u32 cmd, devfn, opcode, port, be, bar;
> +
> +	bar = 0;
> +	be = 0xf;
> +	port = IOSF_PORT_PUNIT;
> +	opcode = PUNIT_OPCODE_REG_READ;
> +	devfn = 16;
> +
> +	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> +		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |

Should be (be << IOSF_BYTE_ENABLES_SHIFT).

> +		(bar << IOSF_BAR_SHIFT);
> +
> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> +	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
> +		DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
> +		return -EAGAIN;
> +	}
> +
> +	I915_WRITE(VLV_IOSF_ADDR, addr);
> +	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
> +
> +	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
> +		     500)) {
> +		DRM_ERROR("timeout waiting for pcode read (%d) to finish\n",
> +			  addr);
> +		return -ETIMEDOUT;
> +	}
> +
> +	*val = I915_READ(VLV_IOSF_DATA);
> +	I915_WRITE(VLV_IOSF_DATA, 0);
> +
> +	return 0;
> +}
> +
> +int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
> +{
> +	u32 cmd, devfn, opcode, port, be, bar;
> +
> +	bar = 0;
> +	be = 0xf;
> +	port = IOSF_PORT_PUNIT;
> +	opcode = PUNIT_OPCODE_REG_WRITE;
> +	devfn = 16;
> +
> +	cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> +		(port << IOSF_PORT_SHIFT) | (be | IOSF_BYTE_ENABLES_SHIFT) |

Ditto.

The obvious copy-pasting makes me note the read/write functions are
roughly the same... would it make sense to have a static common routine
behind the interface functions? Just add opcode parameter, and do *val =
I915_READ(VLV_IOSF_DATA) and I915_WRITE(VLV_IOSF_DATA, *val) depending
on that.

> +		(bar << IOSF_BAR_SHIFT);
> +
> +	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> +	if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
> +		DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
> +		return -EAGAIN;
> +	}
> +
> +	I915_WRITE(VLV_IOSF_ADDR, addr);
> +	I915_WRITE(VLV_IOSF_DATA, val);
> +	I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
> +
> +	if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
> +		     500)) {
> +		DRM_ERROR("timeout waiting for pcode write (%d) to finish\n",
> +			  addr);
> +		return -ETIMEDOUT;
> +	}
> +
> +	I915_WRITE(VLV_IOSF_DATA, 0);
> +
> +	return 0;
> +}
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 06/22] drm/i915: add power context allocation and setup on VLV

[Ville Syrjälä]

On Sat, Feb 02, 2013 at 01:56:10PM +0100, Jesse Barnes wrote:
> The Gunit has a separate reg for this, so allocate some stolen space for
> the power context and initialize the reg.

AFAIK the BIOS is responsible for setting up the PCBR register. The
register can also be locked preventing further updates, so if the BIOS
actually has done what it's supposed to, this code will fail.

So should we just instead read out the PCBR and remove the range from
the stolen mem pool?

> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h        |    2 ++
>  drivers/gpu/drm/i915/i915_gem_stolen.c |   41 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h        |    1 +
>  3 files changed, 44 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f4ae73d..34f01a9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -928,6 +928,8 @@ typedef struct drm_i915_private {
>  	struct drm_mm_node *compressed_fb;
>  	struct drm_mm_node *compressed_llb;
>  
> +	struct drm_mm_node *vlv_pctx;
> +
>  	unsigned long last_gpu_reset;
>  
>  	/* list of fbdev register on this device */
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index f21ae17..ac11a41 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -171,11 +171,49 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev)
>  	dev_priv->cfb_size = 0;
>  }
>  
> +static void i915_setup_pctx(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_mm_node *pctx;
> +	unsigned long pctx_paddr;
> +	int pctx_size = 24*1024;
> +
> +	pctx = drm_mm_search_free(&dev_priv->mm.stolen, pctx_size, 4096, 0);
> +	if (pctx)
> +		pctx = drm_mm_get_block(pctx, pctx_size, 4096);
> +	if (!pctx)
> +		goto err;
> +
> +	pctx_paddr = dev_priv->mm.stolen_base + pctx->start;
> +	if (!pctx_paddr)
> +		goto err_free_pctx;
> +
> +	dev_priv->vlv_pctx = pctx;
> +	I915_WRITE(VLV_PCBR, pctx_paddr);
> +
> +	return;
> +
> +err_free_pctx:
> +	drm_mm_put_block(pctx);
> +err:
> +	DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
> +}
> +
> +static void i915_cleanup_pctx(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	I915_WRITE(VLV_PCBR, 0);
> +	drm_mm_put_block(dev_priv->vlv_pctx);
> +}
> +
>  void i915_gem_cleanup_stolen(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	i915_gem_stolen_cleanup_compression(dev);
> +	if (IS_VALLEYVIEW(dev) && i915_powersave)
> +		i915_cleanup_pctx(dev);
>  	drm_mm_takedown(&dev_priv->mm.stolen);
>  }
>  
> @@ -193,6 +231,9 @@ int i915_gem_init_stolen(struct drm_device *dev)
>  	/* Basic memrange allocator for stolen space */
>  	drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->mm.gtt->stolen_size);
>  
> +	if (IS_VALLEYVIEW(dev) && i915_powersave)
> +		i915_setup_pctx(dev);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 286bab3..c785750 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -561,6 +561,7 @@
>  #define ISR		0x020ac
>  #define VLV_GUNIT_CLOCK_GATE	0x182060
>  #define   GCFG_DIS		(1<<8)
> +#define VLV_PCBR	0x182120
>  #define VLV_IIR_RW	0x182084
>  #define VLV_IER		0x1820a0
>  #define VLV_IIR		0x1820a4
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 06/22] drm/i915: add power context allocation and setup on VLV

[Jesse Barnes]

On Tue, 5 Feb 2013 20:01:15 +0200
Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:

> On Sat, Feb 02, 2013 at 01:56:10PM +0100, Jesse Barnes wrote:
> > The Gunit has a separate reg for this, so allocate some stolen space for
> > the power context and initialize the reg.
> 
> AFAIK the BIOS is responsible for setting up the PCBR register. The
> register can also be locked preventing further updates, so if the BIOS
> actually has done what it's supposed to, this code will fail.
> 
> So should we just instead read out the PCBR and remove the range from
> the stolen mem pool?

At the very least.  I'll have to check with the BIOS folks; I'm pretty
sure on some machines we'll need to do this ourselves.

Jesse
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Re: [PATCH 05/22] drm/i915: enable force wake, disable LLC on VLV

[Jani Nikula]

This has been discussed elsewhere, but I summarize here for
transparency:

This makes some of the display registers take the NEEDS_FORCE_WAKE path
in reg reads and writes, breaking things. Rebased on top of recent
drm-intel-next-queued with Ville's IS_DISPLAYREG nuking commits this
works all right, though.

BR,
Jani.


On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |    4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 13b9b4f..b35b479 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -276,6 +276,8 @@ static const struct intel_device_info intel_valleyview_m_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.is_valleyview = 1,
> +	.has_force_wake = 1,
> +	.has_llc = 0,
>  };
>  
>  static const struct intel_device_info intel_valleyview_d_info = {
> @@ -285,6 +287,8 @@ static const struct intel_device_info intel_valleyview_d_info = {
>  	.has_bsd_ring = 1,
>  	.has_blt_ring = 1,
>  	.is_valleyview = 1,
> +	.has_force_wake = 1,
> +	.has_llc = 0,
>  };
>  
>  static const struct intel_device_info intel_haswell_d_info = {
> -- 
> 1.7.9.5
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 03/22] drm/i915: add UCGCTL4 to display reg check on VLV

[Jani Nikula]

On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Add a few regs needed for various clock gating init purposes and make
> sure they don't fall into the display offset range on VLV.

GEN7_UCGCTL4 needs to be fixed in i915_reg.h after IS_DISPLAYREG
removal.

>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |    1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 69d0637..13b9b4f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1208,6 +1208,7 @@ static bool IS_DISPLAYREG(u32 reg)
>  	case GEN7_HALF_SLICE_CHICKEN1:
>  	case GEN6_MBCTL:
>  	case GEN6_UCGCTL2:
> +	case GEN7_UCGCTL4:
>  		return false;
>  	default:
>  		break;
> -- 
> 1.7.9.5
>
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 06/22] drm/i915: add power context allocation and setup on VLV

[Jani Nikula]

On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> The Gunit has a separate reg for this, so allocate some stolen space for
> the power context and initialize the reg.
>
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.h        |    2 ++
>  drivers/gpu/drm/i915/i915_gem_stolen.c |   41 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h        |    1 +
>  3 files changed, 44 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f4ae73d..34f01a9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -928,6 +928,8 @@ typedef struct drm_i915_private {
>  	struct drm_mm_node *compressed_fb;
>  	struct drm_mm_node *compressed_llb;
>  
> +	struct drm_mm_node *vlv_pctx;
> +
>  	unsigned long last_gpu_reset;
>  
>  	/* list of fbdev register on this device */
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index f21ae17..ac11a41 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -171,11 +171,49 @@ void i915_gem_stolen_cleanup_compression(struct drm_device *dev)
>  	dev_priv->cfb_size = 0;
>  }
>  
> +static void i915_setup_pctx(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_mm_node *pctx;
> +	unsigned long pctx_paddr;
> +	int pctx_size = 24*1024;
> +
> +	pctx = drm_mm_search_free(&dev_priv->mm.stolen, pctx_size, 4096, 0);
> +	if (pctx)
> +		pctx = drm_mm_get_block(pctx, pctx_size, 4096);
> +	if (!pctx)
> +		goto err;
> +
> +	pctx_paddr = dev_priv->mm.stolen_base + pctx->start;
> +	if (!pctx_paddr)
> +		goto err_free_pctx;
> +
> +	dev_priv->vlv_pctx = pctx;
> +	I915_WRITE(VLV_PCBR, pctx_paddr);
> +
> +	return;
> +
> +err_free_pctx:
> +	drm_mm_put_block(pctx);
> +err:
> +	DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
> +}
> +
> +static void i915_cleanup_pctx(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	I915_WRITE(VLV_PCBR, 0);
> +	drm_mm_put_block(dev_priv->vlv_pctx);
> +}
> +
>  void i915_gem_cleanup_stolen(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
>  	i915_gem_stolen_cleanup_compression(dev);
> +	if (IS_VALLEYVIEW(dev) && i915_powersave)
> +		i915_cleanup_pctx(dev);

At least in theory dev_priv->vlv_pctx could be NULL here. Maybe make
dev_priv->vlv_pctx != NULL the condition here?

BR,
Jani.


>  	drm_mm_takedown(&dev_priv->mm.stolen);
>  }
>  
> @@ -193,6 +231,9 @@ int i915_gem_init_stolen(struct drm_device *dev)
>  	/* Basic memrange allocator for stolen space */
>  	drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->mm.gtt->stolen_size);
>  
> +	if (IS_VALLEYVIEW(dev) && i915_powersave)
> +		i915_setup_pctx(dev);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 286bab3..c785750 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -561,6 +561,7 @@
>  #define ISR		0x020ac
>  #define VLV_GUNIT_CLOCK_GATE	0x182060
>  #define   GCFG_DIS		(1<<8)
> +#define VLV_PCBR	0x182120
>  #define VLV_IIR_RW	0x182084
>  #define VLV_IER		0x1820a0
>  #define VLV_IIR		0x1820a4
> -- 
> 1.7.9.5
>
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 03/22] drm/i915: add UCGCTL4 to display reg check on VLV

[Jani Nikula]

On Wed, 06 Feb 2013, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>> Add a few regs needed for various clock gating init purposes and make
>> sure they don't fall into the display offset range on VLV.
>
> GEN7_UCGCTL4 needs to be fixed in i915_reg.h after IS_DISPLAYREG
> removal.

Strike that. The whole patch can be dropped since it's not a display
reg.

>
>>
>> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c |    1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 69d0637..13b9b4f 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1208,6 +1208,7 @@ static bool IS_DISPLAYREG(u32 reg)
>>  	case GEN7_HALF_SLICE_CHICKEN1:
>>  	case GEN6_MBCTL:
>>  	case GEN6_UCGCTL2:
>> +	case GEN7_UCGCTL4:
>>  		return false;
>>  	default:
>>  		break;
>> -- 
>> 1.7.9.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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Re: [PATCH 07/22] drm/i915: new register for IS_DISPLAYREG

[Jani Nikula]

On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> From: Ben Widawsky <ben@bwidawsk.net>
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |    7 +++----
>  drivers/gpu/drm/i915/i915_reg.h |    1 +
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b35b479..28d5992 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1193,10 +1193,6 @@ static bool IS_DISPLAYREG(u32 reg)
>  	    reg <= VLV_ISR)
>  		return false;
>  
> -	if (reg == FORCEWAKE_VLV ||
> -	    reg == FORCEWAKE_ACK_VLV)
> -		return false;
> -
>  	if (reg == GEN6_GDRST)
>  		return false;
>  
> @@ -1213,6 +1209,9 @@ static bool IS_DISPLAYREG(u32 reg)
>  	case GEN6_MBCTL:
>  	case GEN6_UCGCTL2:
>  	case GEN7_UCGCTL4:
> +	case FORCEWAKE_VLV:
> +	case FORCEWAKE_ACK_VLV:
> +	case VLV_GTLC_WAKE_CTRL:

Obviously the IS_DISPLAYREG bits can be dropped now.

BR,
Jani.

>  		return false;
>  	default:
>  		break;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c785750..7e13f34 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4212,6 +4212,7 @@
>  #define  FORCEWAKE_ACK_VLV			0x1300b4
>  #define  FORCEWAKE_ACK_HSW			0x130044
>  #define  FORCEWAKE_ACK				0x130090
> +#define  VLV_GTLC_WAKE_CTRL			0x130090
>  #define  FORCEWAKE_MT				0xa188 /* multi-threaded */
>  #define   FORCEWAKE_KERNEL			0x1
>  #define   FORCEWAKE_USER			0x2
> -- 
> 1.7.9.5
>
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Re: [PATCH 10/22] drm/i915: don't init LVDS on VLV

[Jani Nikula]

On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_lvds.c |    3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 8c61876..feef18c 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -1024,6 +1024,9 @@ static bool intel_lvds_supported(struct drm_device *dev)
>  	if (HAS_PCH_SPLIT(dev))
>  		return true;
>  
> +	if (IS_VALLEYVIEW(dev))
> +		return false;
> +
>  	/* Otherwise LVDS was only attached to mobile products,
>  	 * except for the inglorious 830gm */
>  	return IS_MOBILE(dev) && !IS_I830(dev);
> -- 
> 1.7.9.5
>
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Re: [PATCH 10/22] drm/i915: don't init LVDS on VLV

[Daniel Vetter]

On Wed, Feb 6, 2013 at 2:19 PM, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Up to now all the platform output setup selection has happened in, I'm
not sure whether we should sprinkle this out like that. In any case,
we seem to miss the check for Haswell, too. It probably works out
since the lvds present pin doesn't work, either.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 10/22] drm/i915: don't init LVDS on VLV

[Daniel Vetter]

On Wed, Feb 06, 2013 at 03:19:03PM +0200, Jani Nikula wrote:
> On Sat, 02 Feb 2013, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Queued for -next, thanks for the patch. And Paulo promised to fix up the
confusion around LVDS presence checks.
-Daniel
> 
> > ---
> >  drivers/gpu/drm/i915/intel_lvds.c |    3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> > index 8c61876..feef18c 100644
> > --- a/drivers/gpu/drm/i915/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/intel_lvds.c
> > @@ -1024,6 +1024,9 @@ static bool intel_lvds_supported(struct drm_device *dev)
> >  	if (HAS_PCH_SPLIT(dev))
> >  		return true;
> >  
> > +	if (IS_VALLEYVIEW(dev))
> > +		return false;
> > +
> >  	/* Otherwise LVDS was only attached to mobile products,
> >  	 * except for the inglorious 830gm */
> >  	return IS_MOBILE(dev) && !IS_I830(dev);
> > -- 
> > 1.7.9.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch