From: Karthik B S <karthik.b.s@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 10/11] drm/i915: Implement async flip for ilk/snb
Date: Mon, 18 Jan 2021 16:38:41 +0530 [thread overview]
Message-ID: <8af0e192-f2c8-2f09-46a5-48afd62d3f92@intel.com> (raw)
In-Reply-To: <20210111163711.12913-11-ville.syrjala@linux.intel.com>
On 1/11/2021 10:07 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add support for async flips on ivb/hsw. Again no need for any
> workarounds and just have to deal with the interrupt bits being
> shuffled around a bit.
>
> Cc: Karthik B S <karthik.b.s@intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Looks good to me.
Reviewed-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 24 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
> drivers/gpu/drm/i915/i915_irq.c | 5 ++++
> 3 files changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index f75be2292caa..488ed01bb342 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -559,6 +559,26 @@ ivb_primary_disable_flip_done(struct intel_plane *plane)
> spin_unlock_irq(&i915->irq_lock);
> }
>
> +static void
> +ilk_primary_enable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + spin_lock_irq(&i915->irq_lock);
> + ilk_enable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> +static void
> +ilk_primary_disable_flip_done(struct intel_plane *plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +
> + spin_lock_irq(&i915->irq_lock);
> + ilk_disable_display_irq(i915, DE_PLANE_FLIP_DONE(plane->i9xx_plane));
> + spin_unlock_irq(&i915->irq_lock);
> +}
> +
> static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> enum pipe *pipe)
> {
> @@ -781,6 +801,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->async_flip = g4x_primary_async_flip;
> plane->enable_flip_done = ivb_primary_enable_flip_done;
> plane->disable_flip_done = ivb_primary_disable_flip_done;
> + } else if (IS_GEN_RANGE(dev_priv, 5, 6)) {
> + plane->async_flip = g4x_primary_async_flip;
> + plane->enable_flip_done = ilk_primary_enable_flip_done;
> + plane->disable_flip_done = ilk_primary_disable_flip_done;
> }
>
> if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 25da68f12df1..67add1166d5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2123,7 +2123,8 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
> static bool has_async_flips(struct drm_i915_private *i915)
> {
> return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) ||
> - IS_HASWELL(i915) || IS_IVYBRIDGE(i915);
> + IS_HASWELL(i915) || IS_IVYBRIDGE(i915) ||
> + IS_GEN_RANGE(i915, 5, 6);
> }
>
> static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3518f6f23896..9e04c6b28c12 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2029,6 +2029,9 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
> if (de_iir & DE_PIPE_VBLANK(pipe))
> intel_handle_vblank(dev_priv, pipe);
>
> + if (de_iir & DE_PLANE_FLIP_DONE(pipe))
> + flip_done_handler(dev_priv, pipe);
> +
> if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
> intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
>
> @@ -3577,6 +3580,8 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
> DE_PIPEA_CRC_DONE | DE_POISON);
> extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |
> DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
> + DE_PLANE_FLIP_DONE(PLANE_A) |
> + DE_PLANE_FLIP_DONE(PLANE_B) |
> DE_DP_A_HOTPLUG);
> }
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-01-18 11:08 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-11 16:37 [Intel-gfx] [PATCH v2 00/11] drm/i915: Async flips for all ilk+ platforms Ville Syrjala
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 01/11] drm/i915: WARN if plane src coords are too big Ville Syrjala
2021-01-27 11:11 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 02/11] drm/i915: Limit plane stride to below TILEOFF.x limit Ville Syrjala
2021-01-28 9:41 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 03/11] drm/i915: Drop redundant parens Ville Syrjala
2021-01-15 10:19 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 04/11] drm/i915: Generalize the async flip capability check Ville Syrjala
2021-01-15 10:23 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 05/11] drm/i915: Add plane vfuncs to enable/disable flip_done interrupt Ville Syrjala
2021-01-15 11:38 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 06/11] drm/i915: Move the async_flip bit setup into the .async_flip() hook Ville Syrjala
2021-01-15 11:40 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 07/11] drm/i915: Reuse the async_flip() hook for the async flip disable w/a Ville Syrjala
2021-01-18 9:27 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 08/11] drm/i915: Implement async flips for bdw Ville Syrjala
2021-01-18 9:44 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 09/11] drm/i915: Implement async flip for ivb/hsw Ville Syrjala
2021-01-18 10:45 ` Karthik B S
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 10/11] drm/i915: Implement async flip for ilk/snb Ville Syrjala
2021-01-18 11:08 ` Karthik B S [this message]
2021-01-11 16:37 ` [Intel-gfx] [PATCH v2 11/11] drm/i915: Implement async flips for vlv/chv Ville Syrjala
2021-01-27 8:09 ` Karthik B S
2021-01-11 17:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Async flips for all ilk+ platforms (rev2) Patchwork
2021-01-11 18:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8af0e192-f2c8-2f09-46a5-48afd62d3f92@intel.com \
--to=karthik.b.s@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=ville.syrjala@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).