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Wed, 21 Jul 2021 19:05:21 +0100 To: Vinay Belgaumkar , intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org References: <20210721161120.24610-1-vinay.belgaumkar@intel.com> <20210721161120.24610-10-vinay.belgaumkar@intel.com> From: Michal Wajdeczko Message-ID: <91447d98-cf2d-cf60-e1c8-1bb13b4ae12d@intel.com> Date: Wed, 21 Jul 2021 20:05:20 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Firefox/78.0 Thunderbird/78.12.0 MIME-Version: 1.0 In-Reply-To: <20210721161120.24610-10-vinay.belgaumkar@intel.com> Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH 09/14] drm/i915/guc/slpc: Add debugfs for SLPC info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 21.07.2021 18:11, Vinay Belgaumkar wrote: > This prints out relevant SLPC info from the SLPC shared structure. > > We will send a h2g message which forces SLPC to update the > shared data structure with latest information before reading it. > > v2: Address review comments (Michal W) > > Signed-off-by: Vinay Belgaumkar > Signed-off-by: Sundaresan Sujaritha > --- > .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c | 23 +++++++++++ > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 40 +++++++++++++++++++ > drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h | 4 +- > 3 files changed, 66 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c > index 72ddfff42f7d..46b22187927b 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.c > @@ -12,6 +12,7 @@ > #include "gt/uc/intel_guc_ct.h" > #include "gt/uc/intel_guc_ads.h" > #include "gt/uc/intel_guc_submission.h" > +#include "gt/uc/intel_guc_slpc.h" > > static int guc_info_show(struct seq_file *m, void *data) > { > @@ -50,11 +51,33 @@ static int guc_registered_contexts_show(struct seq_file *m, void *data) > } > DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_registered_contexts); > > +static int guc_slpc_info_show(struct seq_file *m, void *unused) > +{ > + struct intel_guc *guc = m->private; > + struct intel_guc_slpc *slpc = &guc->slpc; > + struct drm_printer p = drm_seq_file_printer(m); > + > + if (!intel_guc_slpc_is_used(guc)) > + return -ENODEV; > + > + return intel_guc_slpc_info(slpc, &p); > +} > +DEFINE_GT_DEBUGFS_ATTRIBUTE(guc_slpc_info); > + > +bool intel_eval_slpc_support(void *data) > +{ > + struct intel_guc *guc; > + > + guc = (struct intel_guc *)data; struct intel_guc *guc = (struct intel_guc *)data; > + return intel_guc_slpc_is_used(guc); > +} > + > void intel_guc_debugfs_register(struct intel_guc *guc, struct dentry *root) > { > static const struct debugfs_gt_file files[] = { > { "guc_info", &guc_info_fops, NULL }, > { "guc_registered_contexts", &guc_registered_contexts_fops, NULL }, > + { "guc_slpc_info", &guc_slpc_info_fops, &intel_eval_slpc_support}, > }; > > if (!intel_guc_is_supported(guc)) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > index c1cf8d46e360..73379985c105 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c > @@ -430,6 +430,46 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) > return 0; > } > > +int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p) > +{ > + struct drm_i915_private *i915 = guc_to_gt(slpc_to_guc(slpc))->i915; > + struct slpc_shared_data *data; > + struct slpc_task_state_data *slpc_tasks; > + intel_wakeref_t wakeref; > + int ret = 0; > + > + with_intel_runtime_pm(&i915->runtime_pm, wakeref) { > + if (slpc_query_task_state(slpc)) > + return -EIO; not sure if you can return directly from "with_rpm" > + > + slpc_tasks = &data->task_state_data; > + > + drm_printf(p, "SLPC state: %s\n", slpc_state_string(slpc)); > + drm_printf(p, "\tgtperf task active: %s\n", > + yesno(slpc_tasks->status & SLPC_GTPERF_TASK_ACTIVE)); > + drm_printf(p, "\tdcc task active: %s\n", > + yesno(slpc_tasks->status & SLPC_DCC_TASK_ACTIVE)); > + drm_printf(p, "\tin dcc: %s\n", > + yesno(slpc_tasks->status & SLPC_IN_DCC)); > + drm_printf(p, "\tfreq switch active: %s\n", > + yesno(slpc_tasks->status & SLPC_FREQ_SWITCH_ACTIVE)); > + drm_printf(p, "\tibc enabled: %s\n", > + yesno(slpc_tasks->status & SLPC_IBC_ENABLED)); > + drm_printf(p, "\tibc active: %s\n", > + yesno(slpc_tasks->status & SLPC_IBC_ACTIVE)); > + drm_printf(p, "\tpg1 enabled: %s\n", > + yesno(slpc_tasks->status & SLPC_PG1_ENABLED)); > + drm_printf(p, "\tpg1 active: %s\n", > + yesno(slpc_tasks->status & SLPC_PG1_ACTIVE)); > + drm_printf(p, "\tmax freq: %dMHz\n", > + slpc_decode_max_freq(slpc)); > + drm_printf(p, "\tmin freq: %dMHz\n", > + slpc_decode_min_freq(slpc)); not sure what they are: DCC ? IBC ? PG1 ? and make sure to use %u for unsigned Michal > + } > + > + return ret; > +} > + > void intel_guc_slpc_fini(struct intel_guc_slpc *slpc) > { > if (!slpc->vma) > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h > index 627c71a95777..852c6316aa47 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h > @@ -10,6 +10,8 @@ > #include "intel_guc_slpc_types.h" > #include "abi/guc_actions_slpc_abi.h" > > +struct drm_printer; > + > static inline bool intel_guc_slpc_is_supported(struct intel_guc *guc) > { > return guc->slpc_supported; > @@ -26,7 +28,6 @@ static inline bool intel_guc_slpc_is_used(struct intel_guc *guc) > } > > void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc); > - > int intel_guc_slpc_init(struct intel_guc_slpc *slpc); > int intel_guc_slpc_enable(struct intel_guc_slpc *slpc); > void intel_guc_slpc_fini(struct intel_guc_slpc *slpc); > @@ -34,5 +35,6 @@ int intel_guc_slpc_set_max_freq(struct intel_guc_slpc *slpc, u32 val); > int intel_guc_slpc_set_min_freq(struct intel_guc_slpc *slpc, u32 val); > int intel_guc_slpc_get_max_freq(struct intel_guc_slpc *slpc, u32 *val); > int intel_guc_slpc_get_min_freq(struct intel_guc_slpc *slpc, u32 *val); > +int intel_guc_slpc_info(struct intel_guc_slpc *slpc, struct drm_printer *p); > > #endif > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx