messages from 2013-01-23 16:55:15 to 2013-01-29 08:30:48 UTC [more...]
[PATCH 0/4] gtt abstractions
2013-01-29 8:30 UTC (23+ messages)
` [PATCH 1/4] drm/i915: vfuncs for gtt_clear_range/insert_entries
` [PATCH 2/4] drm/i915: vfuncs for ppgtt
` [PATCH 3/4] drm/i915: pte_encode is gen6+
` [PATCH 4/4] drm/i915: extract hw ppgtt setup/cleanup code
` [PATCH 1/6] drm/i915: vfuncs for gtt_clear_range/insert_entries
` [PATCH 2/6] drm/i915: vfuncs for ppgtt
` [PATCH 3/6] drm/i915: pte_encode is gen6+
` [PATCH 4/6] drm/i915: extract hw ppgtt setup/cleanup code
` [PATCH 5/6] drm/i915: Add probe and remove to the gtt ops
` [PATCH 6/6] drm/i915: Resume dissecting intel_gtt
intel-gpu-tools patches for read/write MMIO
2013-01-29 8:16 UTC
[RFC PATCH 1/3] PM: Introduce suspend state PM_SUSPEND_FREEZE
2013-01-29 2:05 UTC (10+ messages)
` [RFC PATCH 2/3] ACPI: enable ACPI SCI during suspend
` [RFC PATCH 3/3] i915: ignore lid open event when resuming
` [Intel-gfx] "
[PATCH 1/2] drm/i915: Error state should print /sys/kernel/debug
2013-01-29 0:14 UTC (3+ messages)
` [PATCH 2/2] drm/i915: Adding a warning to FBC description
[PATCH 0/4] disable more register safe/restore code for kms
2013-01-28 21:54 UTC (9+ messages)
` [PATCH 1/4] drm/i915: move modeset checks out of save/restore_modeset_reg
` [PATCH 2/4] drm/i915: extract ums suspend/resume into i915_ums.c
` [PATCH 3/4] drm/i915: dont save/restore VGA state for kms
` [PATCH 4/4] drm/i915: move DP save/restore into i915_ums.c
[PATCH 0/5] [REPOST] GTT cleanups, rebased
2013-01-28 21:08 UTC (14+ messages)
` [PATCH 1/5] drm/i915: trivial: kill-agp collateral cleanups
` [PATCH 2/5] drm/i915: Reclaim GTT space for failed PPGTT
` [PATCH 3/5] drm/i915: Extract gen6 aliasing ppgtt code
` [PATCH 4/5] drm/i915: Aliased PPGTT size abstraction
` [PATCH 4/5 v2] "
` [PATCH 5/5] drm/i915: Dynamically calculate dclv
[PATCH 0/7] Unclaimed register reporting V2
2013-01-28 20:17 UTC (14+ messages)
` [PATCH 1/7] drm/i915: create macros for the "unclaimed register" checks
` [PATCH 2/7] drm/i915: use FPGA_DBG "
` [PATCH 3/7] drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init
` [PATCH 4/7] drm/i915: check for unclaimed registers on I915_READ too
` [PATCH 5/7] drm/i915: WARN on unclaimed registers
` [PATCH 6/7] drm/i915: only check for unclaimed registers if drm_debug
` [PATCH 7/7] drm/i915: print Gen 7 error interrupts
Bug Team Status
2013-01-28 16:36 UTC
[PATCH] drm/i915: Implement WaVSRefCountFullforceMissDisable
2013-01-28 15:51 UTC (3+ messages)
Adding a i915 quirk (here: pipe A force quirk for testing purposes)?
2013-01-28 15:20 UTC (5+ messages)
` [Intel-gfx] "
[PATCH] drm/i915: Only run idle processing from i915_gem_retire_requests_worker
2013-01-28 11:02 UTC (2+ messages)
[PATCH 0/7] Unclaimed registers and power well V2
2013-01-27 23:27 UTC (12+ messages)
` [PATCH 1/7] drm/i915: don't send DP idle pattern before normal pattern on HSW
` [PATCH 2/7] drm/i915: fix intel_init_power_wells
` [PATCH 3/7] drm/i915: dynamic Haswell display power well support
` [PATCH 4/7] drm/i915: only disable enabled planes on intel_fb_restore_mode
` [PATCH 5/7] drm/i915: check the power down well on assert_pipe()
` [PATCH 6/7] drm/i915: turn on the power well before suspending
` [PATCH 7/7] drm/i915: set TRANSCODER_EDP even earlier
[PATCH 0/9] drm/915: Get rid of IS_DISPLAYREG(), continued
2013-01-26 16:43 UTC (11+ messages)
` [PATCH v2 1/9] drm/i915: PLL registers need an offset on VLV
` [PATCH 2/9] drm/i915: Always use adpa_reg
` [PATCH 3/9] drm/i915: VLV doesn't have SDVO
` [PATCH v2 4/9] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLV
` [PATCH 5/9] drm/i915: Include display_mmio_offset in sequencer index/data registers
` [PATCH 6/9] drm/i915: Introduce i915_vgacntrl_reg()
` [PATCH 7/9] drm/i915: Kill IS_DISPLAYREG()
` [PATCH 8/9] drm/i915: Set the SR01 "screen off" bit in i915_redisable_vga() too
` [PATCH 9/9] drm/i915: Don't touch VGA0/VGA1/VGA_PD on ILK+
[PATCH 00/33] drm/915: Get rid of IS_DISPLAYREG()
2013-01-26 16:41 UTC (67+ messages)
` [PATCH 01/33] drm/i915: Convert intel_hdmi to enum port
` [PATCH 02/33] drm/i915: Convert intel_dp "
` [PATCH 03/33] drm/i915: Add display_display_mmio_offset to intel_device_info
` [PATCH 04/33] drm/i915: AUD_VID_DID needs an offset on VLV
` [PATCH 05/33] drm/i915: Per-pipe PP registers are for VLV only
` [PATCH 06/33] drm/i915: VLV_VIDEO_DIP_CTL is "
` [PATCH 07/33] drm/i915: PIPE M/N registers need an offset on VLV
` [PATCH 08/33] drm/i915: SWF screatch "
` [PATCH 09/33] drm/i915: VGACNTRL needs "
` [PATCH 10/33] drm/i915: Primary plane registers need "
` [PATCH 11/33] drm/i915: Pipe "
` [PATCH 12/33] drm/i915: Cursor "
` [PATCH 13/33] drm/i915: VLV_DDL is VLV only and needs an offset
` [PATCH 14/33] drm/i915: DSPFW registers need an offset on VLV
` [PATCH 15/33] drm/i915: DSPARB register needs "
` [PATCH 16/33] drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset
` [PATCH 17/33] drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_init_{sdvo, hdmi, dp} on VLV
` [PATCH 18/33] drm/i915: Panel fitter registers need an offset "
` [PATCH 19/33] drm/i915: PORT_HOTPLUG "
` [PATCH 20/33] drm/i915: VLV_ADPA must be used in VLV code
` [PATCH 21/33] drm/i915: Pipe timing registers need an offset on VLV
` [PATCH 22/33] drm/i915: Pipe palette "
` [PATCH 23/33] drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset
` [PATCH 24/33] drm/i915: VLV doesn't seem to have VGA0/VGA1/VGA_PD registers
` [PATCH 25/33] drm/i915: PLL and clock gating registers need an offset on VLV
` [PATCH 26/33] drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable
` [PATCH 27/33] drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers
` [PATCH 28/33] drm/i915: DPIO registers are VLV only and need an offset
` [PATCH 29/33] drm/i915: VGA registers need an offset on VLV
` [PATCH 30/33] drm/i915: GPIO/GMBUS "
` [PATCH 31/33] drm/i915: Set display_mmio_offset for VLV
` [PATCH 32/33] drm/i915: Kill IS_DISPLAYREG()
` [PATCH 33/33] drm/i915: Kill VLV specific interrupts registers
Question about driver capatibilities - triple monitor?
2013-01-25 21:56 UTC (7+ messages)
` Monitors on thunderbolt? (Was: Question about driver capatibilities - triple monitor?)
[PATCH V3 3/3] i915: introduce modeset_on_resume
2013-01-25 18:27 UTC (3+ messages)
[PATCH 00/10] Haswell unclaimed register fixes and power well enabling
2013-01-25 16:16 UTC (24+ messages)
` [PATCH 01/10] drm/i915: don't save/restore DSPARB on gen5+
` [PATCH 02/10] drm/i915: don't read DP_TP_STATUS(PORT_A)
` [PATCH 03/10] drm/i915: fix intel_init_power_wells
` [PATCH 04/10] drm/i915: dynamic Haswell display power well support
` [PATCH 06/10] drm/i915: check the power down well on assert_pipe()
` [PATCH 07/10] drm/i915: turn on the power well before suspending
` [PATCH 08/10] drm/i915: set TRANSCODER_EDP even earlier
` [PATCH 09/10] drm/i915: print IVB/HSW display error interrupts
[PULL] drm-intel-fixes for 3.8
2013-01-25 10:33 UTC
external screen goes black
2013-01-24 20:43 UTC (7+ messages)
circular locking warning during suspend
2013-01-24 19:58 UTC (2+ messages)
[PATCH 0/2] fbcon+i915 locking fixes
2013-01-24 9:55 UTC (3+ messages)
` [PATCH 2/2] drm/i915: fixup per-crtc locking in intel_release_load_detect_pipe
[QA 01/24] Testing report for `drm-intel-testing` (was: Updated -next)
2013-01-24 5:35 UTC
[PATCH] drm/i915: dump UTS_RELEASE into the error_state
2013-01-23 16:57 UTC (5+ messages)
page: next (older) | prev (newer) | latest
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).