messages from 2020-06-04 10:28:48 to 2020-06-05 18:45:43 UTC [more...]
[Intel-gfx] [PATCH v2 1/1] drm/mm: add ig_frag selftest
2020-06-05 8:39 UTC (4+ messages)
[Intel-gfx] [PATCH] pinctrl: baytrail: Fix pin being driven low for a while on gpiod_get(..., GPIOD_OUT_HIGH)
2020-06-05 18:45 UTC (6+ messages)
[Intel-gfx] [PATCH] drm/i915/gt: Include the engine's fw-domains in the debug info
2020-06-05 17:58 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [CI] drm/i915: Discard a misplaced GGTT vma
2020-06-05 17:26 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Discard a misplaced GGTT vma (rev2)
[Intel-gfx] [PATCH] drm/i915: Fix comments mentioning typo in IS_ENABLED()
2020-06-05 17:15 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse
2020-06-05 16:58 UTC (14+ messages)
` [Intel-gfx] [PATCH 2/5] drm/i915/gem: Separate reloc validation into an earlier step
` [Intel-gfx] [PATCH v2] "
` [Intel-gfx] [PATCH 3/5] drm/i915/gem: Lift GPU relocation allocation
` [Intel-gfx] [PATCH 4/5] drm/i915/gem: Build the reloc request first
` [Intel-gfx] [PATCH 5/5] drm/i915/gem: Add all GPU reloc awaits/signals en masse
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/5] drm/i915: Add list_for_each_entry_safe_continue_reverse (rev2)
[Intel-gfx] [PATCH v2] drm/i915/psr: Program default IO buffer Wake and Fast Wake
2020-06-05 15:47 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Program default IO buffer Wake and Fast Wake (rev2)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 01/10] drm/i915/gt: Set timeslicing priority from queue
2020-06-05 15:43 UTC (22+ messages)
` [Intel-gfx] [PATCH 02/10] drm/i915/gt: Always check to enable timeslicing if not submitting
` [Intel-gfx] [PATCH 03/10] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq"
` [Intel-gfx] [PATCH 04/10] drm/i915/gt: Couple tasklet scheduling for all CS interrupts
` [Intel-gfx] [PATCH 05/10] drm/i915/gt: Support creation of 'internal' rings
` [Intel-gfx] [PATCH 06/10] drm/i915/gt: Use client timeline address for seqno writes
` [Intel-gfx] [PATCH 07/10] drm/i915/gt: Infrastructure for ring scheduling
` [Intel-gfx] [PATCH 08/10] drm/i915/gt: Enable busy-stats for ring-scheduler
` [Intel-gfx] [PATCH 09/10] drm/i915/gt: Implement ring scheduler for gen6/7
` [Intel-gfx] [PATCH 10/10] drm/i915/gt: Enable ring scheduling "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915/gt: Set timeslicing priority from queue
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 1/2] drm/i915: Discard a misplaced GGTT vma
2020-06-05 15:27 UTC (7+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915/gem: Avoid kmalloc under i915->mm_lock
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Discard a misplaced GGTT vma
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 1/3] drm/i915/dp_mst: Fix disabling MST on a port
2020-06-05 15:03 UTC (14+ messages)
` [Intel-gfx] [PATCH v2 "
` [Intel-gfx] [PATCH v3 "
` [Intel-gfx] [PATCH RESEND "
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev4)
` [Intel-gfx] ✓ Fi.CI.IGT: "
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev5)
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RESEND,v3,1/3] drm/i915/dp_mst: Fix disabling MST on a port (rev6)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
` [Intel-gfx] ✓ Fi.CI.IGT: success "
[Intel-gfx] [PATCH 03/18] dma-fence: basic lockdep annotations
2020-06-05 14:30 UTC (3+ messages)
` [Intel-gfx] [PATCH] "
[Intel-gfx] [PATCH 00/18] dma-fence lockdep annotations, round 2
2020-06-05 14:15 UTC (7+ messages)
` [Intel-gfx] [PATCH 13/18] drm/amdgpu/dc: Stop dma_resv_lock inversion in commit_tail
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence lockdep annotations, round 2 (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH] drm/i915/psr: Program default IO buffer Wake and Fast Wake
2020-06-05 14:02 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v3 00/15] Remaining RKL patches
2020-06-05 11:52 UTC (26+ messages)
` [Intel-gfx] [PATCH v3 01/15] drm/i915/rkl: Set transcoder mask properly
` [Intel-gfx] [PATCH v3 02/15] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
` [Intel-gfx] [PATCH v3 03/15] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2}
` [Intel-gfx] [PATCH v3 05/15] drm/i915/rkl: Setup ports/phys
` [Intel-gfx] [PATCH v3 07/15] drm/i915/rkl: Update TGP's pin mapping when paired with RKL
` [Intel-gfx] [PATCH v3 09/15] drm/i915/rkl: Don't try to access transcoder D
` [Intel-gfx] [PATCH v3 10/15] drm/i915/rkl: Don't try to read out DSI transcoders
` [Intel-gfx] [PATCH v3 13/15] drm/i915/rkl: Handle HTI
` [Intel-gfx] [PATCH v3 14/15] drm/i915/rkl: Disable PSR2
` [Intel-gfx] ✓ Fi.CI.IGT: success for Remaining RKL patches
[Intel-gfx] [PATCH 1/2] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
2020-06-05 5:47 UTC (4+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915/rkl: RKL has no MBUS_ABOX_CTL{1, 2}
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI] drm/i915/gem: Async GPU relocations only
2020-06-05 4:11 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915: Add psr_safest_params
2020-06-05 2:40 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
[Intel-gfx] [PATCH v2] drm/i915/gt: Initialize reserved and unspecified MOCS indices
2020-06-04 23:10 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/dp: DP PHY compliance for JSL
2020-06-04 21:03 UTC (5+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [PATCH] drm/i915/tgl: Add HBR and HBR2+ voltage swing table
2020-06-04 20:43 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
[Intel-gfx] [PATCH] drm/i915/dp: Reset link params on connector disconnect
2020-06-04 19:49 UTC (12+ messages)
[Intel-gfx] [PATCH 00/59] devm_drm_dev_alloc, v2
2020-06-04 19:36 UTC (14+ messages)
` [Intel-gfx] [PATCH 53/59] drm/arc: Move to drm/tiny
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for devm_drm_dev_alloc, v2 (rev2)
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for devm_drm_dev_alloc, v2 (rev3)
[Intel-gfx] [PATCH 3/3] drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses
2020-06-04 18:54 UTC (6+ messages)
` [Intel-gfx] [PATCH v2 "
` [Intel-gfx] [PATCH v3 "
[Intel-gfx] [CI] drm/i915/gt: Track if an engine requires forcewake w/a
2020-06-04 18:28 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Track if an engine requires forcewake w/a (rev2)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v2] drm/i915: Fix wrong CDCLK adjustment changes
2020-06-04 18:16 UTC (2+ messages)
[Intel-gfx] [CI] drm/i915: Trim set_timer_ms() intervals
2020-06-04 17:44 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/gt: Extract busy-stats for use in other schedulers
2020-06-04 17:42 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH] drm/i915/gt: Trace HWSP cachelines
2020-06-04 17:00 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI] drm/i915/params: switch to device specific parameters
2020-06-04 15:49 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
[Intel-gfx] [CI] drm/i915/gt: Track if an engine requires forcewake w/a
2020-06-04 15:24 UTC
[Intel-gfx] [PULL] drm-intel-next-fixes
2020-06-04 15:04 UTC
[Intel-gfx] [PATCH] drm/i915/selftests: Exercise all copy engines with the blt routines
2020-06-04 15:03 UTC (8+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise all copy engines with the blt routines (rev2)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser
2020-06-04 13:44 UTC (29+ messages)
` [Intel-gfx] [PATCH 02/22] drm/i915: Trim set_timer_ms() intervals
` [Intel-gfx] [PATCH 03/22] drm/i915/gt: Set timeslicing priority from queue
` [Intel-gfx] [PATCH 04/22] drm/i915/gt: Always check to enable timeslicing if not submitting
` [Intel-gfx] [PATCH 05/22] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq"
` [Intel-gfx] [PATCH 06/22] drm/i915/gt: Couple tasklet scheduling for all CS interrupts
` [Intel-gfx] [PATCH 07/22] drm/i915/gt: Support creation of 'internal' rings
` [Intel-gfx] [PATCH 08/22] drm/i915/gt: Use client timeline address for seqno writes
` [Intel-gfx] [PATCH 09/22] drm/i915/gt: Infrastructure for ring scheduling
` [Intel-gfx] [PATCH 10/22] drm/i915/gt: Enable busy-stats for ring-scheduler
` [Intel-gfx] [PATCH 11/22] drm/i915/gt: Track if an engine requires forcewake w/a
` [Intel-gfx] [PATCH 12/22] drm/i915/gt: Implement ring scheduler for gen6/7
` [Intel-gfx] [PATCH 13/22] drm/i915/gt: Enable ring scheduling "
` [Intel-gfx] [PATCH 14/22] drm/i915/gem: Async GPU relocations only
` [Intel-gfx] [PATCH 15/22] drm/i915: Add list_for_each_entry_safe_continue_reverse
` [Intel-gfx] [PATCH 16/22] drm/i915/gem: Separate reloc validation into an earlier step
` [Intel-gfx] [PATCH 17/22] drm/i915/gem: Lift GPU relocation allocation
` [Intel-gfx] [PATCH 18/22] drm/i915/gem: Build the reloc request first
` [Intel-gfx] [PATCH 19/22] drm/i915/gem: Add all GPU reloc awaits/signals en masse
` [Intel-gfx] [PATCH 20/22] dma-buf: Proxy fence, an unsignaled fence placeholder
` [Intel-gfx] [PATCH 21/22] drm/i915: Unpeel awaits on a proxy fence
` [Intel-gfx] [PATCH 22/22] drm/i915/gem: Make relocations atomic within execbuf
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH v2] drm/i915/tgl: Implement WA_16011163337
2020-06-04 13:25 UTC (2+ messages)
[Intel-gfx] [PATCH 00/13] sysctl: spring cleaning
2020-06-04 13:16 UTC (4+ messages)
` [Intel-gfx] [PATCH 13/13] fs: move binfmt_misc sysctl to its own file
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for sysctl: spring cleaning (rev2)
[Intel-gfx] [drm:gen8_de_irq_handler [i915]] *ERROR* Fault errors on pipe B: 0x00000080
2020-06-04 10:11 UTC (4+ messages)
[Intel-gfx] [PATCH 01/24] Revert "drm/i915/gem: Drop relocation slowpath"
2020-06-04 11:25 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/24] "
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