messages from 2020-09-29 00:29:40 to 2020-09-30 20:10:34 UTC [more...]
[Intel-gfx] remove alloc_vm_area v3
2020-09-30 20:10 UTC (12+ messages)
` [Intel-gfx] [PATCH 01/10] mm: update the documentation for vfree
` [Intel-gfx] [PATCH 02/10] mm: add a VM_MAP_PUT_PAGES flag for vmap
` [Intel-gfx] [PATCH 03/10] mm: add a vmap_pfn function
` [Intel-gfx] [PATCH 04/10] mm: allow a NULL fn callback in apply_to_page_range
` [Intel-gfx] [PATCH 05/10] zsmalloc: switch from alloc_vm_area to get_vm_area
` [Intel-gfx] [PATCH 06/10] drm/i915: use vmap in shmem_pin_map
` [Intel-gfx] [PATCH 07/10] drm/i915: use vmap in i915_gem_object_map
` [Intel-gfx] [PATCH 08/10] xen/xenbus: use apply_to_page_range directly in xenbus_map_ring_pv
` [Intel-gfx] [PATCH 09/10] x86/xen: open code alloc_vm_area in arch_gnttab_valloc
` [Intel-gfx] [PATCH 10/10] mm: remove alloc_vm_area
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/10] mm: update the documentation for vfree
[Intel-gfx] [PATCH] drm/i915: Skip over MI_NOOP when parsing
2020-09-30 19:53 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
[Intel-gfx] [PATCH] drm/i915: don't conflate is_dgfx with fake lmem
2020-09-30 19:07 UTC (5+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v2 00/11] drm/i915: Plumb crtc state to link training code
2020-09-30 18:50 UTC (32+ messages)
` [Intel-gfx] [PATCH v2 01/11] drm/i915: s/pre_empemph/preemph/
` [Intel-gfx] [PATCH v2 02/11] drm/i915: s/old_crtc_state/crtc_state/
` [Intel-gfx] [PATCH v2 03/11] drm/i915: Make intel_dp_process_phy_request() static
` [Intel-gfx] [PATCH v2 04/11] drm/i915: Shove the PHY test into the hotplug work
` [Intel-gfx] [PATCH v3 "
` [Intel-gfx] [PATCH v2 05/11] drm/i915: Split ICL combo PHY buf trans per output type
` [Intel-gfx] [PATCH v2 06/11] drm/i915: Split ICL MG "
` [Intel-gfx] [PATCH v2 07/11] drm/i915: Split EHL combo "
` [Intel-gfx] [PATCH v2 08/11] drm/i915: Split TGL "
` [Intel-gfx] [PATCH v2 09/11] drm/i915: Split TGL DKL "
` [Intel-gfx] [PATCH v2 10/11] drm/i915: Plumb crtc_state to link training
` [Intel-gfx] [PATCH v2 11/11] drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl, status}
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plumb crtc state to link training code (rev4)
` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plumb crtc state to link training code (rev3)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Plumb crtc state to link training code (rev4)
[Intel-gfx] remove alloc_vm_area v2
2020-09-30 18:37 UTC (8+ messages)
[Intel-gfx] [PATCH v2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
2020-09-30 18:20 UTC (19+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v6 00/24] Introduce DG1
2020-09-30 17:33 UTC (38+ messages)
` [Intel-gfx] [PATCH v6 01/24] drm/i915/dg1: add more PCI ids
` [Intel-gfx] [PATCH v6 02/24] drm/i915/dg1: Initialize RAWCLK properly
` [Intel-gfx] [PATCH v6 03/24] drm/i915/dg1: Define MOCS table for DG1
` [Intel-gfx] [PATCH v6 04/24] drm/i915/dg1: Add DG1 power wells
` [Intel-gfx] [PATCH v6 05/24] drm/i915/dg1: Increase mmio size to 4MB
` [Intel-gfx] [PATCH v6 06/24] drm/i915/dg1: Wait for pcode/uncore handshake at startup
` [Intel-gfx] [PATCH v6 07/24] drm/i915/dg1: Add DPLL macros for DG1
` [Intel-gfx] [PATCH v6 08/24] drm/i915/dg1: Add and setup DPLLs "
` [Intel-gfx] [PATCH v6 09/24] drm/i915/dg1: Enable DPLL "
` [Intel-gfx] [PATCH v6 10/24] drm/i915/dg1: add hpd interrupt handling
` [Intel-gfx] [PATCH v6 11/24] drm/i915/dg1: invert HPD pins
` [Intel-gfx] [PATCH v6 12/24] drm/i915/dg1: gmbus pin mapping
` [Intel-gfx] [PATCH v6 13/24] drm/i915/dg1: Enable first 2 ports for DG1
` [Intel-gfx] [PATCH v6 14/24] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
` [Intel-gfx] [PATCH v6 15/24] drm/i915/dg1: Update comp master/slave relationships for PHYs
` [Intel-gfx] [PATCH v6 16/24] drm/i915/dg1: Update voltage swing tables for DP
` [Intel-gfx] [PATCH v6 17/24] drm/i915/dg1: provide port/phy mapping for vbt
` [Intel-gfx] [PATCH v6 18/24] drm/i915/dg1: map/unmap pll clocks
` [Intel-gfx] [PATCH v6 19/24] drm/i915/dg1: enable PORT C/D aka D/E
` [Intel-gfx] [PATCH v6 20/24] drm/i915/dg1: Load DMC
` [Intel-gfx] [PATCH v6 21/24] drm/i915/dg1: Add initial DG1 workarounds
` [Intel-gfx] [PATCH v6 22/24] drm/i915/dg1: DG1 does not support DC6
` [Intel-gfx] [PATCH v6 23/24] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
` [Intel-gfx] [PATCH v6 24/24] drm/i915/dgfx: define llc and snooping behaviour
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [CI 1/3] drm/i915/gt: Signal cancelled requests
2020-09-30 16:57 UTC (5+ messages)
` [Intel-gfx] [CI 2/3] drm/i915/selftests: Finish pending mock requests on cancellation
` [Intel-gfx] [CI 3/3] drm/i915/gt: Retire cancelled requests on unload
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915/gt: Signal cancelled requests
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH rdma-next v4 0/4] Dynamicaly allocate SG table from the pages
2020-09-30 16:51 UTC (11+ messages)
` [Intel-gfx] [PATCH rdma-next v4 4/4] RDMA/umem: Move to allocate SG table from pages
[Intel-gfx] [PATCH 1/3] drm/i915/gt: Signal cancelled requests
2020-09-30 16:30 UTC (8+ messages)
` [Intel-gfx] [PATCH 2/3] drm/i915/selftests: Finish pending mock requests on cancellation
` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Retire cancelled requests on unload
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/gt: Signal cancelled requests
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2
2020-09-30 16:14 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/ehl: Limit eDP to HBR2 (rev2)
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/display/ehl: Limit eDP to HBR2 (rev3)
[Intel-gfx] [PATCH] Revert "drm/i915: Force state->modeset=true when distrust_bios_wm==true"
2020-09-30 15:00 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for "
[Intel-gfx] [PATCH v4 44/52] docs: gpu: i915.rst: Fix several C duplication warnings
2020-09-30 13:25 UTC
[Intel-gfx] [PATCH v2 1/3] drm/i915/vbt: Fix backlight parsing for VBT 234+
2020-09-30 13:03 UTC (5+ messages)
` [Intel-gfx] [PATCH v2 2/3] drm/i915/vbt: Update the version and expected size of BDB_GENERAL_DEFINITIONS map
` [Intel-gfx] [PATCH v2 3/3] drm/i915/vbt: Add VRR VBT toggle
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915/vbt: Fix backlight parsing for VBT 234+
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH 1/3] drm/i915/vbt: Fix backlight parsing for VBT 234+
2020-09-30 12:55 UTC (5+ messages)
` [Intel-gfx] [PATCH 2/3] drm/i915/vbt: Update the version and expected size of BDB_GENERAL_DEFINITIONS map
` [Intel-gfx] [PATCH 3/3] drm/i915/vbt: Add VRR VBT toggle
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/vbt: Fix backlight parsing for VBT 234+
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PULL] topic/gvt-ww-lock
2020-09-30 11:54 UTC (2+ messages)
[Intel-gfx] [PATCH][next] drm/i915: Fix inconsistent IS_ERR and PTR_ERR
2020-09-30 11:31 UTC (3+ messages)
[Intel-gfx] [PATCH] drm/i915: Read DIMM size in Gb rather than GB
2020-09-30 11:24 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/gt: Scrub HW state on remove
2020-09-30 10:11 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v2] vfio/pci: Refine Intel IGD OpRegion support
2020-09-29 22:06 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for vfio/pci: Refine Intel IGD OpRegion support (rev2)
[Intel-gfx] [PATCH v3 0/7] drm: Try to fix encoder possible_clones/crtc
2020-09-29 20:04 UTC (8+ messages)
` [Intel-gfx] [PATCH v3 6/7] drm: Validate encoder->possible_crtcs
[Intel-gfx] [PATCH] i915: Introduce quirk for shifting eDP brightness
2020-09-29 19:32 UTC (14+ messages)
[Intel-gfx] [v6 00/11] Enable HDR on MCA LSPCON based Gen9 devices
2020-09-29 16:22 UTC (13+ messages)
` [Intel-gfx] [v6 02/11] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon
` [Intel-gfx] [v6 03/11] drm/i915/display: Attach HDR property for capable Gen9 devices
` [Intel-gfx] [v6 04/11] drm/i915/display: Enable BT2020 for HDR on LSPCON devices
` [Intel-gfx] [v6 05/11] drm/i915/display: Enable HDR for Parade based lspcon
` [Intel-gfx] [v6 06/11] drm/i915/display: Implement infoframes readback for LSPCON
` [Intel-gfx] [v6 07/11] drm/i915/display: Implement DRM infoframe read "
[Intel-gfx] [PATCH 1/2] drm/atomic: document and enforce rules around "spurious" EBUSY
2020-09-29 15:48 UTC (3+ messages)
` [Intel-gfx] [PATCH 2/2] drm/atomic: debug output for EBUSY
[Intel-gfx] [patch 00/13] preempt: Make preempt count unconditional
2020-09-29 14:54 UTC (17+ messages)
[Intel-gfx] [PATCH i-g-t] i915/gen9_exec_parse: Check parsing of large objects
2020-09-29 13:19 UTC (3+ messages)
` [Intel-gfx] [PATCH i-g-t v2] "
[Intel-gfx] [PATCH 0/2] drm/i915/jsl: Update JasperLake Voltage swing table
2020-09-29 12:45 UTC (12+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
[Intel-gfx] [PATCH v3 0/4] dma-buf: Flag vmap'ed memory as system or I/O memory
2020-09-29 11:14 UTC (10+ messages)
[Intel-gfx] [PATCH v10 0/8] Asynchronous flip implementation for i915
2020-09-29 9:46 UTC (3+ messages)
[Intel-gfx] [PATCH] drm/i915: Avoid mixing integer types during batch copies
2020-09-29 8:45 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
[Intel-gfx] REGRESSION: in intel video driver following introduction of mm_struct.has_pinned
2020-09-29 8:23 UTC (2+ messages)
[Intel-gfx] [PATCH] drm/i915/selftests: Measure the energy consumed while in RC6
2020-09-29 7:59 UTC (4+ messages)
[Intel-gfx] [CI 1/3] drm/i915: Cancel outstanding work after disabling heartbeats on an engine
2020-09-29 7:40 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/3] "
[Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
2020-09-29 2:11 UTC (7+ messages)
` [Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming
` [Intel-gfx] [PATCH 2/5] drm/i915: Factor out skl_wrpll_calc_freq()
` [Intel-gfx] [PATCH 3/5] drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt. hard-coded PLL freqs
` [Intel-gfx] [PATCH 5/5] drm/i915/tgl: Add workaround for incorrect BIOS combo PHY DPLL programming
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
` [Intel-gfx] ✓ Fi.CI.BAT: success "
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