messages from 2021-01-13 22:05:37 to 2021-01-15 08:19:24 UTC [more...]
[Intel-gfx] [PATCH 1/4] drm/i915/selftests: Prepare the selftests for engine resets with ring submission
2021-01-15 8:19 UTC (3+ messages)
` [Intel-gfx] [PATCH 2/4] drm/i915/gt: Lift stop_ring() to reset_prepare
` [Intel-gfx] [PATCH 3/4] drm/i915/gt: Pull ring submission resume under its caller forcewake
[Intel-gfx] [BUG] on reboot: bisected to: drm/i915: Shut down displays gracefully on reboot
2021-01-15 7:50 UTC (6+ messages)
[Intel-gfx] [PATCH] drm/i915/display: Bitwise or the conversion colour specifier together
2021-01-15 7:24 UTC (6+ messages)
[Intel-gfx] [PATCH] drm/i915: support two CSC module on gen11 and later
2021-01-15 6:48 UTC (7+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
` [Intel-gfx] [PATCH v2] "
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: support two CSC module on gen11 and later (rev2)
[Intel-gfx] linux-next: build warnings after merge of the drm-misc tree
2021-01-15 1:23 UTC
[Intel-gfx] [PATCH v7 0/5] drm/i915: Add support for Intel's eDP backlight controls
2021-01-14 23:18 UTC (8+ messages)
` [Intel-gfx] [PATCH v7 1/5] drm/i915: Pass port to intel_panel_bl_funcs.get()
` [Intel-gfx] [PATCH v7 2/5] drm/i915: Keep track of pwm-related backlight hooks separately
` [Intel-gfx] [PATCH v7 3/5] drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)
` [Intel-gfx] [PATCH v7 4/5] drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight
` [Intel-gfx] [PATCH v7 5/5] drm/dp: Revert "drm/dp: Introduce EDID-based quirks"
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add support for Intel's eDP backlight controls (rev10)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH] drm/i915: Add DEBUG_GEM to the recommended CI config
2021-01-14 22:49 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 0/7] drm/i915: Shuffle DP code around
2021-01-14 22:44 UTC (10+ messages)
` [Intel-gfx] [PATCH 1/7] drm/i915: Fix the training pattern debug print
` [Intel-gfx] [PATCH 2/7] drm/i915: Remove dead TPS3->TPS2 fallback code
` [Intel-gfx] [PATCH 3/7] drm/i915: Remove dead signal level debugs
` [Intel-gfx] [PATCH 4/7] drm/i915: Relocate intel_dp_program_link_training_pattern()
` [Intel-gfx] [PATCH 5/7] drm/i915: Split intel_ddi_encoder_reset() from intel_dp_encoder_reset()
` [Intel-gfx] [PATCH 6/7] drm/i915: Fix the PHY compliance test vs. hotplug mishap
` [Intel-gfx] [PATCH 7/7] drm/i915: Introduce g4x_dp.c
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Shuffle DP code around
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH v7 0/3] drm/i915/gen12: Add display render clear color decompression support
2021-01-14 22:10 UTC (8+ messages)
` [Intel-gfx] [PATCH v7 1/3] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color
` [Intel-gfx] [PATCH v7 2/3] drm/i915/gem: Add a helper to read data from a GEM object page
` [Intel-gfx] [PATCH v7 3/3] drm/i915/tgl: Add Clear Color support for TGL Render Decompression
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen12: Add display render clear color decompression support
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH] drm/i915/uc: Add function to define defaults for GuC/HuC enable
2021-01-14 21:39 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Add function to define defaults for GuC/HuC enable (rev2)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 1/3] drm/i915/gem: split gem_create into own file
2021-01-14 21:35 UTC (9+ messages)
` [Intel-gfx] [PATCH 2/3] drm/i915/gem: sanity check object size in gem_create
` [Intel-gfx] [PATCH 3/3] drm/i915/region: convert object_create into object_init
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gem: split gem_create into own file
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [CI 1/5] drm/i915: Mark up protected uses of 'i915_request_completed'
2021-01-14 21:01 UTC (7+ messages)
` [Intel-gfx] [CI 2/5] drm/i915: Drop i915_request.lock serialisation around await_start
` [Intel-gfx] [CI 3/5] drm/i915/gem: Reduce ctx->engine_mutex for reading the clone source
` [Intel-gfx] [CI 4/5] drm/i915/gem: Reduce ctx->engines_mutex for get_engines()
` [Intel-gfx] [CI 5/5] drm/i915: Reduce test_and_set_bit to set_bit in i915_request_submit()
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/5] drm/i915: Mark up protected uses of 'i915_request_completed'
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH] drm-buf: Add debug option
2021-01-14 20:26 UTC (11+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm-buf: Add debug option (rev2)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH 1/2] drm/i915: Add DEBUG_GEM to the recommended CI config
2021-01-14 19:12 UTC (4+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915: Make GEM errors non-fatal by default
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Add DEBUG_GEM to the recommended CI config
` [Intel-gfx] ✓ Fi.CI.BAT: success "
[Intel-gfx] [PATCH v2 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-14 18:29 UTC (4+ messages)
` [Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: Exercise cross-process context isolation
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v6 0/4] drm/i915: Add support for Intel's eDP backlight controls
2021-01-14 17:49 UTC (9+ messages)
` [Intel-gfx] [PATCH v6 1/4] drm/i915: Keep track of pwm-related backlight hooks separately
` [Intel-gfx] [PATCH v6 2/4] drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)
` [Intel-gfx] [PATCH v6 3/4] drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlight
` [Intel-gfx] [PATCH v6 4/4] drm/dp: Revert "drm/dp: Introduce EDID-based quirks"
` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Add support for Intel's eDP backlight controls (rev9)
[Intel-gfx] [PATCH v4 00/18] VRR/Adaptive Sync Enabling on DP/eDP for TGL+
2021-01-14 17:15 UTC (20+ messages)
` [Intel-gfx] [PATCH v4 02/18] drm/i915/display/dp: Attach and set drm connector VRR property
` [Intel-gfx] [PATCH v4 04/18] drm/i915: Extract intel_mode_vblank_start()
` [Intel-gfx] [PATCH v4 05/18] drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()
` [Intel-gfx] [PATCH v4 07/18] drm/i915/display/dp: Do not enable PSR if VRR is enabled
` [Intel-gfx] [PATCH v4 08/18] drm/i915/display: VRR + DRRS cannot be enabled together
` [Intel-gfx] [PATCH v4 09/18] drm/i915: Rename VRR_CTL reg fields
` [Intel-gfx] [PATCH v4 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable
` [Intel-gfx] [PATCH v4 11/18] drm/i915/display/vrr: Send VRR push to flip the frame
` [Intel-gfx] [PATCH v4 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path
` [Intel-gfx] [PATCH v4 13/18] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink
` [Intel-gfx] [PATCH v4 14/18] drm/i915/display: Add HW state readout for VRR
` [Intel-gfx] [PATCH v4 15/18] drm/i915/display: Helpers for VRR vblank min and max start
` [Intel-gfx] [PATCH v4 16/18] drm/i915: Add vrr state dump
` [Intel-gfx] [PATCH v4 17/18] drm/i915: Fix vblank timestamps with VRR
` [Intel-gfx] [PATCH v4 18/18] drm/i915: Fix vblank evasion with vrr
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync Enabling on DP/eDP for TGL+
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [CI] drm/i915/gt: Reapply ppgtt enabling after engine resets
2021-01-14 16:29 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/dg1: Apply WA 1409120013 and 14011059788
2021-01-14 16:04 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
[Intel-gfx] [PATCH 00/11] [rfc v7.1] rebased refactor of intel_display
2021-01-14 16:00 UTC (21+ messages)
` [Intel-gfx] [PATCH 01/11] drm/i915: refactor some crtc code out of intel display. (v2)
` [Intel-gfx] [PATCH 02/11] drm/i915: refactor pll code out into intel_dpll.c
` [Intel-gfx] [PATCH 03/11] drm/i915: split fdi code out from intel_display.c
` [Intel-gfx] [PATCH 04/11] drm/i915: refactor ddi translations into a separate file
` [Intel-gfx] [PATCH 05/11] drm/i915: migrate hsw fdi code to new file
` [Intel-gfx] [PATCH 06/11] drm/i915: migrate skl planes code new file (v3)
` [Intel-gfx] [PATCH 07/11] drm/i915: move pipe update code into crtc
` [Intel-gfx] [PATCH 08/11] drm/i915: split fb scalable checks into g4x and skl versions
` [Intel-gfx] [PATCH 09/11] drm/i915: move is_ccs_modifier to an inline
` [Intel-gfx] [PATCH 10/11] drm/i915: migrate pll enable/disable code to intel_dpll.[ch]
` [Intel-gfx] [PATCH 11/11] drm/i915: migrate i9xx plane get config
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for rebased refactor of intel_display
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PULL] drm-intel-gt-next
2021-01-14 15:22 UTC
[Intel-gfx] [PATCH] drm/i915/gt: Prune 'inline' from execlists
2021-01-14 15:07 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [PATCH] drm/i915: Only enable DFP 4:4:4->4:2:0 conversion when outputting YCbCr 4:4:4
2021-01-14 15:06 UTC (3+ messages)
[Intel-gfx] [PATCH 01/10] drm/i915: Mark up protected uses of 'i915_request_completed'
2021-01-14 13:44 UTC (23+ messages)
` [Intel-gfx] [PATCH 02/10] drm/i915: Drop i915_request.lock serialisation around await_start
` [Intel-gfx] [PATCH 03/10] drm/i915/gem: Reduce ctx->engine_mutex for reading the clone source
` [Intel-gfx] [PATCH 04/10] drm/i915/gem: Reduce ctx->engines_mutex for get_engines()
` [Intel-gfx] [PATCH 05/10] drm/i915: Reduce test_and_set_bit to set_bit in i915_request_submit()
` [Intel-gfx] [PATCH 06/10] drm/i915/gt: Drop atomic for engine->fw_active tracking
` [Intel-gfx] [PATCH 07/10] drm/i915/gt: Extract busy-stats for ring-scheduler
` [Intel-gfx] [PATCH 08/10] drm/i915/gt: Convert stats.active to plain unsigned int
` [Intel-gfx] [PATCH 09/10] drm/i915/gt: Reduce engine runtime stats from seqlock to a latch
` [Intel-gfx] [PATCH 10/10] drm/i915/gt: Reduce GT "
[Intel-gfx] [PATCH] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-14 13:53 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v6 00/64] drm/i915: Remove obj->mm.lock!
2021-01-14 12:06 UTC (3+ messages)
` [Intel-gfx] [PATCH v6 01/64] drm/i915: Do not share hwsp across contexts any more, v6
[Intel-gfx] linux-next: build failure after merge of the drm-misc tree
2021-01-14 11:16 UTC (2+ messages)
[Intel-gfx] [rfc v7] rebased refactor of intel_display
2021-01-14 11:15 UTC (14+ messages)
` [Intel-gfx] [PATCH 01/11] drm/i915: refactor some crtc code out of intel display. (v2)
` [Intel-gfx] [PATCH 02/11] drm/i915: refactor pll code out into intel_dpll.c
` [Intel-gfx] [PATCH 03/11] drm/i915: split fdi code out from intel_display.c
` [Intel-gfx] [PATCH 04/11] drm/i915: refactor ddi translations into a separate file
` [Intel-gfx] [PATCH 05/11] drm/i915: migrate hsw fdi code to new file
` [Intel-gfx] [PATCH 06/11] drm/i915: migrate skl planes code new file (v3)
` [Intel-gfx] [PATCH 07/11] drm/i915: move pipe update code into crtc
` [Intel-gfx] [PATCH 08/11] drm/i915: split fb scalable checks into g4x and skl versions
` [Intel-gfx] [PATCH 09/11] drm/i915: move is_ccs_modifier to an inline
` [Intel-gfx] [PATCH 10/11] drm/i915: migrate pll enable/disable code to intel_dpll.[ch]
` [Intel-gfx] [PATCH 11/11] drm/i915: migrate i9xx plane get config
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [01/11] drm/i915: refactor some crtc code out of intel display. (v2)
[Intel-gfx] [PULL] drm-intel-fixes
2021-01-14 10:54 UTC
[Intel-gfx] [PATCH] drm/i915/selftests: fix the uint*_t types that have crept in
2021-01-14 10:23 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Exercise relative mmio paths to non-privileged registers
2021-01-14 10:18 UTC (4+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Exercise cross-process context isolation
[Intel-gfx] [PATCH v2 00/17] drm/i915/dp: split out pps and aux
2021-01-14 8:56 UTC (10+ messages)
` [Intel-gfx] [PATCH v2 13/17] drm/i915/pps: rename intel_dp_init_panel_power_sequencer* functions
` [Intel-gfx] [PATCH v2 14/17] drm/i915/pps: refactor init abstractions
` [Intel-gfx] [PATCH v2 15/17] drm/i915/pps: move pps code over from intel_display.c and refactor
[Intel-gfx] [PATCH] drm/i915/display: fix the uint*_t types that have crept in
2021-01-14 8:13 UTC (3+ messages)
[Intel-gfx] [PATCH] drm/i915/display: remove useless use of inline
2021-01-14 8:12 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
[Intel-gfx] [PATCH v2] drm/i915: Try to guess PCH type even without ISA bridge
2021-01-14 5:14 UTC (3+ messages)
` [Intel-gfx] [PATCH v4] "
[Intel-gfx] [PATCH 2/2] bdi: Use might_alloc()
2021-01-14 5:07 UTC (2+ messages)
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Try to guess PCH type even without ISA bridge
2021-01-14 4:59 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Try to guess PCH type even without ISA bridge (rev4)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [rfc v7] rebased refactor of intel_display
2021-01-14 3:05 UTC
[Intel-gfx] [CI 1/2] drm/i915/selftests: Force a failed engine reset
2021-01-14 2:38 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with drm/i915/selftests: Force a failed engine reset (rev2)
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [CI] drm/i915/gt: Replace open-coded intel_engine_stop_cs()
2021-01-14 1:46 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Replace open-coded intel_engine_stop_cs() (rev3)
[Intel-gfx] [CI 1/2] drm/i915/gt: Rearrange vlv workarounds
2021-01-14 0:52 UTC (3+ messages)
` [Intel-gfx] [CI 2/2] drm/i915/gt: Rearrange ivb workarounds
` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/gt: Rearrange vlv workarounds
[Intel-gfx] [PATCH] drm/i915/gt: Prune inlines
2021-01-14 0:51 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
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