messages from 2021-02-05 09:49:01 to 2021-02-07 02:31:12 UTC [more...]
[Intel-gfx] [CI 1/4] drm/i915: Move submit_request to i915_sched_engine
2021-02-07 2:31 UTC
[Intel-gfx] [CI 1/4] drm/i915: Move submit_request to i915_sched_engine
2021-02-07 0:40 UTC (7+ messages)
` [Intel-gfx] [CI 2/4] drm/i915: Move finding the current active request to the scheduler
` [Intel-gfx] [CI 3/4] drm/i915: Show execlists queues when dumping state
` [Intel-gfx] [CI 4/4] drm/i915: Wrap i915_request_use_semaphores()
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915: Move submit_request to i915_sched_engine
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [CI 1/4] drm/i915: Move submit_request to i915_sched_engine
2021-02-06 21:57 UTC (7+ messages)
` [Intel-gfx] [CI 2/4] drm/i915: Move finding the current active request to the scheduler
` [Intel-gfx] [CI 3/4] drm/i915: Show execlists queues when dumping state
` [Intel-gfx] [CI 4/4] drm/i915: Wrap i915_request_use_semaphores()
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915: Move submit_request to i915_sched_engine
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [RFC 00/14] Introduce Intel PXP
2021-02-06 16:51 UTC (28+ messages)
` [Intel-gfx] [RFC 01/14] drm/i915/pxp: Define PXP component interface
` [Intel-gfx] [RFC 02/14] mei: pxp: export pavp client to me client bus
` [Intel-gfx] [RFC 03/14] drm/i915/pxp: define PXP device flag and kconfig
` [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage
` [Intel-gfx] [RFC 05/14] drm/i915/pxp: set KCR reg init during the boot time
` [Intel-gfx] [RFC 06/14] drm/i915/pxp: Implement funcs to create the TEE channel
` [Intel-gfx] [RFC 07/14] drm/i915/pxp: Create the arbitrary session after boot
` [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown
` [Intel-gfx] [RFC 09/14] drm/i915/pxp: Implement PXP irq handler
` [Intel-gfx] [RFC 10/14] drm/i915/pxp: Enable PXP power management
` [Intel-gfx] [RFC 11/14] drm/i915/uapi: introduce drm_i915_gem_create_ext
` [Intel-gfx] [RFC 12/14] drm/i915/pxp: User interface for Protected buffer
` [Intel-gfx] [RFC 13/14] drm/i915/pxp: Add plane decryption support
` [Intel-gfx] [RFC 14/14] drm/i915/pxp: enable PXP for integrated Gen12
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [CI 1/5] drm/i915: Wrap access to intel_engine.active
2021-02-06 15:59 UTC (9+ messages)
` [Intel-gfx] [CI 2/5] drm/i915: Move common active lists from engine to i915_scheduler
` [Intel-gfx] [CI 3/5] drm/i915: Move scheduler queue
` [Intel-gfx] [CI 4/5] drm/i915: Move tasklet from execlists to sched
` [Intel-gfx] [CI 5/5] drm/i915/gt: Only kick the scheduler on timeslice/preemption change
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/5] drm/i915: Wrap access to intel_engine.active
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI 1/4] drm/i915: Move submit_request to i915_sched_engine
2021-02-06 15:36 UTC (6+ messages)
` [Intel-gfx] [CI 2/4] drm/i915: Move finding the current active request to the scheduler
` [Intel-gfx] [CI 3/4] drm/i915: Show execlists queues when dumping state
` [Intel-gfx] [CI 4/4] drm/i915: Wrap i915_request_use_semaphores()
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915: Move submit_request to i915_sched_engine
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [RFC v3 00/10] drm: Extract DPCD backlight helpers from i915, add support in nouveau
2021-02-06 15:09 UTC (15+ messages)
` [Intel-gfx] [RFC v3 01/10] drm/nouveau/kms/nv40-/backlight: Assign prop type once
` [Intel-gfx] [RFC v3 02/10] drm/nouveau/kms: Don't probe eDP connectors more then once
` [Intel-gfx] [RFC v3 03/10] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
` [Intel-gfx] [RFC v3 04/10] drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
` [Intel-gfx] [RFC v3 05/10] drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
` [Intel-gfx] [Nouveau] "
` [Intel-gfx] [RFC v3 06/10] drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
` [Intel-gfx] [RFC v3 07/10] drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
` [Intel-gfx] [RFC v3 08/10] drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
` [Intel-gfx] [RFC v3 09/10] drm/i915/dpcd_bl: Print return codes for VESA backlight failures
` [Intel-gfx] [RFC v3 10/10] drm/dp: Extract i915's eDP backlight code into DRM helpers
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev5)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] kernel: Expose SYS_kcmp by default
2021-02-06 14:21 UTC (15+ messages)
` [Intel-gfx] [PATCH v2] "
` [Intel-gfx] [PATCH v3] kcmp: Support selection of SYS_kcmp without CHECKPOINT_RESTORE
` [Intel-gfx] ✓ Fi.CI.BAT: success for kernel: Expose SYS_kcmp by default (rev3)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] RFC: dma-buf: Require VM_SPECIAL vma for mmap
2021-02-06 14:22 UTC (6+ messages)
` [Intel-gfx] [PATCH] RFC: dma-buf: Require VM_PFNMAP "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for RFC: dma-buf: Require VM_SPECIAL vma for mmap (rev2)
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
` [Intel-gfx] [RFC] b922393a2c: WARNING:at_drivers/dma-buf/dma-buf.c:#dma_buf_mmap_internal
[Intel-gfx] [PATCH v3 00/15] drm/i915: Clean up the DDI clock routing mess
2021-02-06 11:51 UTC (20+ messages)
` [Intel-gfx] [PATCH v3 01/15] drm/i915: Use intel_ddi_clk_select() for FDI
` [Intel-gfx] [PATCH v3 02/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
` [Intel-gfx] [PATCH v3 03/15] drm/i915: Extract hsw_ddi_{enable, disable}_clock()
` [Intel-gfx] [PATCH v3 04/15] drm/i915: Extract skl_ddi_{enable, disable}_clock()
` [Intel-gfx] [PATCH v3 05/15] drm/i195: Extract cnl_ddi_{enable, disable}_clock()
` [Intel-gfx] [PATCH v3 06/15] drm/i915: Convert DG1 over to .{enable, disable}_clock()
` [Intel-gfx] [PATCH v3 07/15] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs
` [Intel-gfx] [PATCH v3 08/15] drm/i915: Use intel_de_rmw() for DDI clock routing
` [Intel-gfx] [PATCH v3 09/15] drm/i915: Sprinkle a few missing locks around shared DDI clock registers
` [Intel-gfx] [PATCH v3 10/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()
` [Intel-gfx] [PATCH v3 11/15] drm/i915: Extract _cnl_ddi_{enable, disable}_clock()
` [Intel-gfx] [PATCH v3 12/15] drm/i915: Split adl-s/rkl from icl_ddi_combo_{enable, disable}_clock()
` [Intel-gfx] [PATCH v3 13/15] drm/i915: Use .disable_clock() for pll sanitation
` [Intel-gfx] [PATCH v3 14/15] drm/i915: Relocate icl_sanitize_encoder_pll_mapping()
` [Intel-gfx] [PATCH v3 15/15] drm/i915: s/dev_priv/i915/ for the remainder of DDI clock routing
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up the DDI clock routing mess (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915: Nuke INTEL_OUTPUT_FORMAT_INVALID
2021-02-06 10:58 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915: Add link rate and lane count to i915_display_info
2021-02-06 10:13 UTC (7+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
` [Intel-gfx] [PATCH v2] "
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add link rate and lane count to i915_display_info (rev2)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/display: Allow PSR2 selective fetch to be enabled at run-time
2021-02-06 8:28 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH v12 0/8] drm/i915: refactor intel_display.c + a bit more
2021-02-06 7:41 UTC (17+ messages)
` [Intel-gfx] [PATCH v12 1/8] drm/i915: migrate skl planes code new file (v5)
` [Intel-gfx] [PATCH v12 2/8] drm/i915: move pipe update code into crtc. (v2)
` [Intel-gfx] [PATCH v12 3/8] drm/i915: split fb scalable checks into g4x and skl versions
` [Intel-gfx] [PATCH v12 4/8] drm/i915: move is_ccs_modifier to an inline
` [Intel-gfx] [PATCH v12 5/8] drm/i915: migrate pll enable/disable code to intel_dpll.[ch]
` [Intel-gfx] [PATCH v12 6/8] drm/i915: migrate i9xx plane get config
` [Intel-gfx] [PATCH v12 7/8] drm/i915: refactor skylake scaler code into new file
` [Intel-gfx] [PATCH v12 8/8] drm/i915: move ddi pll state get to dpll mgr
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: refactor intel_display.c + a bit more (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/gt: Ratelimit heartbeat completion probing
2021-02-06 6:45 UTC (7+ messages)
` [Intel-gfx] [PATCH v4] "
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Ratelimit heartbeat completion probing (rev5)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Ratelimit heartbeat completion probing (rev7)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915: Autoselect CONFIG_CHECKPOINT_RESTORE for SYS_kcmp
2021-02-06 4:21 UTC (6+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [CI] drm/i915/selftest: Synchronise with the GPU timestamp
2021-02-06 3:25 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftest: Synchronise with the GPU timestamp (rev2)
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [CI 1/2] drm/i915/gt: Always flush the submission queue on checking for idle
2021-02-05 22:07 UTC (3+ messages)
` [Intel-gfx] [CI 2/2] drm/i915/gt: Pull all execlists scheduler initialisation together
` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915/gt: Always flush the submission queue on checking for idle
[Intel-gfx] [PATCH] drm/vblank: Avoid storing a timestamp for the same frame twice
2021-02-05 21:19 UTC (6+ messages)
[Intel-gfx] [PATCH v2 1/2] drm/i915: cleanup the region class/instance encoding
2021-02-05 20:58 UTC (4+ messages)
` [Intel-gfx] [PATCH v2 2/2] drm/i915: give stolen system memory its own class
` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915: cleanup the region class/instance encoding
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [PATCH] drm/i915/vbt: update DP max link rate table
2021-02-05 20:26 UTC (2+ messages)
[Intel-gfx] [PATCH 0/3] HDMI2.1 PCON Misc Fixes
2021-02-05 20:22 UTC (10+ messages)
` [Intel-gfx] [PATCH 1/3] i915/display/intel_dp: Read PCON DSC ENC caps only for DPCD rev >= 1.4
` [Intel-gfx] [PATCH 2/3] drm/dp_helper: Define options for FRL training for HDMI2.1 PCON
` [Intel-gfx] [PATCH 3/3] i915/display: Remove FRL related code from disable DP sequence for older platforms
[Intel-gfx] [PATCH] drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register
2021-02-05 18:48 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [PATCH] drm/i915/hdcp: Show connector hdcp capability
2021-02-05 18:21 UTC (2+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
[Intel-gfx] [PATCH i-g-t] i915/module_load: Tidy up gem_exec_store workalike
2021-02-05 17:43 UTC (2+ messages)
[Intel-gfx] linux-next: manual merge of the drivers-x86 tree with the drm-misc tree
2021-02-05 14:01 UTC (6+ messages)
[Intel-gfx] [PATCH v11 00/10] drm/i915: refactor intel_display.c + a bit more
2021-02-05 13:52 UTC (5+ messages)
` [Intel-gfx] [PATCH v11 01/10] drm/i915: refactor ddi translations into a separate file (v2)
` [Intel-gfx] [PATCH v11 02/10] drm/i915: migrate hsw fdi code to new file
[Intel-gfx] [PATCH 1/2] drm/i915: Index min_{cdclk, voltage_level}[] with pipe
2021-02-05 13:50 UTC (4+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915: Use intel_hdmi_port_clock() more
[Intel-gfx] [PATCH] drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters read only
2021-02-05 13:41 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "
[Intel-gfx] [PATCH] drm/i915/display: Remove PSR2 on JSL and EHL
2021-02-05 13:39 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [PATCH v15 1/2] drm/i915/display: Support PSR Multiple Instances
2021-02-05 13:33 UTC (4+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v15,1/2] "
[Intel-gfx] [PATCH] drm/i915/display: support ddr5 mem types
2021-02-05 13:25 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [PATCH v2] drm/i915/debugfs : PM_REQ and PM_RES registers
2021-02-05 13:09 UTC (5+ messages)
` [Intel-gfx] [PATCH v4] "
[Intel-gfx] [PATCH 32/56] drm/i915: Move scheduler queue
2021-02-04 13:36 UTC
[Intel-gfx] [PATCH] drm/i915/debugfs: HDCP capability enc NULL check
2021-02-05 12:12 UTC (5+ messages)
[Intel-gfx] [PATCH 01/57] drm/i915/gt: Restrict the GT clock override to just Icelake
2021-02-05 9:48 UTC (5+ messages)
` [Intel-gfx] [PATCH 30/57] drm/i915: Move timeslicing flag to scheduler
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