messages from 2021-07-01 16:58:14 to 2021-07-05 07:45:23 UTC [more...]
[Intel-gfx] [PATCH v15 00/12] Restricted DMA
2021-07-05 7:29 UTC (18+ messages)
` [Intel-gfx] [PATCH v15 06/12] swiotlb: Use is_swiotlb_force_bounce for swiotlb data bouncing
` [Intel-gfx] [PATCH v15 12/12] of: Add plumbing for restricted DMA pool
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Restricted DMA (rev2)
[Intel-gfx] [PATCH] include/uapi/drm: fix spelling mistakes in header files
2021-07-03 9:00 UTC (2+ messages)
[Intel-gfx] [PATCH] drm/i915/dmc: Use RUNTIME_INFO->stp for DMC
2021-07-05 7:45 UTC (8+ messages)
[Intel-gfx] [PATCH v6 0/2] drm/i915/display/dsc: Set BPP in the kernel
2021-07-05 7:23 UTC (7+ messages)
` [Intel-gfx] [PATCH v6 /2] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable
` [Intel-gfx] [PATCH v6 2/2] drm/i915/display/dsc: Set BPP in the kernel
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH v5 0/2] drm/i915: IRQ fixes
2021-07-03 17:55 UTC (8+ messages)
` [Intel-gfx] [PATCH v5 1/2] drm/i915: Use the correct IRQ during resume
` [Intel-gfx] [PATCH v5 2/2] drm/i915: Drop all references to DRM IRQ midlayer
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: IRQ fixes (rev4)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 00/47] GuC submission support
2021-07-03 8:21 UTC (17+ messages)
` [Intel-gfx] [PATCH 47/47] drm/i915/guc: Unblock GuC submission on Gen11+
[Intel-gfx] [PATCH 0/8] drm/i915/fbc: Rework CFB stride/size calculations
2021-07-03 1:37 UTC (12+ messages)
` [Intel-gfx] [PATCH 1/8] drm/i915/fbc: Rewrite the FBC tiling check a bit
` [Intel-gfx] [PATCH 2/8] drm/i915/fbc: Extract intel_fbc_update()
` [Intel-gfx] [PATCH 3/8] drm/i915/fbc: Move the "recompress on activate" to a central place
` [Intel-gfx] [PATCH 4/8] drm/i915/fbc: Polish the skl+ FBC stride override handling
` [Intel-gfx] [PATCH 5/8] drm/i915/fbc: Rework cfb stride/size calculations
` [Intel-gfx] [PATCH 6/8] drm/i915/fbc: Align FBC segments to 512B on glk+
` [Intel-gfx] [PATCH 7/8] drm/i915/fbc: Implement Wa_16011863758 for icl+
` [Intel-gfx] [PATCH 8/8] drm/i915/fbc: Allow higher compression limits on FBC1
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/fbc: Rework CFB stride/size calculations
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH] drm/i915: Improve debug Kconfig texts a bit
2021-07-03 0:40 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v2 1/3] drm/i915: use consistent CPU mappings for pin_map users
2021-07-02 19:22 UTC (6+ messages)
` [Intel-gfx] [PATCH v2 3/3] drm/i915/uapi: reject set_domain for discrete
` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/3] drm/i915: use consistent CPU mappings for pin_map users
[Intel-gfx] [PATCH 1/3] drm/i915: use consistent CPU mappings for pin_map users
2021-07-02 19:16 UTC (4+ messages)
` [Intel-gfx] [PATCH 2/3] drm/i915/uapi: reject caching ioctls for discrete
` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: use consistent CPU mappings for pin_map users
[Intel-gfx] [PATCH v4 0/2] drm/i915: IRQ fixes
2021-07-02 19:13 UTC (2+ messages)
[Intel-gfx] [PATCH v7 0/5] drm: address potential UAF bugs with drm_master ptrs
2021-07-02 19:07 UTC (9+ messages)
` [Intel-gfx] [PATCH v7 1/5] drm: avoid circular locks in drm_mode_getconnector
` [Intel-gfx] [PATCH v7 2/5] drm: separate locks in __drm_mode_object_find
` [Intel-gfx] [PATCH v7 3/5] drm: add a locked version of drm_is_current_master
` [Intel-gfx] [PATCH v7 4/5] drm: serialize drm_file.master with a master lock
` [Intel-gfx] [PATCH v7 5/5] drm: protect drm_master pointers in drm_lease.c
` [Intel-gfx] ✓ Fi.CI.BAT: success for drm: address potential UAF bugs with drm_master ptrs
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 1/2] drm/i915/gem: Correct the locking and pin pattern for dma-buf
2021-07-02 17:09 UTC (2+ messages)
[Intel-gfx] [PATCH 1/2] drm/i915/selftests: fix smatch warning in igt_check_blocks
2021-07-02 14:04 UTC (5+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915/selftests: fix smatch warning in mock_reserve
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: fix smatch warning in igt_check_blocks
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v5 0/2] drm/i915/display/dsc: Set BPP in the kernel
2021-07-02 13:22 UTC (7+ messages)
` [Intel-gfx] [PATCH v5 1/2] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable
` [Intel-gfx] [PATCH v5 2/2] drm/i915/display/dsc: Set BPP in the kernel
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/dsc: Set BPP in the kernel (rev5)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 00/53] Begin enabling Xe_HP SDV and DG2 platforms
2021-07-02 12:42 UTC (73+ messages)
` [Intel-gfx] [PATCH 01/53] drm/i915: Add "release id" version
` [Intel-gfx] [PATCH 02/53] drm/i915: Add XE_HP initial definitions
` [Intel-gfx] [PATCH 03/53] drm/i915: Fork DG1 interrupt handler
` [Intel-gfx] [PATCH 04/53] drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-based
` [Intel-gfx] [PATCH 05/53] drm/i915/gen12: Use fuse info to enable SFC
` [Intel-gfx] [PATCH 06/53] drm/i915/selftests: Allow for larger engine counts
` [Intel-gfx] [PATCH 07/53] drm/i915/xehp: Extra media engines - Part 1 (engine definitions)
` [Intel-gfx] [PATCH 08/53] drm/i915/xehp: Extra media engines - Part 2 (interrupts)
` [Intel-gfx] [PATCH 09/53] drm/i915/xehp: Extra media engines - Part 3 (reset)
` [Intel-gfx] [PATCH 10/53] drm/i915/xehp: Xe_HP forcewake support
` [Intel-gfx] [PATCH 11/53] drm/i915/xehp: Define multicast register ranges
` [Intel-gfx] [PATCH 12/53] drm/i915/xehp: Handle new device context ID format
` [Intel-gfx] [PATCH 13/53] drm/i915/xehp: New engine context offsets
` [Intel-gfx] [PATCH 14/53] drm/i915/xehp: handle new steering options
` [Intel-gfx] [PATCH 15/53] drm/i915/xehp: Loop over all gslices for INSTDONE processing
` [Intel-gfx] [PATCH 16/53] drm/i915/xehpsdv: add initial XeHP SDV definitions
` [Intel-gfx] [PATCH 17/53] drm/i915/xehp: Changes to ss/eu definitions
` [Intel-gfx] [PATCH 18/53] drm/i915/xehpsdv: Add maximum sseu limits
` [Intel-gfx] [PATCH 19/53] drm/i915/xehpsdv: Add compute DSS type
` [Intel-gfx] [PATCH 20/53] drm/i915/xehpsdv: Define steering tables
` [Intel-gfx] [PATCH 21/53] drm/i915/xehpsdv: Define MOCS table for XeHP SDV
` [Intel-gfx] [PATCH 22/53] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP
` [Intel-gfx] [PATCH 23/53] drm/i915/xehpsdv: Read correct RP_STATE_CAP register
` [Intel-gfx] [PATCH 24/53] drm/i915/dg2: add DG2 platform info
` [Intel-gfx] [PATCH 25/53] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
` [Intel-gfx] [PATCH 26/53] drm/i915/dg2: Add forcewake table
` [Intel-gfx] [PATCH 27/53] drm/i915/dg2: Update LNCF steering ranges
` [Intel-gfx] [PATCH 28/53] drm/i915/dg2: Add SQIDI steering
` [Intel-gfx] [PATCH 29/53] drm/i915/dg2: Add new LRI reg offsets
` [Intel-gfx] [PATCH 30/53] drm/i915/dg2: Maintain backward-compatible nested batch behavior
` [Intel-gfx] [PATCH 31/53] drm/i915/dg2: Report INSTDONE_GEOM values in error state
` [Intel-gfx] [PATCH 32/53] drm/i915/dg2: Define MOCS table for DG2
` [Intel-gfx] [PATCH 33/53] drm/i915/dg2: Add fake PCH
` [Intel-gfx] [PATCH 34/53] drm/i915/dg2: Add cdclk table and reference clock
` [Intel-gfx] [PATCH 35/53] drm/i915/dg2: Skip shared DPLL handling
` [Intel-gfx] [PATCH 36/53] drm/i915/dg2: Don't wait for AUX power well enable ACKs
` [Intel-gfx] [PATCH 37/53] drm/i915/dg2: Setup display outputs
` [Intel-gfx] [PATCH 38/53] drm/i915/dg2: Add dbuf programming
` [Intel-gfx] [PATCH 39/53] drm/i915/dg2: Don't program BW_BUDDY registers
` [Intel-gfx] [PATCH 40/53] drm/i915/dg2: Don't read DRAM info
` [Intel-gfx] [PATCH 41/53] drm/i915/dg2: DG2 has fixed memory bandwidth
` [Intel-gfx] [PATCH 42/53] drm/i915/dg2: Add MPLLB programming for SNPS PHY
` [Intel-gfx] [PATCH 43/53] drm/i915/dg2: Add MPLLB programming for HDMI
` [Intel-gfx] [PATCH 44/53] drm/i915/dg2: Add vswing programming for SNPS phys
` [Intel-gfx] [PATCH 45/53] drm/i915/dg2: Update modeset sequences
` [Intel-gfx] [PATCH 46/53] drm/i915/dg2: Classify DG2 PHY types
` [Intel-gfx] [PATCH 47/53] drm/i915/dg2: Wait for SNPS PHY calibration during display init
` [Intel-gfx] [PATCH 48/53] drm/i915/dg2: Update lane disable power state during PSR
` [Intel-gfx] [PATCH 49/53] drm/i915/dg2: Add DG2 to the PSR2 defeature list
` [Intel-gfx] [PATCH 50/53] drm/i915/display/dsc: Add Per connector debugfs node for DSC BPP enable
` [Intel-gfx] [PATCH 51/53] drm/i915/display/dsc: Set BPP in the kernel
` [Intel-gfx] [PATCH 52/53] drm/i915/dg2: Update to bigjoiner path
` [Intel-gfx] [PATCH 53/53] drm/i915/dg2: Configure PCON in DP pre-enable path
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Begin enabling Xe_HP SDV and DG2 platforms
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "
[Intel-gfx] [drm-intel:drm-intel-gt-next 8/14] drivers/gpu/drm/i915/gt/selftest_migrate.c:102 copy() error: uninitialized symbol 'rq'
2021-07-02 12:19 UTC (7+ messages)
[Intel-gfx] [drm-intel:drm-intel-gt-next 7/8] drivers/gpu/drm/i915/selftests/intel_memory_region.c:227 igt_mock_reserve() error: 'mem' dereferencing possible ERR_PTR()
2021-07-02 9:30 UTC
[Intel-gfx] [PATCH 0/2] Stepping/substepping reorg for DMC
2021-07-02 8:56 UTC (7+ messages)
` [Intel-gfx] [PATCH 1/2] drm/i915/dmc: Use RUNTIME_INFO->step "
` [Intel-gfx] [PATCH 2/2] drm/i915/dmc: Add steping info table for remaining platforms
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Stepping/substepping reorg for DMC
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "
[Intel-gfx] [PATCH 0/7] CT changes required for GuC submission
2021-07-02 6:55 UTC (11+ messages)
` [Intel-gfx] [PATCH 1/7] drm/i915/guc: Relax CTB response timeout
` [Intel-gfx] [PATCH 3/7] drm/i915/guc: Increase size of CTB buffers
` [Intel-gfx] [PATCH 4/7] drm/i915/guc: Add non blocking CTB send function
` [Intel-gfx] [PATCH 5/7] drm/i915/guc: Add stall timer to "
` [Intel-gfx] [PATCH 6/7] drm/i915/guc: Optimize CTB writes and reads
` [Intel-gfx] [PATCH 7/7] drm/i915/guc: Module load failure test for CT buffer creation
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CT changes required for GuC submission (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH v1 1/2] drm/i915/gem: Correct the locking and pin pattern for dma-buf
2021-07-02 6:31 UTC (4+ messages)
` [Intel-gfx] [PATCH v1 2/2] drm/i915/gem: Migrate to system at dma-buf attach time
` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v1,1/2] drm/i915/gem: Correct the locking and pin pattern for dma-buf
[Intel-gfx] [PATCH] drm/i915/guc: Improve GuC CTB ABI
2021-07-02 2:19 UTC (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 0/4] drm/i915/guc: Improve CTB error handling
2021-07-02 1:31 UTC (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
[Intel-gfx] [PATCH 1/2] drm/i915/gem: Correct the locking and pin pattern for dma-buf
2021-07-01 19:58 UTC (2+ messages)
` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] "
[Intel-gfx] [PULL] drm-intel-next-fixes
2021-07-01 19:30 UTC (5+ messages)
[Intel-gfx] [PATCH 0/1] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR
2021-07-01 19:27 UTC (3+ messages)
` [Intel-gfx] [PATCH 1/1] "
[Intel-gfx] Requests For Proposals for hosting XDC 2022 are now open
2021-07-01 16:14 UTC (2+ messages)
` [Intel-gfx] [Mesa-dev] "
[Intel-gfx] [PATCH] drm/i915/display: check if compressed_llb was allocated
2021-07-01 17:42 UTC (3+ messages)
[Intel-gfx] [PATCH] drm/i915/display/dg1: Correctly map DPLLs during state readout
2021-07-01 17:19 UTC (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
[Intel-gfx] [PATCH] drm/i915/gt: Fix -EDEADLK handling regression
2021-07-01 17:00 UTC (3+ messages)
page: next (older) | prev (newer) | latest
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).