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 messages from 2021-07-28 22:00:27 to 2021-07-30 00:01:52 UTC [more...]

[Intel-gfx] [PATCH 00/25] Remove CNL - for drm-intel-next
 2021-07-30  0:01 UTC  (13+ messages)
` [Intel-gfx] [PATCH 13/25] drm/i915/display: remove explicit CNL handling from intel_display_power.c
` [Intel-gfx] [PATCH 17/25] drm/i915: remove explicit CNL handling from intel_pm.c
` [Intel-gfx] [PATCH 18/25] drm/i915: remove explicit CNL handling from intel_pch.c
` [Intel-gfx] [PATCH 19/25] drm/i915: remove explicit CNL handling from intel_wopcm.c
` [Intel-gfx] [PATCH 22/25] drm/i915: switch num_scalers/num_sprites to consider DISPLAY_VER
` [Intel-gfx] [PATCH 24/25] drm/i915: rename/remove CNL registers
` [Intel-gfx] [PATCH 25/25] drm/i915: finish removal of CNL
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Remove CNL - for drm-intel-next
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Remove CNL - for drm-intel-next (rev2)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Remove CNL - for drm-intel-next (rev3)

[Intel-gfx] [PATCH i-g-t 0/1] Fix gem_scheduler.manycontexts for GuC submission
 2021-07-30  0:00 UTC  (4+ messages)
` [Intel-gfx] [PATCH i-g-t 1/1] i915/gem_scheduler: Ensure submission order in manycontexts
  ` [Intel-gfx] [igt-dev] "

[Intel-gfx] [PATCH v4 00/14] drm/i915/guc/slpc: Enable GuC based power management features
 2021-07-29 23:40 UTC  (20+ messages)
` [Intel-gfx] [PATCH 01/14] drm/i915/guc/slpc: Initial definitions for SLPC
` [Intel-gfx] [PATCH 03/14] drm/i915/guc/slpc: Adding SLPC communication interfaces
` [Intel-gfx] [PATCH 05/14] drm/i915/guc/slpc: Enable SLPC and add related H2G events
` [Intel-gfx] [PATCH 07/14] drm/i915/guc/slpc: Add methods to set min/max frequency
` [Intel-gfx] [PATCH 11/14] drm/i915/guc/slpc: Cache platform frequency limits
` [Intel-gfx] [PATCH 12/14] drm/i915/guc/slpc: Sysfs hooks for SLPC
` [Intel-gfx] [PATCH 13/14] drm/i915/guc/slpc: Add SLPC selftest
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc/slpc: Enable GuC based power management features (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH 10/25] drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.c
 2021-07-29 23:39 UTC  (2+ messages)
` [Intel-gfx] [PATCH v1.1 "

[Intel-gfx] [PATCH 0/6] Forcewake and shadowed register updates
 2021-07-29 23:36 UTC  (18+ messages)
` [Intel-gfx] [PATCH 1/6] drm/i915: correct name of GT forcewake domain in error messages
` [Intel-gfx] [PATCH 2/6] drm/i915: Re-use gen11 forcewake read functions on gen12
` [Intel-gfx] [PATCH 3/6] drm/i915: Make shadow tables range-based
  ` [Intel-gfx] [PATCH v2 "
` [Intel-gfx] [PATCH 4/6] drm/i915/gen11: Update shadowed register table
` [Intel-gfx] [PATCH 5/6] drm/i915/gen12: "
` [Intel-gfx] [PATCH 6/6] drm/i915/xehp: Xe_HP shadowed registers are a strict superset of gen12
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Forcewake and shadowed register updates (rev2)
` [Intel-gfx] ✓ Fi.CI.BAT: success "

[Intel-gfx] [PATCH i-g-t 0/7] Updates for GuC & parallel submission
 2021-07-29 23:35 UTC  (4+ messages)
` [Intel-gfx] [PATCH i-g-t 6/7] i915/gem_scheduler: Make gem_scheduler understand static priority mapping
  ` [Intel-gfx] [igt-dev] "

[Intel-gfx] [PATCH 1/2] drm/i915/selftests: fixup igt_shrink_thp
 2021-07-29 23:16 UTC  (6+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH v3 0/1] lpsp with hdmi/dp outputs
 2021-07-29 22:27 UTC  (4+ messages)
` [Intel-gfx] [PATCH v3 1/1] drm/i915/dg1: Adjust the AUDIO power domain
` [Intel-gfx] ✓ Fi.CI.BAT: success for lpsp with hdmi/dp outputs
` [Intel-gfx] ✗ Fi.CI.IGT: failure "

[Intel-gfx] [PATCH CI 01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
 2021-07-29 22:26 UTC  (13+ messages)
` [Intel-gfx] [PATCH CI 02/10] drm/i915/bios: Start to support two integrated panels
` [Intel-gfx] [PATCH CI 03/10] drm/i915/bios: Enable parse of two integrated panels timing data
` [Intel-gfx] [PATCH CI 04/10] drm/i915/bios: Enable parse of two integrated panels backlight data
` [Intel-gfx] [PATCH CI 05/10] drm/i915/bios: Enable parse of two integrated panels eDP data
` [Intel-gfx] [PATCH CI 06/10] drm/i915/bios: Enable parse of two integrated panels PSR data
` [Intel-gfx] [PATCH CI 07/10] drm/i915/bios: Enable parse of two DSI panels data
` [Intel-gfx] [PATCH CI 08/10] drm/i915/bios: Nuke panel_type
` [Intel-gfx] [PATCH CI 09/10] drm/i915/bios: Only use opregion panel index for display ver 8 and older
` [Intel-gfx] [PATCH CI 10/10] drm/i915/display/tgl+: Use PPS index from vbt
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/10] drm/i915/bios: Allow DSI ports to be parsed by parse_ddi_port()
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "

[Intel-gfx] [PATCH v4 00/18] Begin enabling Xe_HP SDV and DG2 platforms
 2021-07-29 20:59 UTC  (21+ messages)
` [Intel-gfx] [PATCH v4 01/18] drm/i915/xehp: handle new steering options
` [Intel-gfx] [PATCH v4 02/18] drm/i915/xehpsdv: Define steering tables
` [Intel-gfx] [PATCH v4 03/18] drm/i915/dg2: Add forcewake table
` [Intel-gfx] [PATCH v4 04/18] drm/i915/dg2: Update LNCF steering ranges
` [Intel-gfx] [PATCH v4 05/18] drm/i915/dg2: Add SQIDI steering
` [Intel-gfx] [PATCH v4 06/18] drm/i915/xehp: Loop over all gslices for INSTDONE processing
` [Intel-gfx] [PATCH v4 07/18] drm/i915/dg2: Report INSTDONE_GEOM values in error state
` [Intel-gfx] [PATCH v4 08/18] drm/i915/xehp: Changes to ss/eu definitions
` [Intel-gfx] [PATCH v4 09/18] drm/i915/xehpsdv: Add maximum sseu limits
` [Intel-gfx] [PATCH v4 10/18] drm/i915/xehpsdv: Add compute DSS type
` [Intel-gfx] [PATCH v4 11/18] drm/i915/dg2: DG2 uses the same sseu limits as XeHP SDV
` [Intel-gfx] [PATCH v4 12/18] drm/i915/xehpsdv: Define MOCS table for "
` [Intel-gfx] [PATCH v4 13/18] drm/i915/dg2: Define MOCS table for DG2
` [Intel-gfx] [PATCH v4 14/18] drm/i915/xehpsdv: factor out function to read RP_STATE_CAP
` [Intel-gfx] [PATCH v4 15/18] drm/i915/xehpsdv: Read correct RP_STATE_CAP register
` [Intel-gfx] [PATCH v4 16/18] drm/i915/dg2: Add new LRI reg offsets
` [Intel-gfx] [PATCH v4 17/18] drm/i915/dg2: Maintain backward-compatible nested batch behavior
` [Intel-gfx] [PATCH v4 18/18] drm/i915/dg2: Configure PCON in DP pre-enable path
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Begin enabling Xe_HP SDV and DG2 platforms (rev8)

[Intel-gfx] [PULL] drm-misc-next
 2021-07-29 20:57 UTC 

[Intel-gfx] [PATCH 1/2] drm/i915/selftests: fixup igt_shrink_thp
 2021-07-29 20:53 UTC  (8+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915: Use Transparent Hugepages when IOMMU is enabled
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: fixup igt_shrink_thp
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✗ Fi.CI.IGT: failure "

[Intel-gfx] [PATCH v6 00/15] drm/i915: Introduce Intel PXP
 2021-07-29 20:45 UTC  (25+ messages)
` [Intel-gfx] [PATCH v6 01/15] drm/i915/pxp: Define PXP component interface
` [Intel-gfx] [PATCH v6 02/15] mei: pxp: export pavp client to me client bus
` [Intel-gfx] [PATCH v6 03/15] drm/i915/pxp: define PXP device flag and kconfig
` [Intel-gfx] [PATCH v6 04/15] drm/i915/pxp: allocate a vcs context for pxp usage
` [Intel-gfx] [PATCH v6 05/15] drm/i915/pxp: Implement funcs to create the TEE channel
` [Intel-gfx] [PATCH v6 06/15] drm/i915/pxp: set KCR reg init
` [Intel-gfx] [PATCH v6 07/15] drm/i915/pxp: Create the arbitrary session after boot
` [Intel-gfx] [PATCH v6 08/15] drm/i915/pxp: Implement arb session teardown
` [Intel-gfx] [PATCH v6 09/15] drm/i915/pxp: Implement PXP irq handler
` [Intel-gfx] [PATCH v6 10/15] drm/i915/pxp: interfaces for using protected objects
` [Intel-gfx] [PATCH v6 11/15] drm/i915/pxp: start the arb session on demand
` [Intel-gfx] [PATCH v6 12/15] drm/i915/pxp: Enable PXP power management
` [Intel-gfx] [PATCH v6 13/15] drm/i915/pxp: Add plane decryption support
` [Intel-gfx] [PATCH v6 14/15] drm/i915/pxp: black pixels on pxp disabled
` [Intel-gfx] [PATCH v6 15/15] drm/i915/pxp: enable PXP for integrated Gen12
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce Intel PXP (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH v2] drm/i915/selftests: prefer the create_user helper
 2021-07-29 19:17 UTC  (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: prefer the create_user helper (rev2)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH] drm/i915/dp: DPTX writes Swing/Pre-emphs(DPCD 0x103-0x106) requested during PHY Layer testing
 2021-07-29 16:50 UTC  (3+ messages)
` [Intel-gfx] [PATCH v2] "

[Intel-gfx] [PATCH 14/25] drm/i915/display: remove CNL ddi buf translation tables
 2021-07-29 16:23 UTC  (2+ messages)
` [Intel-gfx] [PATCH v1.1 "

[Intel-gfx] [PATCH v3 00/30] Begin enabling Xe_HP SDV and DG2 platforms
 2021-07-29 15:14 UTC  (7+ messages)
` [Intel-gfx] [PATCH v3 21/30] drm/i915/dg2: Report INSTDONE_GEOM values in error state
` [Intel-gfx] [PATCH v3 22/30] drm/i915/dg2: Define MOCS table for DG2
` [Intel-gfx] [PATCH v3 23/30] drm/i915/dg2: Add MPLLB programming for SNPS PHY

[Intel-gfx] [PATCH 0/3] drm, drm/vmwgfx: fixes and updates related to drm_master
 2021-07-29 14:45 UTC  (7+ messages)
` [Intel-gfx] [PATCH 1/3] drm: use the lookup lock in drm_is_current_master

[Intel-gfx] [PATCH 0/4] Remove CNL - for drm-intel-gt-next
 2021-07-29 11:14 UTC  (9+ messages)
` [Intel-gfx] [PATCH 1/4] drm/i915/gt: remove explicit CNL handling from intel_mocs.c
` [Intel-gfx] [PATCH 2/4] drm/i915/gt: remove explicit CNL handling from intel_sseu.c
` [Intel-gfx] [PATCH 3/4] drm/i915/gt: rename CNL references in intel_engine.h
` [Intel-gfx] [PATCH 4/4] drm/i915/gt: remove GRAPHICS_VER == 10
` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Remove CNL - for drm-intel-gt-next
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH] drm/i915/selftests: fixup igt_shrink_thp
 2021-07-29 10:55 UTC  (3+ messages)

[Intel-gfx] [PATCH rdma-next v3 0/3] SG fix together with update to RDMA umem
 2021-07-29  9:42 UTC  (5+ messages)
` [Intel-gfx] [PATCH rdma-next v3 1/3] lib/scatterlist: Provide a dedicated function to support table append
` [Intel-gfx] [PATCH rdma-next v3 2/3] lib/scatterlist: Fix wrong update of orig_nents
` [Intel-gfx] [PATCH rdma-next v3 3/3] RDMA: Use the sg_table directly and remove the opencoded version from umem
` [Intel-gfx] ✗ Fi.CI.BUILD: failure for SG fix together with update to RDMA umem (rev3)

[Intel-gfx] [PATCH i-g-t v2 01/11] lib/i915/gem_mman: add FIXED mmap mode
 2021-07-29  8:50 UTC  (9+ messages)
` [Intel-gfx] [PATCH i-g-t v2 02/11] lib/i915/gem_mman: add fixed mode to mmap__device_coherent
` [Intel-gfx] [PATCH i-g-t v2 03/11] lib/i915/gem_mman: add fixed mode to mmap__cpu_coherent
` [Intel-gfx] [PATCH i-g-t v2 04/11] lib/i915/gem_mman: add fixed mode to gem_mmap__cpu

[Intel-gfx] [PATCH i-g-t 1/7] lib/i915/gem_mman: add FIXED mmap mode
 2021-07-29  8:22 UTC  (5+ messages)
` [Intel-gfx] [igt-dev] "

[Intel-gfx] refactor the i915 GVT support
 2021-07-29  8:19 UTC  (9+ messages)

[Intel-gfx] [PATCH v3 00/14] Provide core infrastructure for managing open/release
 2021-07-29  8:16 UTC  (21+ messages)
` [Intel-gfx] [PATCH v3 01/14] vfio/samples: Remove module get/put
` [Intel-gfx] [PATCH v3 02/14] vfio/mbochs: Fix missing error unwind of mbochs_used_mbytes
` [Intel-gfx] [PATCH v3 03/14] vfio: Introduce a vfio_uninit_group_dev() API call
` [Intel-gfx] [PATCH v3 04/14] vfio: Provide better generic support for open/release vfio_device_ops
` [Intel-gfx] [PATCH v3 05/14] vfio/samples: Delete useless open/close
` [Intel-gfx] [PATCH v3 06/14] vfio/fsl: Move to the device set infrastructure
` [Intel-gfx] [PATCH v3 07/14] vfio/platform: Use open_device() instead of open coding a refcnt scheme
` [Intel-gfx] [PATCH v3 08/14] vfio/pci: Move to the device set infrastructure
` [Intel-gfx] [PATCH v3 09/14] vfio/pci: Change vfio_pci_try_bus_reset() to use the dev_set
` [Intel-gfx] [PATCH v3 10/14] vfio/pci: Reorganize VFIO_DEVICE_PCI_HOT_RESET to use the device set
` [Intel-gfx] [PATCH v3 11/14] vfio/mbochs: Fix close when multiple device FDs are open
` [Intel-gfx] [PATCH v3 12/14] vfio/ap, ccw: Fix open/close "
` [Intel-gfx] [PATCH v3 13/14] vfio/gvt: "
` [Intel-gfx] [PATCH v3 14/14] vfio: Remove struct vfio_device_ops open/release
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Provide core infrastructure for managing open/release (rev7)
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH] drm/i915: Fix the 12 BPC bits for PIPE_MISC reg
 2021-07-29  8:01 UTC  (2+ messages)

[Intel-gfx] [PATCH 0/1] Fix gem_ctx_persistence failures with GuC submission
 2021-07-29  7:30 UTC  (4+ messages)
` [Intel-gfx] [PATCH 1/1] drm/i915: Check if engine has heartbeat when closing a context
` [Intel-gfx] ✓ Fi.CI.BAT: success for Fix gem_ctx_persistence failures with GuC submission
` [Intel-gfx] ✗ Fi.CI.IGT: failure "

[Intel-gfx] [PATCH] drm/i915: Correct SFC_DONE register offset
 2021-07-29  6:45 UTC  (4+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [CI 1/2] drm/i915/adl_s: Update ddi buf translation tables
 2021-07-29  5:57 UTC  (5+ messages)
` [Intel-gfx] [CI 2/2] drm/i915/adl_p: Add ddi buf translation tables for combo PHY
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/2] drm/i915/adl_s: Update ddi buf translation tables
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH] drm/i915/selftests: prefer the create_user helper
 2021-07-29  2:14 UTC  (2+ messages)

[Intel-gfx] [PATCH] drm/i915: Disable bonding on gen12+ platforms
 2021-07-29  1:58 UTC  (2+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "


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