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[Intel-gfx] [PATCH v3 00/14] Provide core infrastructure for managing open/release
 2021-08-05 11:47 UTC  (6+ messages)
` [Intel-gfx] [PATCH v3 09/14] vfio/pci: Change vfio_pci_try_bus_reset() to use the dev_set

[Intel-gfx] [PATCH v5 00/20] drm/sched dependency handling and implicit sync fixes
 2021-08-05 10:47 UTC  (21+ messages)
` [Intel-gfx] [PATCH v5 01/20] drm/sched: Split drm_sched_job_init
` [Intel-gfx] [PATCH v5 02/20] drm/msm: Fix drm/sched point of no return rules
` [Intel-gfx] [PATCH v5 03/20] drm/sched: Barriers are needed for entity->last_scheduled
` [Intel-gfx] [PATCH v5 04/20] drm/sched: Add dependency tracking
` [Intel-gfx] [PATCH v5 05/20] drm/sched: drop entity parameter from drm_sched_push_job
` [Intel-gfx] [PATCH v5 06/20] drm/sched: improve docs around drm_sched_entity
` [Intel-gfx] [PATCH v5 07/20] drm/panfrost: use scheduler dependency tracking
` [Intel-gfx] [PATCH v5 08/20] drm/lima: "
` [Intel-gfx] [PATCH v5 09/20] drm/v3d: Move drm_sched_job_init to v3d_job_init
` [Intel-gfx] [PATCH v5 10/20] drm/v3d: Use scheduler dependency handling
` [Intel-gfx] [PATCH v5 11/20] drm/etnaviv: "
` [Intel-gfx] [PATCH v5 12/20] drm/msm: "
` [Intel-gfx] [PATCH v5 13/20] drm/gem: Delete gem array fencing helpers
` [Intel-gfx] [PATCH v5 14/20] drm/sched: Don't store self-dependencies
` [Intel-gfx] [PATCH v5 15/20] drm/sched: Check locking in drm_sched_job_await_implicit
` [Intel-gfx] [PATCH v5 16/20] drm/msm: Don't break exclusive fence ordering
` [Intel-gfx] [PATCH v5 17/20] drm/etnaviv: "
` [Intel-gfx] [PATCH v5 18/20] drm/i915: delete exclude argument from i915_sw_fence_await_reservation
` [Intel-gfx] [PATCH v5 19/20] drm/i915: Don't break exclusive fence ordering
` [Intel-gfx] [PATCH v5 20/20] dma-resv: Give the docs a do-over

[Intel-gfx] [PATCH v3 0/8] remove rcu support from i915_address_space
 2021-08-05 10:39 UTC  (9+ messages)
` [Intel-gfx] [PATCH v3 1/8] drm/i915: Drop code to handle set-vm races from execbuf
` [Intel-gfx] [PATCH v3 2/8] drm/i915: Rename i915_gem_context_get_vm_rcu to i915_gem_context_get_eb_vm
` [Intel-gfx] [PATCH v3 3/8] drm/i915: Use i915_gem_context_get_eb_vm in ctx_getparam
` [Intel-gfx] [PATCH v3 4/8] drm/i915: Add i915_gem_context_is_full_ppgtt
` [Intel-gfx] [PATCH v3 5/8] drm/i915: Use i915_gem_context_get_eb_vm in intel_context_set_gem
` [Intel-gfx] [PATCH v3 6/8] drm/i915: Drop __rcu from gem_context->vm
` [Intel-gfx] [PATCH v3 7/8] drm/i915: use xa_lock/unlock for fpriv->vm_xa lookups
` [Intel-gfx] [PATCH v3 8/8] drm/i915: Stop rcu support for i915_address_space

[Intel-gfx] [PULL] drm-misc-next
 2021-08-05 10:22 UTC 

[Intel-gfx] [PATCH] drm/i915: Update small joiner ram size
 2021-08-05 10:19 UTC 

[Intel-gfx] [PATCH] drm/i915/userptr: Probe existence of backing struct pages upon creation
 2021-08-05 10:14 UTC  (9+ messages)

[Intel-gfx] [RESEND PATCH v2 0/2] locking/lockdep, drm: apply new lockdep assert in drm_auth.c
 2021-08-05 10:08 UTC  (4+ messages)
` [Intel-gfx] [RESEND PATCH v2 2/2] drm: add lockdep assert to drm_is_current_master_locked
` [Intel-gfx] ✓ Fi.CI.IGT: success for locking/lockdep, drm: apply new lockdep assert in drm_auth.c

[Intel-gfx] [PATCH v5 00/12] i915 TTM sync accelerated migration and clear
 2021-08-05 10:05 UTC  (3+ messages)
` [Intel-gfx] [PATCH v5 07/12] drm/i915/gt: Pipelined page migration

[Intel-gfx] [PATCH 00/46] Parallel submission aka multi-bb execbuf
 2021-08-05  8:29 UTC  (54+ messages)
` [Intel-gfx] [PATCH 01/46] drm/i915/guc: Allow flexible number of context ids
` [Intel-gfx] [PATCH 02/46] drm/i915/guc: Connect the number of guc_ids to debugfs
` [Intel-gfx] [PATCH 03/46] drm/i915/guc: Don't return -EAGAIN to user when guc_ids exhausted
` [Intel-gfx] [PATCH 04/46] drm/i915/guc: Don't allow requests not ready to consume all guc_ids
` [Intel-gfx] [PATCH 05/46] drm/i915/guc: Introduce guc_submit_engine object
` [Intel-gfx] [PATCH 06/46] drm/i915/guc: Check return of __xa_store when registering a context
` [Intel-gfx] [PATCH 07/46] drm/i915/guc: Non-static lrc descriptor registration buffer
` [Intel-gfx] [PATCH 08/46] drm/i915/guc: Take GT PM ref when deregistering context
` [Intel-gfx] [PATCH 09/46] drm/i915: Add GT PM unpark worker
` [Intel-gfx] [PATCH 10/46] drm/i915/guc: Take engine PM when a context is pinned with GuC submission
` [Intel-gfx] [PATCH 11/46] drm/i915/guc: Don't call switch_to_kernel_context "
` [Intel-gfx] [PATCH 12/46] drm/i915/guc: Selftest for GuC flow control
` [Intel-gfx] [PATCH 13/46] drm/i915: Add logical engine mapping
` [Intel-gfx] [PATCH 14/46] drm/i915: Expose logical engine instance to user
` [Intel-gfx] [PATCH 15/46] drm/i915/guc: Introduce context parent-child relationship
` [Intel-gfx] [PATCH 16/46] drm/i915/guc: Implement GuC parent-child context pin / unpin functions
` [Intel-gfx] [PATCH 17/46] drm/i915/guc: Add multi-lrc context registration
` [Intel-gfx] [PATCH 18/46] drm/i915/guc: Ensure GuC schedule operations do not operate on child contexts
` [Intel-gfx] [PATCH 19/46] drm/i915/guc: Assign contexts in parent-child relationship consecutive guc_ids
` [Intel-gfx] [PATCH 20/46] drm/i915/guc: Add hang check to GuC submit engine
` [Intel-gfx] [PATCH 21/46] drm/i915/guc: Add guc_child_context_destroy
` [Intel-gfx] [PATCH 22/46] drm/i915/guc: Implement multi-lrc submission
` [Intel-gfx] [PATCH 23/46] drm/i915/guc: Insert submit fences between requests in parent-child relationship
` [Intel-gfx] [PATCH 24/46] drm/i915/guc: Implement multi-lrc reset
` [Intel-gfx] [PATCH 25/46] drm/i915/guc: Update debugfs for GuC multi-lrc
` [Intel-gfx] [PATCH 26/46] drm/i915: Connect UAPI to GuC multi-lrc interface
` [Intel-gfx] [PATCH 27/46] drm/i915/doc: Update parallel submit doc to point to i915_drm.h
` [Intel-gfx] [PATCH 28/46] drm/i915/guc: Add basic GuC multi-lrc selftest
` [Intel-gfx] [PATCH 29/46] drm/i915/guc: Extend GuC flow control selftest for multi-lrc
` [Intel-gfx] [PATCH 30/46] drm/i915/guc: Implement no mid batch preemption "
` [Intel-gfx] [PATCH 31/46] drm/i915: Move secure execbuf check to execbuf2
` [Intel-gfx] [PATCH 32/46] drm/i915: Move input/exec fence handling to i915_gem_execbuffer2
` [Intel-gfx] [PATCH 33/46] drm/i915: Move output "
` [Intel-gfx] [PATCH 34/46] drm/i915: Return output fence from i915_gem_do_execbuffer
` [Intel-gfx] [PATCH 35/46] drm/i915: Store batch index in struct i915_execbuffer
` [Intel-gfx] [PATCH 36/46] drm/i915: Allow callers of i915_gem_do_execbuffer to override the batch index
` [Intel-gfx] [PATCH 37/46] drm/i915: Teach execbuf there can be more than one batch in the objects list
` [Intel-gfx] [PATCH 38/46] drm/i915: Only track object dependencies on first request
` [Intel-gfx] [PATCH 39/46] drm/i915: Force parallel contexts to use copy engine for reloc
` [Intel-gfx] [PATCH 40/46] drm/i915: Multi-batch execbuffer2
` [Intel-gfx] [PATCH 41/46] drm/i915: Eliminate unnecessary VMA calls for multi-BB submission
` [Intel-gfx] [PATCH 42/46] drm/i915: Hold all parallel requests until last request, properly handle error
` [Intel-gfx] [PATCH 43/46] drm/i915/guc: Handle errors in multi-lrc requests
` [Intel-gfx] [PATCH 44/46] drm/i915: Enable multi-bb execbuf
` [Intel-gfx] [PATCH 45/46] drm/i915/execlists: Weak parallel submission support for execlists
` [Intel-gfx] [PATCH 46/46] drm/i915/guc: Add delay before disabling scheduling on contexts
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Parallel submission aka multi-bb execbuf (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.DOCS: "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH 1/2] drm/i915: Disable gpu relocations
 2021-08-04 22:26 UTC  (7+ messages)
` [Intel-gfx] [PATCH 2/2] drm/i915: delete gpu reloc code
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Disable gpu relocations
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH] fbdev/efifb: Release PCI device's runtime PM ref during FB destroy
 2021-08-04 22:23 UTC  (3+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "

[Intel-gfx] [PATCH -next] drm/i915: fix i915_globals_exit() section mismatch error
 2021-08-04 21:16 UTC  (3+ messages)
` [Intel-gfx] ✓ Fi.CI.BAT: success for "

[Intel-gfx] [PATCH v4 10/18] drm/i915/xehpsdv: Add compute DSS type
 2021-08-04 21:00 UTC  (3+ messages)

[Intel-gfx] [PATCH v4 00/18] Begin enabling Xe_HP SDV and DG2 platforms
 2021-08-04 20:26 UTC  (15+ messages)
` [Intel-gfx] [PATCH v4 01/18] drm/i915/xehp: handle new steering options
` [Intel-gfx] [PATCH v4 02/18] drm/i915/xehpsdv: Define steering tables
` [Intel-gfx] [PATCH v4 03/18] drm/i915/dg2: Add forcewake table
` [Intel-gfx] [PATCH v4 04/18] drm/i915/dg2: Update LNCF steering ranges
` [Intel-gfx] [PATCH v4 05/18] drm/i915/dg2: Add SQIDI steering
` [Intel-gfx] [PATCH v4 08/18] drm/i915/xehp: Changes to ss/eu definitions
` [Intel-gfx] [PATCH v4 09/18] drm/i915/xehpsdv: Add maximum sseu limits

[Intel-gfx] [PATCH 0/4] Enable GuC submission by default on DG1
 2021-08-04 19:37 UTC  (12+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] [PATCH 1/4] drm/i915: Do not define vma on stack
` [Intel-gfx] [PATCH 2/4] drm/i915/guc: put all guc objects in lmem when available
` [Intel-gfx] [PATCH 3/4] drm/i915/guc: Add DG1 GuC / HuC firmware defs
` [Intel-gfx] [PATCH 4/4] drm/i915/guc: Enable GuC submission by default on DG1
` [Intel-gfx] ✓ Fi.CI.BAT: success for "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PULL] drm-intel-fixes
 2021-08-04 18:31 UTC 

[Intel-gfx] [PULL] drm-misc-fixes
 2021-08-04 18:09 UTC 

[Intel-gfx] [PATCH] drm/i915/dp: Use max params for older panels
 2021-08-04 16:13 UTC  (3+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "

[Intel-gfx] [PATCH 0/9] remove rcu support from i915_address_space
 2021-08-04 15:10 UTC  (13+ messages)
` [Intel-gfx] [PATCH v2 1/9] drm/i915: Drop code to handle set-vm races from execbuf
` [Intel-gfx] [PATCH v2 2/9] drm/i915: Rename i915_gem_context_get_vm_rcu to i915_gem_context_get_eb_vm
` [Intel-gfx] [PATCH v2 3/9] drm/i915: Use i915_gem_context_get_eb_vm in ctx_getparam
` [Intel-gfx] [PATCH v2 4/9] drm/i915: Add i915_gem_context_is_full_ppgtt
` [Intel-gfx] [PATCH v2 5/9] drm/i915: Use i915_gem_context_get_eb_vm in intel_context_set_gem
` [Intel-gfx] [PATCH v2 6/9] drm/i915: Drop __rcu from gem_context->vm
` [Intel-gfx] [PATCH v2 7/9] drm/i915: use xa_lock/unlock for fpriv->vm_xa lookups
` [Intel-gfx] [PATCH v2 8/9] drm/i915: Stop rcu support for i915_address_space
` [Intel-gfx] [PATCH v2 9/9] drm/i915: Split out intel_context_create_user
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for remove rcu support from i915_address_space (rev3)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "

[Intel-gfx] [PATCH 0/7] drm/i915: Migrate memory to SMEM when imported cross-device
 2021-08-04 14:35 UTC  (18+ messages)
` [Intel-gfx] [PATCH 4/7] drm/i915/gem/ttm: Place new BOs in the requested region
` [Intel-gfx] [PATCH 5/7] drm/i915/gem/ttm: Respect the objection region in placement_from_obj

[Intel-gfx] refactor the i915 GVT support
 2021-08-04  5:40 UTC  (13+ messages)
` [Intel-gfx] [PATCH 01/21] drm/i915/gvt: integrate into the main Makefile

[Intel-gfx] [PATCH] drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabled
 2021-08-04  5:32 UTC  (10+ messages)
` [Intel-gfx] ✗ Fi.CI.IGT: failure for "
` [Intel-gfx] ✓ Fi.CI.BAT: success "
` [Intel-gfx] ✓ Fi.CI.IGT: "

[Intel-gfx] [PATCH i-g-t 0/3] IGT fixes for priority management + capture with GuC submission
 2021-08-04  1:23 UTC  (4+ messages)
` [Intel-gfx] [PATCH i-g-t 1/3] i915/gem_exec_schedule: Make gem_exec_schedule understand static priority mapping
` [Intel-gfx] [PATCH i-g-t 2/3] i915/gem_ctx_shared: Make gem_ctx_shared "
` [Intel-gfx] [PATCH i-g-t 3/3] i915/gem_exec_capture: Update to support GuC based resets

[Intel-gfx] [drm-intel:for-linux-next-fixes 2/2] WARNING: modpost: vmlinux.o(.text+0x12afa56): Section mismatch in reference from the function i915_globals_exit() to the function .exit.text:__i915_globals_flush()
 2021-08-03 23:21 UTC 

[Intel-gfx] [PATCH 1/7] drm/i915: Settle on "adl-x" in WA comments
 2021-08-03 22:39 UTC  (5+ messages)
` [Intel-gfx] [PATCH 6/7] drm/i915/display/adl_p: Correctly program MBUS DBOX A credits

[Intel-gfx] [drm-intel:for-linux-next-fixes 2/2] WARNING: modpost: vmlinux.o(.text.unlikely+0x105a3b): Section mismatch in reference from the function i915_globals_exit() to the function .exit.text:__i915_globals_flush()
 2021-08-03 22:17 UTC 

[Intel-gfx] [PATCH 0/8] Enable triggered perf query for Xe_HP
 2021-08-03 21:58 UTC  (13+ messages)
` [Intel-gfx] [PATCH 1/8] drm/i915/gt: Lock intel_engine_apply_whitelist with uncore->lock
` [Intel-gfx] [PATCH 2/8] drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow
` [Intel-gfx] [PATCH 3/8] drm/i915/gt: Check for conflicting RING_NONPRIV
` [Intel-gfx] [PATCH 4/8] drm/i915/gt: Enable dynamic adjustment of RING_NONPRIV
` [Intel-gfx] [PATCH 5/8] drm/i915/perf: Ensure observation logic is not clock gated
` [Intel-gfx] [PATCH 6/8] drm/i915/perf: Whitelist OA report trigger registers
` [Intel-gfx] [PATCH 7/8] drm/i915/perf: Whitelist OA counter and buffer registers
` [Intel-gfx] [PATCH 8/8] drm/i915/perf: Map OA buffer to user space for gen12 performance query
` [Intel-gfx] ✗ Fi.CI.DOCS: warning for Enable triggered perf query for Xe_HP
` [Intel-gfx] ✗ Fi.CI.BAT: failure "

[Intel-gfx] [PATCH v2 0/9] drm: Add privacy-screen class and connector properties
 2021-08-03 20:50 UTC  (3+ messages)

[Intel-gfx] [PATCH 1/4] drm/i915/display/tgl+: Dispatch atomic commits instead of front buffer modifications
 2021-08-03 17:19 UTC  (7+ messages)
` [Intel-gfx] [PATCH 3/4] drm/i915: Nuke ORIGIN_GTT
` [Intel-gfx] [PATCH 4/4] DO_NOT_MERGE: drm/i915/display: Enable PSR2 selective fetch by default

[Intel-gfx] [PATCH 0/9] remove rcu support from i915_address_space
 2021-08-03 13:09 UTC  (4+ messages)
` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for remove rcu support from i915_address_space (rev2)
` [Intel-gfx] ✗ Fi.CI.SPARSE: "
` [Intel-gfx] ✗ Fi.CI.BAT: failure "

[Intel-gfx] New uAPI for color management proposal and feedback request v2
 2021-08-03  9:38 UTC 

[Intel-gfx] [PATCH i-g-t 0/1] Fix gem_scheduler.manycontexts for GuC submission
 2021-08-03  8:54 UTC  (7+ messages)
` [Intel-gfx] [PATCH i-g-t 1/1] i915/gem_scheduler: Ensure submission order in manycontexts

[Intel-gfx] [PATCH 6/9] drm/i915: Drop __rcu from gem_context->vm
 2021-08-03  0:35 UTC  (2+ messages)

[Intel-gfx] [PATCH v2] drm/i915/display: Fix the 12 BPC bits for PIPE_MISC reg
 2021-08-02 23:13 UTC  (2+ messages)
` [Intel-gfx] ✓ Fi.CI.IGT: success for "

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