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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL3PR11MB5746.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: eed45ec1-62fc-4d9f-6220-08d96eda8b76 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Sep 2021 12:58:36.8903 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mOlMDIc+hd65jzmhdTadG4yIUui5sgkDLwf03dkc/q8aW4Ox1PQpnUwYjT2wwuU44cEUF6atrQz4/NCYfsseHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3901 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to L3_WB X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi, I see a failure reported on IGT-CI for this series for SKL, igt@gem_ctx_isolation@preservation-s3@rcs0: shard-skl: PASS -> DMESG-WARN Changes set in this series are applicable for gen12 onward platforms except= TGL/RKL. So above failure look like a false alarm to me. Regards -Ayaz > -----Original Message----- > From: Siddiqui, Ayaz A > Sent: Friday, September 3, 2021 2:52 PM > To: intel-gfx@lists.freedesktop.org > Cc: Siddiqui, Ayaz A > Subject: [PATCH V5 0/5] drm/i915/gt: Initialize unused MOCS entries to > L3_WB >=20 > Gen >=3D 12 onwards MOCS table doesn't have a setting for PTE so > I915_MOCS_PTE is not a valid index and it will have different MOCS values > are based on the platform. >=20 > To detect these kinds of misprogramming, all the unspecified and reserved > MOCS indexes are set to WB_L3. TGL/RKL unspecified MOCS indexes are > pointing to L3 UC are kept intact to avoid API break. >=20 > This series also contains patches to program BLIT_CCTL and CMD_CCTL > registers to UC. > Since we are quite late to update MOCS table for TGL so added a new MOCS > table for ADL family. >=20 > V2: > 1. Added CMD_CCTL to GUC regset list so that it can be restored > after engine reset. > 2. Checkpatch warning removal. >=20 > V3: > 1. Changed implementation to have a framework only. > 2. Added register type for proper application. > 3. moved CMD_CCTL programming to a separate patch. > 4. Added L3CC initialization during gt reset so that MOCS indexes are > set before GuC initialization. > 5. Removed Renderer check for L3CC verification in selftest. >=20 > V4: > 1. Moved register programming in Workaorund section as fake workaround. > 2. Removed seperate ADL mocs table, new logic is to set unused index as > L3_WB for gen12 platform except TGL/RKL. >=20 > V5: > 1. Final version reviewed by Matt Roper 2. Removed "drm/i915/selftest: > Remove Renderer class check for l3cc table read" form series, > this patch will be taken care of in different series. >=20 > Ayaz A Siddiqui (4): > drm/i915/gt: Add support of mocs propagation > drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward > drm/i915/gt: Set BLIT_CCTL reg to un-cached > drm/i915/gt: Initialize unused MOCS entries with device specific > values >=20 > Sreedhar Telukuntla (1): > drm/i915/gt: Initialize L3CC table in mocs init >=20 > drivers/gpu/drm/i915/gt/intel_gt.c | 2 + > drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++ > drivers/gpu/drm/i915/gt/intel_mocs.c | 72 ++++++++++++++------- > drivers/gpu/drm/i915/gt/intel_mocs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 70 > +++++++++++++++++++- > drivers/gpu/drm/i915/i915_reg.h | 26 ++++++++ > 6 files changed, 151 insertions(+), 24 deletions(-) >=20 > -- > 2.26.2