From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: Re: [PATCH 1/6] drm/i915/crt: don't set HOTPLUG bits on !PCH Date: Wed, 17 Oct 2012 18:31:10 -0300 Message-ID: References: <1349978908-7687-1-git-send-email-daniel.vetter@ffwll.ch> <1349978908-7687-2-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ie0-f177.google.com (mail-ie0-f177.google.com [209.85.223.177]) by gabe.freedesktop.org (Postfix) with ESMTP id B64DE9E832 for ; Wed, 17 Oct 2012 14:31:10 -0700 (PDT) Received: by mail-ie0-f177.google.com with SMTP id e14so13492861iej.36 for ; Wed, 17 Oct 2012 14:31:10 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org 2012/10/12 Daniel Vetter : > On Fri, Oct 12, 2012 at 7:17 PM, Paulo Zanoni wrote: >> Ok, so please do a final test: try to write something to those >> "must-be-preserved" bits and check if the values stay or not. If after >> writing 1 to bits 17-18, 20-23 you read 0, then you have my >> Reviewed-by: Paulo Zanoni . I still do plan >> to test the 6 patches of the series on hsw later btw. > > I've tested a few bits on a few machines, and some do stick and some > cause ... strange things (like a seemingly random set of other > register bits also being set). I guess that's not the answer you've > been looking for. I'd still prefer if we just try to clear things, > worst case we can easily read out the current state of these reserved > bits at boot up and restore them at resume time. But I'd really prefer > if we reduce our reliance on the boot-up state from the bios as much > as possible. And in this case here the only way to figure things out > is to merge it (it's really early for 3.8 anyway) and see what > happens. Well, ok then... Both the old and the new version don't exactly follow the spec, but I guess writing zero makes more sense than enabling random bits, especially because you said you checked and your machines actually have zeros on those bits. Reviewed-by: Paulo Zanoni > > Cheers, Daniel > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch -- Paulo Zanoni