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From: Paulo Zanoni <przanoni@gmail.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable
Date: Wed, 31 Oct 2012 15:46:52 -0200
Message-ID: <CA+gsUGTow0Sv_VvyKb4LLWOZQrLhLFmAm70BLEQ4WaD-6ddZvw@mail.gmail.com> (raw)
In-Reply-To: <1351549416-2824-4-git-send-email-daniel.vetter@ffwll.ch>

Hi

2012/10/29 Daniel Vetter <daniel.vetter@ffwll.ch>:
> Found in Bspec vol4h South Display Engine Registers [CPT, PPT],
> section "5.3.1  TRANS_CHICKEN_1—Transcoder Chicken Bits 1"
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Magic!

I wonder if we shouldn't read->change->write instead of just write,
zeroing every other bit. This comment applies to everything at
init_clock_gating, not just your patch.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 ++++
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>  2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f1fe3a0..14851ab 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3803,6 +3803,10 @@
>  #define  TRANS_6BPC             (2<<5)
>  #define  TRANS_12BPC            (3<<5)
>
> +#define _TRANSA_CHICKEN1        0xf0060
> +#define _TRANSB_CHICKEN1        0xf1060
> +#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
> +#define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE     (1<<4)
>  #define _TRANSA_CHICKEN2        0xf0064
>  #define _TRANSB_CHICKEN2        0xf1064
>  #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3469fbd..1d96c1f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3795,6 +3795,11 @@ static void cpt_init_clock_gating(struct drm_device *dev)
>         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
>         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
>                    DPLS_EDP_PPS_FIX_DIS);
> +       /* WADP0ClockGatingDisable */
> +       for_each_pipe(pipe) {
> +               I915_WRITE(TRANS_CHICKEN1(pipe),
> +                          TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> +       }
>  }
>
>  void intel_init_clock_gating(struct drm_device *dev)
> --
> 1.7.11.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

  reply index

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-10-29 22:23 [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu Daniel Vetter
2012-10-29 22:23 ` [PATCH 2/5] drm/i915: drop unnecessary check from fdi_link_train code Daniel Vetter
2012-10-31 17:27   ` Paulo Zanoni
2012-10-29 22:23 ` [PATCH 3/5] drm/i915: CPT/PPT pch dp transcoder workaround Daniel Vetter
2012-10-29 22:23 ` [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable Daniel Vetter
2012-10-31 17:46   ` Paulo Zanoni [this message]
2012-10-29 22:23 ` [PATCH 5/5] drm/i915: kill pch_init_clock_gating indirection Daniel Vetter
2012-10-31 17:52   ` Paulo Zanoni
2012-10-31 17:31 ` [PATCH 1/5] drm/i915: check whether the pch is the soulmate of the cpu Paulo Zanoni
2012-10-31 21:52 [PATCH 0/5] ivb fdi b/c fixes Daniel Vetter
2012-10-31 21:52 ` [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable Daniel Vetter
2012-11-01 16:18   ` Paulo Zanoni

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