From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: Re: [PATCH 4/5] drm/i915: implement WADP0ClockGatingDisable Date: Wed, 31 Oct 2012 15:46:52 -0200 Message-ID: References: <1351549416-2824-1-git-send-email-daniel.vetter@ffwll.ch> <1351549416-2824-4-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ie0-f177.google.com (mail-ie0-f177.google.com [209.85.223.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C9D4A09B0 for ; Wed, 31 Oct 2012 10:46:52 -0700 (PDT) Received: by mail-ie0-f177.google.com with SMTP id e14so2452006iej.36 for ; Wed, 31 Oct 2012 10:46:52 -0700 (PDT) In-Reply-To: <1351549416-2824-4-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org Hi 2012/10/29 Daniel Vetter : > Found in Bspec vol4h South Display Engine Registers [CPT, PPT], > section "5.3.1 TRANS_CHICKEN_1=97Transcoder Chicken Bits 1" > > Signed-off-by: Daniel Vetter Magic! I wonder if we shouldn't read->change->write instead of just write, zeroing every other bit. This comment applies to everything at init_clock_gating, not just your patch. Reviewed-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_pm.c | 5 +++++ > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index f1fe3a0..14851ab 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3803,6 +3803,10 @@ > #define TRANS_6BPC (2<<5) > #define TRANS_12BPC (3<<5) > > +#define _TRANSA_CHICKEN1 0xf0060 > +#define _TRANSB_CHICKEN1 0xf1060 > +#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICK= EN1) > +#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) > #define _TRANSA_CHICKEN2 0xf0064 > #define _TRANSB_CHICKEN2 0xf1064 > #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICK= EN2) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 3469fbd..1d96c1f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3795,6 +3795,11 @@ static void cpt_init_clock_gating(struct drm_devic= e *dev) > I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); > I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | > DPLS_EDP_PPS_FIX_DIS); > + /* WADP0ClockGatingDisable */ > + for_each_pipe(pipe) { > + I915_WRITE(TRANS_CHICKEN1(pipe), > + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); > + } > } > > void intel_init_clock_gating(struct drm_device *dev) > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Paulo Zanoni