* [Intel-gfx] [PATCH v2 01/10] drm/i915/xelpd: add XE_LPD display characteristics
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-05-06 19:09 ` Souza, Jose
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 02/10] drm/i915/adl_p: Add PCI Devices IDs Imre Deak
` (13 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx
From: Matt Roper <matthew.d.roper@intel.com>
Let's start preparing for upcoming platforms that will use an XE_LPD
design.
v2:
- Use the now-preferred "XE_LPD" term to refer to this design
- Utilize DISPLAY_VER() rather than a feature flag
- Drop unused mbus_size field (Lucas)
v3:
- Adjust for dbuf.{size,slice_mask} (Ville)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com> (v2)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 10 ++++++++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index f3ca5d5c97781..acf47252d9e75 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -380,6 +380,8 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915,
enum dbuf_slice {
DBUF_S1,
DBUF_S2,
+ DBUF_S3,
+ DBUF_S4,
I915_MAX_DBUF_SLICES
};
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c678e0663d808..00e15fe00f4f0 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -939,6 +939,16 @@ static const struct intel_device_info adl_s_info = {
.dma_mask_size = 46,
};
+#define XE_LPD_FEATURES \
+ .display.ver = 13, \
+ .display.has_psr_hw_tracking = 0, \
+ .abox_mask = GENMASK(1, 0), \
+ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
+ .dbuf.size = 4096, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
+
#undef GEN
#undef PLATFORM
--
2.27.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 01/10] drm/i915/xelpd: add XE_LPD display characteristics
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 01/10] drm/i915/xelpd: add XE_LPD display characteristics Imre Deak
@ 2021-05-06 19:09 ` Souza, Jose
0 siblings, 0 replies; 25+ messages in thread
From: Souza, Jose @ 2021-05-06 19:09 UTC (permalink / raw)
To: intel-gfx, Deak, Imre
On Thu, 2021-05-06 at 19:19 +0300, Imre Deak wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> Let's start preparing for upcoming platforms that will use an XE_LPD
> design.
>
> v2:
> - Use the now-preferred "XE_LPD" term to refer to this design
> - Utilize DISPLAY_VER() rather than a feature flag
> - Drop unused mbus_size field (Lucas)
> v3:
> - Adjust for dbuf.{size,slice_mask} (Ville)
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> (v2)
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 10 ++++++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index f3ca5d5c97781..acf47252d9e75 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -380,6 +380,8 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915,
> enum dbuf_slice {
> DBUF_S1,
> DBUF_S2,
> + DBUF_S3,
> + DBUF_S4,
> I915_MAX_DBUF_SLICES
> };
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index c678e0663d808..00e15fe00f4f0 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -939,6 +939,16 @@ static const struct intel_device_info adl_s_info = {
> .dma_mask_size = 46,
> };
>
> +#define XE_LPD_FEATURES \
> + .display.ver = 13, \
> + .display.has_psr_hw_tracking = 0, \
> + .abox_mask = GENMASK(1, 0), \
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
> + .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
> + .dbuf.size = 4096, \
> + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
> +
> #undef GEN
> #undef PLATFORM
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 02/10] drm/i915/adl_p: Add PCI Devices IDs
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 01/10] drm/i915/xelpd: add XE_LPD display characteristics Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 03/10] drm/i915/adl_p: ADL_P device info enabling Imre Deak
` (12 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx
From: Clinton Taylor <Clinton.A.Taylor@intel.com>
Add 18 known PCI device IDs
Bspec: 55376
Cc: Caz Yokoyama <caz.yokoyama@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
include/drm/i915_pciids.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 3be25768321d2..eee18fa53b547 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -647,4 +647,25 @@
INTEL_VGA_DEVICE(0x4692, info), \
INTEL_VGA_DEVICE(0x4693, info)
+/* ADL-P */
+#define INTEL_ADLP_IDS(info) \
+ INTEL_VGA_DEVICE(0x46A0, info), \
+ INTEL_VGA_DEVICE(0x46A1, info), \
+ INTEL_VGA_DEVICE(0x46A2, info), \
+ INTEL_VGA_DEVICE(0x46A3, info), \
+ INTEL_VGA_DEVICE(0x46A6, info), \
+ INTEL_VGA_DEVICE(0x46A8, info), \
+ INTEL_VGA_DEVICE(0x46AA, info), \
+ INTEL_VGA_DEVICE(0x462A, info), \
+ INTEL_VGA_DEVICE(0x4626, info), \
+ INTEL_VGA_DEVICE(0x4628, info), \
+ INTEL_VGA_DEVICE(0x46B0, info), \
+ INTEL_VGA_DEVICE(0x46B1, info), \
+ INTEL_VGA_DEVICE(0x46B2, info), \
+ INTEL_VGA_DEVICE(0x46B3, info), \
+ INTEL_VGA_DEVICE(0x46C0, info), \
+ INTEL_VGA_DEVICE(0x46C1, info), \
+ INTEL_VGA_DEVICE(0x46C2, info), \
+ INTEL_VGA_DEVICE(0x46C3, info)
+
#endif /* _I915_PCIIDS_H */
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* [Intel-gfx] [PATCH v2 03/10] drm/i915/adl_p: ADL_P device info enabling
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 01/10] drm/i915/xelpd: add XE_LPD display characteristics Imre Deak
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 02/10] drm/i915/adl_p: Add PCI Devices IDs Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support Imre Deak
` (11 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx
From: Clinton Taylor <Clinton.A.Taylor@intel.com>
Add ADL-P to the device_info table and support MACROS.
Bspec: 49185, 55372, 55373
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 12 ++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 1 +
5 files changed, 16 insertions(+)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6edd1e2ee8afa..b553ffe9b9851 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -552,6 +552,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
INTEL_TGL_12_IDS(&gen11_early_ops),
INTEL_RKL_IDS(&gen11_early_ops),
INTEL_ADLS_IDS(&gen11_early_ops),
+ INTEL_ADLP_IDS(&gen11_early_ops),
};
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3cfa6effbb5f1..128198e8b4d0a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1400,6 +1400,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
+#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 00e15fe00f4f0..3a1cec2ba8ca3 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -949,6 +949,17 @@ static const struct intel_device_info adl_s_info = {
.dbuf.size = 4096, \
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
+static const struct intel_device_info adl_p_info = {
+ GEN12_FEATURES,
+ XE_LPD_FEATURES,
+ PLATFORM(INTEL_ALDERLAKE_P),
+ .require_force_probe = 1,
+ .platform_engine_mask =
+ BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+ .ppgtt_size = 48,
+ .dma_mask_size = 39,
+};
+
#undef GEN
#undef PLATFORM
@@ -1026,6 +1037,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_TGL_12_IDS(&tgl_info),
INTEL_RKL_IDS(&rkl_info),
INTEL_ADLS_IDS(&adl_s_info),
+ INTEL_ADLP_IDS(&adl_p_info),
{0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6a351a7094174..3b975ce1ff591 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -67,6 +67,7 @@ static const char * const platform_names[] = {
PLATFORM_NAME(ROCKETLAKE),
PLATFORM_NAME(DG1),
PLATFORM_NAME(ALDERLAKE_S),
+ PLATFORM_NAME(ALDERLAKE_P),
};
#undef PLATFORM_NAME
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6aefe4fde197b..e98b369597367 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -87,6 +87,7 @@ enum intel_platform {
INTEL_ROCKETLAKE,
INTEL_DG1,
INTEL_ALDERLAKE_S,
+ INTEL_ALDERLAKE_P,
INTEL_MAX_PLATFORMS
};
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* [Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (2 preceding siblings ...)
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 03/10] drm/i915/adl_p: ADL_P device info enabling Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-07-28 6:50 ` Daniel Vetter
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 05/10] drm/i915/xelpd: Fallback to plane stride limitations when using DPT Imre Deak
` (10 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Wilson Chris P, Auld Matthew, Bommu Krishnaiah
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add support for DPT (display page table). DPT is a
slightly peculiar two level page table scheme used for
tiled scanout buffers (linear uses direct ggtt mapping
still). The plane surface address will point at a page
in the DPT which holds the PTEs for 512 actual pages.
Thus we require 1/512 of the ggttt address space
compared to a direct ggtt mapping.
We create a new DPT address space for each framebuffer and
track two vmas (one for the DPT, another for the ggtt).
TODO:
- Is the i915_address_space approaach sane?
- Maybe don't map the whole DPT to write the PTEs?
- Deal with remapping/rotation? Need to create a
separate DPT for each remapped/rotated plane I
guess. Or else we'd need to make the per-fb DPT
large enough to support potentially several
remapped/rotated vmas. How large should that be?
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Wilson Chris P <Chris.P.Wilson@intel.com>
Cc: Tang CQ <cq.tang@intel.com>
Cc: Auld Matthew <matthew.auld@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Wilson Chris P <Chris.P.Wilson@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 7 +-
drivers/gpu/drm/i915/display/intel_display.c | 352 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_display.h | 1 +
.../drm/i915/display/intel_display_types.h | 15 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
.../drm/i915/display/skl_universal_plane.c | 19 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 7 +
drivers/gpu/drm/i915/gt/intel_ggtt.c | 7 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 5 +
9 files changed, 392 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 7bfb26ca0bd07..36f52a1d7552f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -102,7 +102,8 @@ intel_plane_duplicate_state(struct drm_plane *plane)
__drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
- intel_state->vma = NULL;
+ intel_state->ggtt_vma = NULL;
+ intel_state->dpt_vma = NULL;
intel_state->flags = 0;
/* add reference to fb */
@@ -125,7 +126,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct intel_plane_state *plane_state = to_intel_plane_state(state);
- drm_WARN_ON(plane->dev, plane_state->vma);
+
+ drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
+ drm_WARN_ON(plane->dev, plane_state->dpt_vma);
__drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
if (plane_state->hw.fb)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5d53ee4c58f5b..99a921ea2e81b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -67,6 +67,7 @@
#include "gem/i915_gem_object.h"
#include "gt/intel_rps.h"
+#include "gt/gen8_ppgtt.h"
#include "g4x_dp.h"
#include "g4x_hdmi.h"
@@ -124,6 +125,176 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
+struct i915_dpt {
+ struct i915_address_space vm;
+
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ void __iomem *iomem;
+};
+
+#define i915_is_dpt(vm) ((vm)->is_dpt)
+
+static inline struct i915_dpt *
+i915_vm_to_dpt(struct i915_address_space *vm)
+{
+ BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
+ GEM_BUG_ON(!i915_is_dpt(vm));
+ return container_of(vm, struct i915_dpt, vm);
+}
+
+#define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
+
+static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
+{
+ writeq(pte, addr);
+}
+
+static void dpt_insert_page(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+ gen8_pte_t __iomem *base = dpt->iomem;
+
+ gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
+ vm->pte_encode(addr, level, flags));
+}
+
+static void dpt_insert_entries(struct i915_address_space *vm,
+ struct i915_vma *vma,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+ gen8_pte_t __iomem *base = dpt->iomem;
+ const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
+ struct sgt_iter sgt_iter;
+ dma_addr_t addr;
+ int i;
+
+ /*
+ * Note that we ignore PTE_READ_ONLY here. The caller must be careful
+ * not to allow the user to override access to a read only page.
+ */
+
+ i = vma->node.start / I915_GTT_PAGE_SIZE;
+ for_each_sgt_daddr(addr, sgt_iter, vma->pages)
+ gen8_set_pte(&base[i++], pte_encode | addr);
+}
+
+static void dpt_clear_range(struct i915_address_space *vm,
+ u64 start, u64 length)
+{
+}
+
+static void dpt_bind_vma(struct i915_address_space *vm,
+ struct i915_vm_pt_stash *stash,
+ struct i915_vma *vma,
+ enum i915_cache_level cache_level,
+ u32 flags)
+{
+ struct drm_i915_gem_object *obj = vma->obj;
+ u32 pte_flags;
+
+ /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
+ pte_flags = 0;
+ if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
+ pte_flags |= PTE_READ_ONLY;
+ if (i915_gem_object_is_lmem(obj))
+ pte_flags |= PTE_LM;
+
+ vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
+
+ vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
+
+ /*
+ * Without aliasing PPGTT there's no difference between
+ * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
+ * upgrade to both bound if we bind either to avoid double-binding.
+ */
+ atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
+}
+
+static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
+{
+ vm->clear_range(vm, vma->node.start, vma->size);
+}
+
+static void dpt_cleanup(struct i915_address_space *vm)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+
+ i915_gem_object_put(dpt->obj);
+}
+
+static struct i915_address_space *
+intel_dpt_create(struct drm_gem_object *obj)
+{
+ struct drm_i915_private *i915 = to_i915(obj->dev);
+ size_t size = DIV_ROUND_UP_ULL(obj->size, 512);
+ struct drm_i915_gem_object *dpt_obj;
+ struct i915_address_space *vm;
+ struct i915_dpt *dpt;
+ int ret;
+
+ size = round_up(size, 4096);
+
+ if (HAS_LMEM(i915))
+ dpt_obj = i915_gem_object_create_lmem(i915, size, 0);
+ else
+ dpt_obj = i915_gem_object_create_stolen(i915, size);
+ if (IS_ERR(dpt_obj))
+ return ERR_CAST(dpt_obj);
+
+ ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
+ if (ret) {
+ i915_gem_object_put(dpt_obj);
+ return ERR_PTR(ret);
+ }
+
+ dpt = kzalloc(sizeof(*dpt), GFP_KERNEL);
+ if (!dpt) {
+ i915_gem_object_put(dpt_obj);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ vm = &dpt->vm;
+
+ vm->gt = &i915->gt;
+ vm->i915 = i915;
+ vm->dma = i915->drm.dev;
+ vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
+ vm->is_dpt = true;
+
+ i915_address_space_init(vm, VM_CLASS_DPT);
+
+ vm->insert_page = dpt_insert_page;
+ vm->clear_range = dpt_clear_range;
+ vm->insert_entries = dpt_insert_entries;
+ vm->cleanup = dpt_cleanup;
+
+ vm->vma_ops.bind_vma = dpt_bind_vma;
+ vm->vma_ops.unbind_vma = dpt_unbind_vma;
+ vm->vma_ops.set_pages = ggtt_set_pages;
+ vm->vma_ops.clear_pages = clear_pages;
+
+ vm->pte_encode = gen8_ggtt_pte_encode;
+
+ dpt->obj = dpt_obj;
+
+ return &dpt->vm;
+}
+
+static void intel_dpt_destroy(struct i915_address_space *vm)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+
+ i915_vm_close(&dpt->vm);
+}
+
/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
@@ -974,6 +1145,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
+ if (intel_fb_uses_dpt(fb))
+ return 512 * 4096;
+
/* AUX_DIST needs only 4K alignment */
if (is_ccs_plane(fb, color_plane))
return 4096;
@@ -1027,6 +1201,62 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
}
+static struct i915_vma *
+intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
+ const struct i915_ggtt_view *view,
+ bool uses_fence,
+ unsigned long *out_flags,
+ struct i915_address_space *vm)
+{
+ struct drm_device *dev = fb->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct i915_vma *vma;
+ u32 alignment;
+ int ret;
+
+ if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
+ return ERR_PTR(-EINVAL);
+
+ alignment = 4096 * 512;
+
+ atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
+
+ ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
+ if (ret) {
+ vma = ERR_PTR(ret);
+ goto err;
+ }
+
+ vma = i915_vma_instance(obj, vm, view);
+ if (IS_ERR(vma))
+ goto err;
+
+ if (i915_vma_misplaced(vma, 0, alignment, 0)) {
+ ret = i915_vma_unbind(vma);
+ if (ret) {
+ vma = ERR_PTR(ret);
+ goto err;
+ }
+ }
+
+ ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
+ if (ret) {
+ vma = ERR_PTR(ret);
+ goto err;
+ }
+
+ vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
+
+ i915_gem_object_flush_if_display(obj);
+
+ i915_vma_get(vma);
+err:
+ atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
+
+ return vma;
+}
+
struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
bool phys_cursor,
@@ -1630,6 +1860,49 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
intel_wait_for_vblank(dev_priv, crtc->pipe);
}
+static struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
+{
+ struct drm_i915_private *i915 = vm->i915;
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+ intel_wakeref_t wakeref;
+ struct i915_vma *vma;
+ void __iomem *iomem;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+ atomic_inc(&i915->gpu_error.pending_fb_pin);
+
+ vma = i915_gem_object_ggtt_pin(dpt->obj, NULL, 0, 4096,
+ HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);
+ if (IS_ERR(vma))
+ goto err;
+
+ iomem = i915_vma_pin_iomap(vma);
+ i915_vma_unpin(vma);
+ if (IS_ERR(iomem)) {
+ vma = iomem;
+ goto err;
+ }
+
+ dpt->vma = vma;
+ dpt->iomem = iomem;
+
+ i915_vma_get(vma);
+
+err:
+ atomic_dec(&i915->gpu_error.pending_fb_pin);
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+
+ return vma;
+}
+
+static void intel_dpt_unpin(struct i915_address_space *vm)
+{
+ struct i915_dpt *dpt = i915_vm_to_dpt(vm);
+
+ i915_vma_unpin_iomap(dpt->vma);
+ i915_vma_put(dpt->vma);
+}
+
static void
intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
struct intel_initial_plane_config *plane_config)
@@ -1675,12 +1948,12 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
continue;
state = to_intel_plane_state(c->primary->state);
- if (!state->vma)
+ if (!state->ggtt_vma)
continue;
if (intel_plane_ggtt_offset(state) == plane_config->base) {
fb = state->hw.fb;
- vma = state->vma;
+ vma = state->ggtt_vma;
goto valid_fb;
}
}
@@ -1707,7 +1980,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
&intel_state->view);
__i915_vma_pin(vma);
- intel_state->vma = i915_vma_get(vma);
+ intel_state->ggtt_vma = i915_vma_get(vma);
if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
if (vma->fence)
intel_state->flags |= PLANE_HAS_FENCE;
@@ -10551,25 +10824,60 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
plane->id == PLANE_CURSOR &&
INTEL_INFO(dev_priv)->display.cursor_needs_physical;
- vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
- &plane_state->view.gtt,
- intel_plane_uses_fence(plane_state),
- &plane_state->flags);
- if (IS_ERR(vma))
- return PTR_ERR(vma);
-
- plane_state->vma = vma;
+ if (!intel_fb_uses_dpt(fb)) {
+ vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
+ &plane_state->view.gtt,
+ intel_plane_uses_fence(plane_state),
+ &plane_state->flags);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ plane_state->ggtt_vma = vma;
+ } else {
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+
+ vma = intel_dpt_pin(intel_fb->dpt_vm);
+ if (IS_ERR(vma))
+ return PTR_ERR(vma);
+
+ plane_state->ggtt_vma = vma;
+
+ vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
+ &plane_state->flags, intel_fb->dpt_vm);
+ if (IS_ERR(vma)) {
+ intel_dpt_unpin(intel_fb->dpt_vm);
+ plane_state->ggtt_vma = NULL;
+ return PTR_ERR(vma);
+ }
+
+ plane_state->dpt_vma = vma;
+
+ WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
+ }
return 0;
}
void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
{
+ struct drm_framebuffer *fb = old_plane_state->hw.fb;
struct i915_vma *vma;
- vma = fetch_and_zero(&old_plane_state->vma);
- if (vma)
- intel_unpin_fb_vma(vma, old_plane_state->flags);
+ if (!intel_fb_uses_dpt(fb)) {
+ vma = fetch_and_zero(&old_plane_state->ggtt_vma);
+ if (vma)
+ intel_unpin_fb_vma(vma, old_plane_state->flags);
+ } else {
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+
+ vma = fetch_and_zero(&old_plane_state->dpt_vma);
+ if (vma)
+ intel_unpin_fb_vma(vma, old_plane_state->flags);
+
+ vma = fetch_and_zero(&old_plane_state->ggtt_vma);
+ if (vma)
+ intel_dpt_unpin(intel_fb->dpt_vm);
+ }
}
/**
@@ -11092,6 +11400,10 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
drm_framebuffer_cleanup(fb);
+
+ if (intel_fb_uses_dpt(fb))
+ intel_dpt_destroy(intel_fb->dpt_vm);
+
intel_frontbuffer_put(intel_fb->frontbuffer);
kfree(intel_fb);
@@ -11262,6 +11574,18 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
if (ret)
goto err;
+ if (intel_fb_uses_dpt(fb)) {
+ struct i915_address_space *vm;
+
+ vm = intel_dpt_create(&obj->base);
+ if (IS_ERR(vm)) {
+ ret = PTR_ERR(vm);
+ goto err;
+ }
+
+ intel_fb->dpt_vm = vm;
+ }
+
ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
if (ret) {
drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index fc0df4c63e8de..bf12e77bcd175 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -44,6 +44,7 @@ struct drm_mode_fb_cmd2;
struct drm_modeset_acquire_ctx;
struct drm_plane;
struct drm_plane_state;
+struct i915_address_space;
struct i915_ggtt_view;
struct intel_atomic_state;
struct intel_crtc;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6d8cdaa367485..7fe96777dc671 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -128,6 +128,8 @@ struct intel_framebuffer {
struct intel_fb_view normal_view;
struct intel_fb_view rotated_view;
struct intel_fb_view remapped_view;
+
+ struct i915_address_space *dpt_vm;
};
struct intel_fbdev {
@@ -610,7 +612,8 @@ struct intel_plane_state {
enum drm_scaling_filter scaling_filter;
} hw;
- struct i915_vma *vma;
+ struct i915_vma *ggtt_vma;
+ struct i915_vma *dpt_vma;
unsigned long flags;
#define PLANE_HAS_FENCE BIT(0)
@@ -1972,9 +1975,15 @@ intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pip
intel_wait_for_vblank(dev_priv, pipe);
}
-static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
+static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
{
- return i915_ggtt_offset(state->vma);
+ return fb && DISPLAY_VER(to_i915(fb->dev)) >= 13 &&
+ fb->modifier != DRM_FORMAT_MOD_LINEAR;
+}
+
+static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
+{
+ return i915_ggtt_offset(plane_state->ggtt_vma);
}
static inline struct intel_frontbuffer *
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index b2f3ac846f5b6..1847a161cb374 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -737,11 +737,11 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
- !plane_state->vma->fence);
+ !plane_state->ggtt_vma->fence);
if (plane_state->flags & PLANE_HAS_FENCE &&
- plane_state->vma->fence)
- cache->fence_id = plane_state->vma->fence->id;
+ plane_state->ggtt_vma->fence)
+ cache->fence_id = plane_state->ggtt_vma->fence->id;
else
cache->fence_id = -1;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 0d34a5ad4e2b9..6df3e745f830d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -934,6 +934,21 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
return plane_color_ctl;
}
+static u32 skl_surf_address(const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ u32 offset = plane_state->view.color_plane[color_plane].offset;
+
+ if (intel_fb_uses_dpt(fb)) {
+ WARN_ON(offset & 0x1fffff);
+ return offset >> 9;
+ } else {
+ WARN_ON(offset & 0xfff);
+ return offset;
+ }
+}
+
static void
skl_program_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -944,7 +959,7 @@ skl_program_plane(struct intel_plane *plane,
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
- u32 surf_addr = plane_state->view.color_plane[color_plane].offset;
+ u32 surf_addr = skl_surf_address(plane_state, color_plane);
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
int aux_plane = skl_main_to_aux_plane(fb, color_plane);
@@ -983,7 +998,7 @@ skl_program_plane(struct intel_plane *plane,
}
if (aux_plane) {
- aux_dist = plane_state->view.color_plane[aux_plane].offset - surf_addr;
+ aux_dist = skl_surf_address(plane_state, aux_plane) - surf_addr;
if (DISPLAY_VER(dev_priv) < 12)
aux_dist |= skl_plane_stride(plane_state, aux_plane);
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
index 76a08b9c1f5c8..b9028c2ad3c7d 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
@@ -6,8 +6,15 @@
#ifndef __GEN8_PPGTT_H__
#define __GEN8_PPGTT_H__
+#include <linux/kernel.h>
+
+struct i915_address_space;
struct intel_gt;
+enum i915_cache_level;
struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
+u64 gen8_ggtt_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags);
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index dcb3b299cf4aa..35069ca5d7deb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -18,6 +18,7 @@
#include "i915_vgpu.h"
#include "intel_gtt.h"
+#include "gen8_ppgtt.h"
static int
i915_get_ggtt_vma_pages(struct i915_vma *vma);
@@ -187,9 +188,9 @@ static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
intel_gtt_chipset_flush();
}
-static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
- enum i915_cache_level level,
- u32 flags)
+u64 gen8_ggtt_pte_encode(dma_addr_t addr,
+ enum i915_cache_level level,
+ u32 flags)
{
gen8_pte_t pte = addr | _PAGE_PRESENT;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 44ce27c516319..ca00b45827b74 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -248,6 +248,7 @@ struct i915_address_space {
struct dma_resv resv; /* reservation lock for all pd objects, and buffer pool */
#define VM_CLASS_GGTT 0
#define VM_CLASS_PPGTT 1
+#define VM_CLASS_DPT 2
struct drm_i915_gem_object *scratch[4];
/**
@@ -258,6 +259,9 @@ struct i915_address_space {
/* Global GTT */
bool is_ggtt:1;
+ /* Display page table */
+ bool is_dpt:1;
+
/* Some systems support read-only mappings for GGTT and/or PPGTT */
bool has_read_only:1;
@@ -354,6 +358,7 @@ struct i915_ppgtt {
};
#define i915_is_ggtt(vm) ((vm)->is_ggtt)
+#define i915_is_dpt(vm) ((vm)->is_dpt)
int __must_check
i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww);
--
2.27.0
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support Imre Deak
@ 2021-07-28 6:50 ` Daniel Vetter
2021-07-28 16:41 ` Rodrigo Vivi
0 siblings, 1 reply; 25+ messages in thread
From: Daniel Vetter @ 2021-07-28 6:50 UTC (permalink / raw)
To: Imre Deak, Syrjala, Ville, Rodrigo Vivi, Nikula, Jani
Cc: Bommu Krishnaiah, intel-gfx, Auld Matthew, Wilson Chris P
On Thu, May 6, 2021 at 6:19 PM Imre Deak <imre.deak@intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add support for DPT (display page table). DPT is a
> slightly peculiar two level page table scheme used for
> tiled scanout buffers (linear uses direct ggtt mapping
> still). The plane surface address will point at a page
> in the DPT which holds the PTEs for 512 actual pages.
> Thus we require 1/512 of the ggttt address space
> compared to a direct ggtt mapping.
>
> We create a new DPT address space for each framebuffer and
> track two vmas (one for the DPT, another for the ggtt).
>
> TODO:
> - Is the i915_address_space approaach sane?
> - Maybe don't map the whole DPT to write the PTEs?
> - Deal with remapping/rotation? Need to create a
> separate DPT for each remapped/rotated plane I
> guess. Or else we'd need to make the per-fb DPT
> large enough to support potentially several
> remapped/rotated vmas. How large should that be?
I know this code predates efforts to split up intel_display.c, but
adding entirely new feature to intel_display.c like this isn't cool.
Please move this to intel_display_pt.c or something like that and give
it a reasonable interface. Minimal kerneldoc as bonus would be great
too.
I'm feeling like dim should reject any patch which has a positive
diffstat on intel_display.c until this file is in better shape. Would
be harsh, but we seem to be stuck in one step forward, one step back
mode.
-Daniel
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Wilson Chris P <Chris.P.Wilson@intel.com>
> Cc: Tang CQ <cq.tang@intel.com>
> Cc: Auld Matthew <matthew.auld@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Reviewed-by: Wilson Chris P <Chris.P.Wilson@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c | 7 +-
> drivers/gpu/drm/i915/display/intel_display.c | 352 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_display.h | 1 +
> .../drm/i915/display/intel_display_types.h | 15 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
> .../drm/i915/display/skl_universal_plane.c | 19 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 7 +
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 7 +-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 5 +
> 9 files changed, 392 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 7bfb26ca0bd07..36f52a1d7552f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -102,7 +102,8 @@ intel_plane_duplicate_state(struct drm_plane *plane)
>
> __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
>
> - intel_state->vma = NULL;
> + intel_state->ggtt_vma = NULL;
> + intel_state->dpt_vma = NULL;
> intel_state->flags = 0;
>
> /* add reference to fb */
> @@ -125,7 +126,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
> struct drm_plane_state *state)
> {
> struct intel_plane_state *plane_state = to_intel_plane_state(state);
> - drm_WARN_ON(plane->dev, plane_state->vma);
> +
> + drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
> + drm_WARN_ON(plane->dev, plane_state->dpt_vma);
>
> __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
> if (plane_state->hw.fb)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5d53ee4c58f5b..99a921ea2e81b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -67,6 +67,7 @@
> #include "gem/i915_gem_object.h"
>
> #include "gt/intel_rps.h"
> +#include "gt/gen8_ppgtt.h"
>
> #include "g4x_dp.h"
> #include "g4x_hdmi.h"
> @@ -124,6 +125,176 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
> static void intel_modeset_setup_hw_state(struct drm_device *dev,
> struct drm_modeset_acquire_ctx *ctx);
>
> +struct i915_dpt {
> + struct i915_address_space vm;
> +
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + void __iomem *iomem;
> +};
> +
> +#define i915_is_dpt(vm) ((vm)->is_dpt)
> +
> +static inline struct i915_dpt *
> +i915_vm_to_dpt(struct i915_address_space *vm)
> +{
> + BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
> + GEM_BUG_ON(!i915_is_dpt(vm));
> + return container_of(vm, struct i915_dpt, vm);
> +}
> +
> +#define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
> +
> +static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
> +{
> + writeq(pte, addr);
> +}
> +
> +static void dpt_insert_page(struct i915_address_space *vm,
> + dma_addr_t addr,
> + u64 offset,
> + enum i915_cache_level level,
> + u32 flags)
> +{
> + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> + gen8_pte_t __iomem *base = dpt->iomem;
> +
> + gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
> + vm->pte_encode(addr, level, flags));
> +}
> +
> +static void dpt_insert_entries(struct i915_address_space *vm,
> + struct i915_vma *vma,
> + enum i915_cache_level level,
> + u32 flags)
> +{
> + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> + gen8_pte_t __iomem *base = dpt->iomem;
> + const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
> + struct sgt_iter sgt_iter;
> + dma_addr_t addr;
> + int i;
> +
> + /*
> + * Note that we ignore PTE_READ_ONLY here. The caller must be careful
> + * not to allow the user to override access to a read only page.
> + */
> +
> + i = vma->node.start / I915_GTT_PAGE_SIZE;
> + for_each_sgt_daddr(addr, sgt_iter, vma->pages)
> + gen8_set_pte(&base[i++], pte_encode | addr);
> +}
> +
> +static void dpt_clear_range(struct i915_address_space *vm,
> + u64 start, u64 length)
> +{
> +}
> +
> +static void dpt_bind_vma(struct i915_address_space *vm,
> + struct i915_vm_pt_stash *stash,
> + struct i915_vma *vma,
> + enum i915_cache_level cache_level,
> + u32 flags)
> +{
> + struct drm_i915_gem_object *obj = vma->obj;
> + u32 pte_flags;
> +
> + /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
> + pte_flags = 0;
> + if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
> + pte_flags |= PTE_READ_ONLY;
> + if (i915_gem_object_is_lmem(obj))
> + pte_flags |= PTE_LM;
> +
> + vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
> +
> + vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
> +
> + /*
> + * Without aliasing PPGTT there's no difference between
> + * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
> + * upgrade to both bound if we bind either to avoid double-binding.
> + */
> + atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
> +}
> +
> +static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
> +{
> + vm->clear_range(vm, vma->node.start, vma->size);
> +}
> +
> +static void dpt_cleanup(struct i915_address_space *vm)
> +{
> + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> +
> + i915_gem_object_put(dpt->obj);
> +}
> +
> +static struct i915_address_space *
> +intel_dpt_create(struct drm_gem_object *obj)
> +{
> + struct drm_i915_private *i915 = to_i915(obj->dev);
> + size_t size = DIV_ROUND_UP_ULL(obj->size, 512);
> + struct drm_i915_gem_object *dpt_obj;
> + struct i915_address_space *vm;
> + struct i915_dpt *dpt;
> + int ret;
> +
> + size = round_up(size, 4096);
> +
> + if (HAS_LMEM(i915))
> + dpt_obj = i915_gem_object_create_lmem(i915, size, 0);
> + else
> + dpt_obj = i915_gem_object_create_stolen(i915, size);
> + if (IS_ERR(dpt_obj))
> + return ERR_CAST(dpt_obj);
> +
> + ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
> + if (ret) {
> + i915_gem_object_put(dpt_obj);
> + return ERR_PTR(ret);
> + }
> +
> + dpt = kzalloc(sizeof(*dpt), GFP_KERNEL);
> + if (!dpt) {
> + i915_gem_object_put(dpt_obj);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + vm = &dpt->vm;
> +
> + vm->gt = &i915->gt;
> + vm->i915 = i915;
> + vm->dma = i915->drm.dev;
> + vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
> + vm->is_dpt = true;
> +
> + i915_address_space_init(vm, VM_CLASS_DPT);
> +
> + vm->insert_page = dpt_insert_page;
> + vm->clear_range = dpt_clear_range;
> + vm->insert_entries = dpt_insert_entries;
> + vm->cleanup = dpt_cleanup;
> +
> + vm->vma_ops.bind_vma = dpt_bind_vma;
> + vm->vma_ops.unbind_vma = dpt_unbind_vma;
> + vm->vma_ops.set_pages = ggtt_set_pages;
> + vm->vma_ops.clear_pages = clear_pages;
> +
> + vm->pte_encode = gen8_ggtt_pte_encode;
> +
> + dpt->obj = dpt_obj;
> +
> + return &dpt->vm;
> +}
> +
> +static void intel_dpt_destroy(struct i915_address_space *vm)
> +{
> + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> +
> + i915_vm_close(&dpt->vm);
> +}
> +
> /* returns HPLL frequency in kHz */
> int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
> {
> @@ -974,6 +1145,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> {
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
>
> + if (intel_fb_uses_dpt(fb))
> + return 512 * 4096;
> +
> /* AUX_DIST needs only 4K alignment */
> if (is_ccs_plane(fb, color_plane))
> return 4096;
> @@ -1027,6 +1201,62 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
> plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
> }
>
> +static struct i915_vma *
> +intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
> + const struct i915_ggtt_view *view,
> + bool uses_fence,
> + unsigned long *out_flags,
> + struct i915_address_space *vm)
> +{
> + struct drm_device *dev = fb->dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> + struct i915_vma *vma;
> + u32 alignment;
> + int ret;
> +
> + if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
> + return ERR_PTR(-EINVAL);
> +
> + alignment = 4096 * 512;
> +
> + atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
> +
> + ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
> + if (ret) {
> + vma = ERR_PTR(ret);
> + goto err;
> + }
> +
> + vma = i915_vma_instance(obj, vm, view);
> + if (IS_ERR(vma))
> + goto err;
> +
> + if (i915_vma_misplaced(vma, 0, alignment, 0)) {
> + ret = i915_vma_unbind(vma);
> + if (ret) {
> + vma = ERR_PTR(ret);
> + goto err;
> + }
> + }
> +
> + ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
> + if (ret) {
> + vma = ERR_PTR(ret);
> + goto err;
> + }
> +
> + vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
> +
> + i915_gem_object_flush_if_display(obj);
> +
> + i915_vma_get(vma);
> +err:
> + atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
> +
> + return vma;
> +}
> +
> struct i915_vma *
> intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> bool phys_cursor,
> @@ -1630,6 +1860,49 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> intel_wait_for_vblank(dev_priv, crtc->pipe);
> }
>
> +static struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
> +{
> + struct drm_i915_private *i915 = vm->i915;
> + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> + intel_wakeref_t wakeref;
> + struct i915_vma *vma;
> + void __iomem *iomem;
> +
> + wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> + atomic_inc(&i915->gpu_error.pending_fb_pin);
> +
> + vma = i915_gem_object_ggtt_pin(dpt->obj, NULL, 0, 4096,
> + HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);
> + if (IS_ERR(vma))
> + goto err;
> +
> + iomem = i915_vma_pin_iomap(vma);
> + i915_vma_unpin(vma);
> + if (IS_ERR(iomem)) {
> + vma = iomem;
> + goto err;
> + }
> +
> + dpt->vma = vma;
> + dpt->iomem = iomem;
> +
> + i915_vma_get(vma);
> +
> +err:
> + atomic_dec(&i915->gpu_error.pending_fb_pin);
> + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> +
> + return vma;
> +}
> +
> +static void intel_dpt_unpin(struct i915_address_space *vm)
> +{
> + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> +
> + i915_vma_unpin_iomap(dpt->vma);
> + i915_vma_put(dpt->vma);
> +}
> +
> static void
> intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> struct intel_initial_plane_config *plane_config)
> @@ -1675,12 +1948,12 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> continue;
>
> state = to_intel_plane_state(c->primary->state);
> - if (!state->vma)
> + if (!state->ggtt_vma)
> continue;
>
> if (intel_plane_ggtt_offset(state) == plane_config->base) {
> fb = state->hw.fb;
> - vma = state->vma;
> + vma = state->ggtt_vma;
> goto valid_fb;
> }
> }
> @@ -1707,7 +1980,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> &intel_state->view);
>
> __i915_vma_pin(vma);
> - intel_state->vma = i915_vma_get(vma);
> + intel_state->ggtt_vma = i915_vma_get(vma);
> if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
> if (vma->fence)
> intel_state->flags |= PLANE_HAS_FENCE;
> @@ -10551,25 +10824,60 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
> plane->id == PLANE_CURSOR &&
> INTEL_INFO(dev_priv)->display.cursor_needs_physical;
>
> - vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
> - &plane_state->view.gtt,
> - intel_plane_uses_fence(plane_state),
> - &plane_state->flags);
> - if (IS_ERR(vma))
> - return PTR_ERR(vma);
> -
> - plane_state->vma = vma;
> + if (!intel_fb_uses_dpt(fb)) {
> + vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
> + &plane_state->view.gtt,
> + intel_plane_uses_fence(plane_state),
> + &plane_state->flags);
> + if (IS_ERR(vma))
> + return PTR_ERR(vma);
> +
> + plane_state->ggtt_vma = vma;
> + } else {
> + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +
> + vma = intel_dpt_pin(intel_fb->dpt_vm);
> + if (IS_ERR(vma))
> + return PTR_ERR(vma);
> +
> + plane_state->ggtt_vma = vma;
> +
> + vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
> + &plane_state->flags, intel_fb->dpt_vm);
> + if (IS_ERR(vma)) {
> + intel_dpt_unpin(intel_fb->dpt_vm);
> + plane_state->ggtt_vma = NULL;
> + return PTR_ERR(vma);
> + }
> +
> + plane_state->dpt_vma = vma;
> +
> + WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
> + }
>
> return 0;
> }
>
> void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
> {
> + struct drm_framebuffer *fb = old_plane_state->hw.fb;
> struct i915_vma *vma;
>
> - vma = fetch_and_zero(&old_plane_state->vma);
> - if (vma)
> - intel_unpin_fb_vma(vma, old_plane_state->flags);
> + if (!intel_fb_uses_dpt(fb)) {
> + vma = fetch_and_zero(&old_plane_state->ggtt_vma);
> + if (vma)
> + intel_unpin_fb_vma(vma, old_plane_state->flags);
> + } else {
> + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +
> + vma = fetch_and_zero(&old_plane_state->dpt_vma);
> + if (vma)
> + intel_unpin_fb_vma(vma, old_plane_state->flags);
> +
> + vma = fetch_and_zero(&old_plane_state->ggtt_vma);
> + if (vma)
> + intel_dpt_unpin(intel_fb->dpt_vm);
> + }
> }
>
> /**
> @@ -11092,6 +11400,10 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
> struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
>
> drm_framebuffer_cleanup(fb);
> +
> + if (intel_fb_uses_dpt(fb))
> + intel_dpt_destroy(intel_fb->dpt_vm);
> +
> intel_frontbuffer_put(intel_fb->frontbuffer);
>
> kfree(intel_fb);
> @@ -11262,6 +11574,18 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> if (ret)
> goto err;
>
> + if (intel_fb_uses_dpt(fb)) {
> + struct i915_address_space *vm;
> +
> + vm = intel_dpt_create(&obj->base);
> + if (IS_ERR(vm)) {
> + ret = PTR_ERR(vm);
> + goto err;
> + }
> +
> + intel_fb->dpt_vm = vm;
> + }
> +
> ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
> if (ret) {
> drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index fc0df4c63e8de..bf12e77bcd175 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -44,6 +44,7 @@ struct drm_mode_fb_cmd2;
> struct drm_modeset_acquire_ctx;
> struct drm_plane;
> struct drm_plane_state;
> +struct i915_address_space;
> struct i915_ggtt_view;
> struct intel_atomic_state;
> struct intel_crtc;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6d8cdaa367485..7fe96777dc671 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -128,6 +128,8 @@ struct intel_framebuffer {
> struct intel_fb_view normal_view;
> struct intel_fb_view rotated_view;
> struct intel_fb_view remapped_view;
> +
> + struct i915_address_space *dpt_vm;
> };
>
> struct intel_fbdev {
> @@ -610,7 +612,8 @@ struct intel_plane_state {
> enum drm_scaling_filter scaling_filter;
> } hw;
>
> - struct i915_vma *vma;
> + struct i915_vma *ggtt_vma;
> + struct i915_vma *dpt_vma;
> unsigned long flags;
> #define PLANE_HAS_FENCE BIT(0)
>
> @@ -1972,9 +1975,15 @@ intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pip
> intel_wait_for_vblank(dev_priv, pipe);
> }
>
> -static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
> +static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
> {
> - return i915_ggtt_offset(state->vma);
> + return fb && DISPLAY_VER(to_i915(fb->dev)) >= 13 &&
> + fb->modifier != DRM_FORMAT_MOD_LINEAR;
> +}
> +
> +static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
> +{
> + return i915_ggtt_offset(plane_state->ggtt_vma);
> }
>
> static inline struct intel_frontbuffer *
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index b2f3ac846f5b6..1847a161cb374 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -737,11 +737,11 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
>
> drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
> - !plane_state->vma->fence);
> + !plane_state->ggtt_vma->fence);
>
> if (plane_state->flags & PLANE_HAS_FENCE &&
> - plane_state->vma->fence)
> - cache->fence_id = plane_state->vma->fence->id;
> + plane_state->ggtt_vma->fence)
> + cache->fence_id = plane_state->ggtt_vma->fence->id;
> else
> cache->fence_id = -1;
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 0d34a5ad4e2b9..6df3e745f830d 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -934,6 +934,21 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> return plane_color_ctl;
> }
>
> +static u32 skl_surf_address(const struct intel_plane_state *plane_state,
> + int color_plane)
> +{
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + u32 offset = plane_state->view.color_plane[color_plane].offset;
> +
> + if (intel_fb_uses_dpt(fb)) {
> + WARN_ON(offset & 0x1fffff);
> + return offset >> 9;
> + } else {
> + WARN_ON(offset & 0xfff);
> + return offset;
> + }
> +}
> +
> static void
> skl_program_plane(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -944,7 +959,7 @@ skl_program_plane(struct intel_plane *plane,
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> - u32 surf_addr = plane_state->view.color_plane[color_plane].offset;
> + u32 surf_addr = skl_surf_address(plane_state, color_plane);
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> @@ -983,7 +998,7 @@ skl_program_plane(struct intel_plane *plane,
> }
>
> if (aux_plane) {
> - aux_dist = plane_state->view.color_plane[aux_plane].offset - surf_addr;
> + aux_dist = skl_surf_address(plane_state, aux_plane) - surf_addr;
>
> if (DISPLAY_VER(dev_priv) < 12)
> aux_dist |= skl_plane_stride(plane_state, aux_plane);
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> index 76a08b9c1f5c8..b9028c2ad3c7d 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> @@ -6,8 +6,15 @@
> #ifndef __GEN8_PPGTT_H__
> #define __GEN8_PPGTT_H__
>
> +#include <linux/kernel.h>
> +
> +struct i915_address_space;
> struct intel_gt;
> +enum i915_cache_level;
>
> struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
> +u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> + enum i915_cache_level level,
> + u32 flags);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index dcb3b299cf4aa..35069ca5d7deb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -18,6 +18,7 @@
> #include "i915_vgpu.h"
>
> #include "intel_gtt.h"
> +#include "gen8_ppgtt.h"
>
> static int
> i915_get_ggtt_vma_pages(struct i915_vma *vma);
> @@ -187,9 +188,9 @@ static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
> intel_gtt_chipset_flush();
> }
>
> -static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> - enum i915_cache_level level,
> - u32 flags)
> +u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> + enum i915_cache_level level,
> + u32 flags)
> {
> gen8_pte_t pte = addr | _PAGE_PRESENT;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 44ce27c516319..ca00b45827b74 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -248,6 +248,7 @@ struct i915_address_space {
> struct dma_resv resv; /* reservation lock for all pd objects, and buffer pool */
> #define VM_CLASS_GGTT 0
> #define VM_CLASS_PPGTT 1
> +#define VM_CLASS_DPT 2
>
> struct drm_i915_gem_object *scratch[4];
> /**
> @@ -258,6 +259,9 @@ struct i915_address_space {
> /* Global GTT */
> bool is_ggtt:1;
>
> + /* Display page table */
> + bool is_dpt:1;
> +
> /* Some systems support read-only mappings for GGTT and/or PPGTT */
> bool has_read_only:1;
>
> @@ -354,6 +358,7 @@ struct i915_ppgtt {
> };
>
> #define i915_is_ggtt(vm) ((vm)->is_ggtt)
> +#define i915_is_dpt(vm) ((vm)->is_dpt)
>
> int __must_check
> i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww);
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support
2021-07-28 6:50 ` Daniel Vetter
@ 2021-07-28 16:41 ` Rodrigo Vivi
2021-07-28 19:06 ` Daniel Vetter
0 siblings, 1 reply; 25+ messages in thread
From: Rodrigo Vivi @ 2021-07-28 16:41 UTC (permalink / raw)
To: Daniel Vetter; +Cc: Wilson Chris P, Auld Matthew, Bommu Krishnaiah, intel-gfx
On Wed, Jul 28, 2021 at 08:50:20AM +0200, Daniel Vetter wrote:
> On Thu, May 6, 2021 at 6:19 PM Imre Deak <imre.deak@intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Add support for DPT (display page table). DPT is a
> > slightly peculiar two level page table scheme used for
> > tiled scanout buffers (linear uses direct ggtt mapping
> > still). The plane surface address will point at a page
> > in the DPT which holds the PTEs for 512 actual pages.
> > Thus we require 1/512 of the ggttt address space
> > compared to a direct ggtt mapping.
> >
> > We create a new DPT address space for each framebuffer and
> > track two vmas (one for the DPT, another for the ggtt).
> >
> > TODO:
> > - Is the i915_address_space approaach sane?
> > - Maybe don't map the whole DPT to write the PTEs?
> > - Deal with remapping/rotation? Need to create a
> > separate DPT for each remapped/rotated plane I
> > guess. Or else we'd need to make the per-fb DPT
> > large enough to support potentially several
> > remapped/rotated vmas. How large should that be?
>
> I know this code predates efforts to split up intel_display.c, but
> adding entirely new feature to intel_display.c like this isn't cool.
> Please move this to intel_display_pt.c or something like that and give
> it a reasonable interface. Minimal kerneldoc as bonus would be great
> too.
>
> I'm feeling like dim should reject any patch which has a positive
> diffstat on intel_display.c until this file is in better shape. Would
> be harsh, but we seem to be stuck in one step forward, one step back
> mode.
I like this idea, although that would mean more intel-only stuff in dim
what is not good :/
> -Daniel
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > Cc: Wilson Chris P <Chris.P.Wilson@intel.com>
> > Cc: Tang CQ <cq.tang@intel.com>
> > Cc: Auld Matthew <matthew.auld@intel.com>
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > Reviewed-by: Wilson Chris P <Chris.P.Wilson@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > .../gpu/drm/i915/display/intel_atomic_plane.c | 7 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 352 +++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_display.h | 1 +
> > .../drm/i915/display/intel_display_types.h | 15 +-
> > drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
> > .../drm/i915/display/skl_universal_plane.c | 19 +-
> > drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 7 +
> > drivers/gpu/drm/i915/gt/intel_ggtt.c | 7 +-
> > drivers/gpu/drm/i915/gt/intel_gtt.h | 5 +
> > 9 files changed, 392 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > index 7bfb26ca0bd07..36f52a1d7552f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > @@ -102,7 +102,8 @@ intel_plane_duplicate_state(struct drm_plane *plane)
> >
> > __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
> >
> > - intel_state->vma = NULL;
> > + intel_state->ggtt_vma = NULL;
> > + intel_state->dpt_vma = NULL;
> > intel_state->flags = 0;
> >
> > /* add reference to fb */
> > @@ -125,7 +126,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
> > struct drm_plane_state *state)
> > {
> > struct intel_plane_state *plane_state = to_intel_plane_state(state);
> > - drm_WARN_ON(plane->dev, plane_state->vma);
> > +
> > + drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
> > + drm_WARN_ON(plane->dev, plane_state->dpt_vma);
> >
> > __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
> > if (plane_state->hw.fb)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 5d53ee4c58f5b..99a921ea2e81b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -67,6 +67,7 @@
> > #include "gem/i915_gem_object.h"
> >
> > #include "gt/intel_rps.h"
> > +#include "gt/gen8_ppgtt.h"
> >
> > #include "g4x_dp.h"
> > #include "g4x_hdmi.h"
> > @@ -124,6 +125,176 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
> > static void intel_modeset_setup_hw_state(struct drm_device *dev,
> > struct drm_modeset_acquire_ctx *ctx);
> >
> > +struct i915_dpt {
> > + struct i915_address_space vm;
> > +
> > + struct drm_i915_gem_object *obj;
> > + struct i915_vma *vma;
> > + void __iomem *iomem;
> > +};
> > +
> > +#define i915_is_dpt(vm) ((vm)->is_dpt)
> > +
> > +static inline struct i915_dpt *
> > +i915_vm_to_dpt(struct i915_address_space *vm)
> > +{
> > + BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
> > + GEM_BUG_ON(!i915_is_dpt(vm));
> > + return container_of(vm, struct i915_dpt, vm);
> > +}
> > +
> > +#define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
> > +
> > +static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
> > +{
> > + writeq(pte, addr);
> > +}
> > +
> > +static void dpt_insert_page(struct i915_address_space *vm,
> > + dma_addr_t addr,
> > + u64 offset,
> > + enum i915_cache_level level,
> > + u32 flags)
> > +{
> > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > + gen8_pte_t __iomem *base = dpt->iomem;
> > +
> > + gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
> > + vm->pte_encode(addr, level, flags));
> > +}
> > +
> > +static void dpt_insert_entries(struct i915_address_space *vm,
> > + struct i915_vma *vma,
> > + enum i915_cache_level level,
> > + u32 flags)
> > +{
> > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > + gen8_pte_t __iomem *base = dpt->iomem;
> > + const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
> > + struct sgt_iter sgt_iter;
> > + dma_addr_t addr;
> > + int i;
> > +
> > + /*
> > + * Note that we ignore PTE_READ_ONLY here. The caller must be careful
> > + * not to allow the user to override access to a read only page.
> > + */
> > +
> > + i = vma->node.start / I915_GTT_PAGE_SIZE;
> > + for_each_sgt_daddr(addr, sgt_iter, vma->pages)
> > + gen8_set_pte(&base[i++], pte_encode | addr);
> > +}
> > +
> > +static void dpt_clear_range(struct i915_address_space *vm,
> > + u64 start, u64 length)
> > +{
> > +}
> > +
> > +static void dpt_bind_vma(struct i915_address_space *vm,
> > + struct i915_vm_pt_stash *stash,
> > + struct i915_vma *vma,
> > + enum i915_cache_level cache_level,
> > + u32 flags)
> > +{
> > + struct drm_i915_gem_object *obj = vma->obj;
> > + u32 pte_flags;
> > +
> > + /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
> > + pte_flags = 0;
> > + if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
> > + pte_flags |= PTE_READ_ONLY;
> > + if (i915_gem_object_is_lmem(obj))
> > + pte_flags |= PTE_LM;
> > +
> > + vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
> > +
> > + vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
> > +
> > + /*
> > + * Without aliasing PPGTT there's no difference between
> > + * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
> > + * upgrade to both bound if we bind either to avoid double-binding.
> > + */
> > + atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
> > +}
> > +
> > +static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
> > +{
> > + vm->clear_range(vm, vma->node.start, vma->size);
> > +}
> > +
> > +static void dpt_cleanup(struct i915_address_space *vm)
> > +{
> > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > +
> > + i915_gem_object_put(dpt->obj);
> > +}
> > +
> > +static struct i915_address_space *
> > +intel_dpt_create(struct drm_gem_object *obj)
> > +{
> > + struct drm_i915_private *i915 = to_i915(obj->dev);
> > + size_t size = DIV_ROUND_UP_ULL(obj->size, 512);
> > + struct drm_i915_gem_object *dpt_obj;
> > + struct i915_address_space *vm;
> > + struct i915_dpt *dpt;
> > + int ret;
> > +
> > + size = round_up(size, 4096);
> > +
> > + if (HAS_LMEM(i915))
> > + dpt_obj = i915_gem_object_create_lmem(i915, size, 0);
> > + else
> > + dpt_obj = i915_gem_object_create_stolen(i915, size);
> > + if (IS_ERR(dpt_obj))
> > + return ERR_CAST(dpt_obj);
> > +
> > + ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
> > + if (ret) {
> > + i915_gem_object_put(dpt_obj);
> > + return ERR_PTR(ret);
> > + }
> > +
> > + dpt = kzalloc(sizeof(*dpt), GFP_KERNEL);
> > + if (!dpt) {
> > + i915_gem_object_put(dpt_obj);
> > + return ERR_PTR(-ENOMEM);
> > + }
> > +
> > + vm = &dpt->vm;
> > +
> > + vm->gt = &i915->gt;
> > + vm->i915 = i915;
> > + vm->dma = i915->drm.dev;
> > + vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
> > + vm->is_dpt = true;
> > +
> > + i915_address_space_init(vm, VM_CLASS_DPT);
> > +
> > + vm->insert_page = dpt_insert_page;
> > + vm->clear_range = dpt_clear_range;
> > + vm->insert_entries = dpt_insert_entries;
> > + vm->cleanup = dpt_cleanup;
> > +
> > + vm->vma_ops.bind_vma = dpt_bind_vma;
> > + vm->vma_ops.unbind_vma = dpt_unbind_vma;
> > + vm->vma_ops.set_pages = ggtt_set_pages;
> > + vm->vma_ops.clear_pages = clear_pages;
> > +
> > + vm->pte_encode = gen8_ggtt_pte_encode;
> > +
> > + dpt->obj = dpt_obj;
> > +
> > + return &dpt->vm;
> > +}
> > +
> > +static void intel_dpt_destroy(struct i915_address_space *vm)
> > +{
> > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > +
> > + i915_vm_close(&dpt->vm);
> > +}
> > +
> > /* returns HPLL frequency in kHz */
> > int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
> > {
> > @@ -974,6 +1145,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > {
> > struct drm_i915_private *dev_priv = to_i915(fb->dev);
> >
> > + if (intel_fb_uses_dpt(fb))
> > + return 512 * 4096;
> > +
> > /* AUX_DIST needs only 4K alignment */
> > if (is_ccs_plane(fb, color_plane))
> > return 4096;
> > @@ -1027,6 +1201,62 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
> > plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
> > }
> >
> > +static struct i915_vma *
> > +intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
> > + const struct i915_ggtt_view *view,
> > + bool uses_fence,
> > + unsigned long *out_flags,
> > + struct i915_address_space *vm)
> > +{
> > + struct drm_device *dev = fb->dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> > + struct i915_vma *vma;
> > + u32 alignment;
> > + int ret;
> > +
> > + if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
> > + return ERR_PTR(-EINVAL);
> > +
> > + alignment = 4096 * 512;
> > +
> > + atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
> > +
> > + ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
> > + if (ret) {
> > + vma = ERR_PTR(ret);
> > + goto err;
> > + }
> > +
> > + vma = i915_vma_instance(obj, vm, view);
> > + if (IS_ERR(vma))
> > + goto err;
> > +
> > + if (i915_vma_misplaced(vma, 0, alignment, 0)) {
> > + ret = i915_vma_unbind(vma);
> > + if (ret) {
> > + vma = ERR_PTR(ret);
> > + goto err;
> > + }
> > + }
> > +
> > + ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
> > + if (ret) {
> > + vma = ERR_PTR(ret);
> > + goto err;
> > + }
> > +
> > + vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
> > +
> > + i915_gem_object_flush_if_display(obj);
> > +
> > + i915_vma_get(vma);
> > +err:
> > + atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
> > +
> > + return vma;
> > +}
> > +
> > struct i915_vma *
> > intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> > bool phys_cursor,
> > @@ -1630,6 +1860,49 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> > intel_wait_for_vblank(dev_priv, crtc->pipe);
> > }
> >
> > +static struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
> > +{
> > + struct drm_i915_private *i915 = vm->i915;
> > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > + intel_wakeref_t wakeref;
> > + struct i915_vma *vma;
> > + void __iomem *iomem;
> > +
> > + wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> > + atomic_inc(&i915->gpu_error.pending_fb_pin);
> > +
> > + vma = i915_gem_object_ggtt_pin(dpt->obj, NULL, 0, 4096,
> > + HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);
> > + if (IS_ERR(vma))
> > + goto err;
> > +
> > + iomem = i915_vma_pin_iomap(vma);
> > + i915_vma_unpin(vma);
> > + if (IS_ERR(iomem)) {
> > + vma = iomem;
> > + goto err;
> > + }
> > +
> > + dpt->vma = vma;
> > + dpt->iomem = iomem;
> > +
> > + i915_vma_get(vma);
> > +
> > +err:
> > + atomic_dec(&i915->gpu_error.pending_fb_pin);
> > + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> > +
> > + return vma;
> > +}
> > +
> > +static void intel_dpt_unpin(struct i915_address_space *vm)
> > +{
> > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > +
> > + i915_vma_unpin_iomap(dpt->vma);
> > + i915_vma_put(dpt->vma);
> > +}
> > +
> > static void
> > intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > struct intel_initial_plane_config *plane_config)
> > @@ -1675,12 +1948,12 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > continue;
> >
> > state = to_intel_plane_state(c->primary->state);
> > - if (!state->vma)
> > + if (!state->ggtt_vma)
> > continue;
> >
> > if (intel_plane_ggtt_offset(state) == plane_config->base) {
> > fb = state->hw.fb;
> > - vma = state->vma;
> > + vma = state->ggtt_vma;
> > goto valid_fb;
> > }
> > }
> > @@ -1707,7 +1980,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > &intel_state->view);
> >
> > __i915_vma_pin(vma);
> > - intel_state->vma = i915_vma_get(vma);
> > + intel_state->ggtt_vma = i915_vma_get(vma);
> > if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
> > if (vma->fence)
> > intel_state->flags |= PLANE_HAS_FENCE;
> > @@ -10551,25 +10824,60 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
> > plane->id == PLANE_CURSOR &&
> > INTEL_INFO(dev_priv)->display.cursor_needs_physical;
> >
> > - vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
> > - &plane_state->view.gtt,
> > - intel_plane_uses_fence(plane_state),
> > - &plane_state->flags);
> > - if (IS_ERR(vma))
> > - return PTR_ERR(vma);
> > -
> > - plane_state->vma = vma;
> > + if (!intel_fb_uses_dpt(fb)) {
> > + vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
> > + &plane_state->view.gtt,
> > + intel_plane_uses_fence(plane_state),
> > + &plane_state->flags);
> > + if (IS_ERR(vma))
> > + return PTR_ERR(vma);
> > +
> > + plane_state->ggtt_vma = vma;
> > + } else {
> > + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > +
> > + vma = intel_dpt_pin(intel_fb->dpt_vm);
> > + if (IS_ERR(vma))
> > + return PTR_ERR(vma);
> > +
> > + plane_state->ggtt_vma = vma;
> > +
> > + vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
> > + &plane_state->flags, intel_fb->dpt_vm);
> > + if (IS_ERR(vma)) {
> > + intel_dpt_unpin(intel_fb->dpt_vm);
> > + plane_state->ggtt_vma = NULL;
> > + return PTR_ERR(vma);
> > + }
> > +
> > + plane_state->dpt_vma = vma;
> > +
> > + WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
> > + }
> >
> > return 0;
> > }
> >
> > void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
> > {
> > + struct drm_framebuffer *fb = old_plane_state->hw.fb;
> > struct i915_vma *vma;
> >
> > - vma = fetch_and_zero(&old_plane_state->vma);
> > - if (vma)
> > - intel_unpin_fb_vma(vma, old_plane_state->flags);
> > + if (!intel_fb_uses_dpt(fb)) {
> > + vma = fetch_and_zero(&old_plane_state->ggtt_vma);
> > + if (vma)
> > + intel_unpin_fb_vma(vma, old_plane_state->flags);
> > + } else {
> > + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > +
> > + vma = fetch_and_zero(&old_plane_state->dpt_vma);
> > + if (vma)
> > + intel_unpin_fb_vma(vma, old_plane_state->flags);
> > +
> > + vma = fetch_and_zero(&old_plane_state->ggtt_vma);
> > + if (vma)
> > + intel_dpt_unpin(intel_fb->dpt_vm);
> > + }
> > }
> >
> > /**
> > @@ -11092,6 +11400,10 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
> > struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> >
> > drm_framebuffer_cleanup(fb);
> > +
> > + if (intel_fb_uses_dpt(fb))
> > + intel_dpt_destroy(intel_fb->dpt_vm);
> > +
> > intel_frontbuffer_put(intel_fb->frontbuffer);
> >
> > kfree(intel_fb);
> > @@ -11262,6 +11574,18 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> > if (ret)
> > goto err;
> >
> > + if (intel_fb_uses_dpt(fb)) {
> > + struct i915_address_space *vm;
> > +
> > + vm = intel_dpt_create(&obj->base);
> > + if (IS_ERR(vm)) {
> > + ret = PTR_ERR(vm);
> > + goto err;
> > + }
> > +
> > + intel_fb->dpt_vm = vm;
> > + }
> > +
> > ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
> > if (ret) {
> > drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > index fc0df4c63e8de..bf12e77bcd175 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -44,6 +44,7 @@ struct drm_mode_fb_cmd2;
> > struct drm_modeset_acquire_ctx;
> > struct drm_plane;
> > struct drm_plane_state;
> > +struct i915_address_space;
> > struct i915_ggtt_view;
> > struct intel_atomic_state;
> > struct intel_crtc;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 6d8cdaa367485..7fe96777dc671 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -128,6 +128,8 @@ struct intel_framebuffer {
> > struct intel_fb_view normal_view;
> > struct intel_fb_view rotated_view;
> > struct intel_fb_view remapped_view;
> > +
> > + struct i915_address_space *dpt_vm;
> > };
> >
> > struct intel_fbdev {
> > @@ -610,7 +612,8 @@ struct intel_plane_state {
> > enum drm_scaling_filter scaling_filter;
> > } hw;
> >
> > - struct i915_vma *vma;
> > + struct i915_vma *ggtt_vma;
> > + struct i915_vma *dpt_vma;
> > unsigned long flags;
> > #define PLANE_HAS_FENCE BIT(0)
> >
> > @@ -1972,9 +1975,15 @@ intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pip
> > intel_wait_for_vblank(dev_priv, pipe);
> > }
> >
> > -static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
> > +static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
> > {
> > - return i915_ggtt_offset(state->vma);
> > + return fb && DISPLAY_VER(to_i915(fb->dev)) >= 13 &&
> > + fb->modifier != DRM_FORMAT_MOD_LINEAR;
> > +}
> > +
> > +static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
> > +{
> > + return i915_ggtt_offset(plane_state->ggtt_vma);
> > }
> >
> > static inline struct intel_frontbuffer *
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index b2f3ac846f5b6..1847a161cb374 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -737,11 +737,11 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> > cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
> >
> > drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
> > - !plane_state->vma->fence);
> > + !plane_state->ggtt_vma->fence);
> >
> > if (plane_state->flags & PLANE_HAS_FENCE &&
> > - plane_state->vma->fence)
> > - cache->fence_id = plane_state->vma->fence->id;
> > + plane_state->ggtt_vma->fence)
> > + cache->fence_id = plane_state->ggtt_vma->fence->id;
> > else
> > cache->fence_id = -1;
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 0d34a5ad4e2b9..6df3e745f830d 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -934,6 +934,21 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> > return plane_color_ctl;
> > }
> >
> > +static u32 skl_surf_address(const struct intel_plane_state *plane_state,
> > + int color_plane)
> > +{
> > + const struct drm_framebuffer *fb = plane_state->hw.fb;
> > + u32 offset = plane_state->view.color_plane[color_plane].offset;
> > +
> > + if (intel_fb_uses_dpt(fb)) {
> > + WARN_ON(offset & 0x1fffff);
> > + return offset >> 9;
> > + } else {
> > + WARN_ON(offset & 0xfff);
> > + return offset;
> > + }
> > +}
> > +
> > static void
> > skl_program_plane(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state,
> > @@ -944,7 +959,7 @@ skl_program_plane(struct intel_plane *plane,
> > enum plane_id plane_id = plane->id;
> > enum pipe pipe = plane->pipe;
> > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > - u32 surf_addr = plane_state->view.color_plane[color_plane].offset;
> > + u32 surf_addr = skl_surf_address(plane_state, color_plane);
> > u32 stride = skl_plane_stride(plane_state, color_plane);
> > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > @@ -983,7 +998,7 @@ skl_program_plane(struct intel_plane *plane,
> > }
> >
> > if (aux_plane) {
> > - aux_dist = plane_state->view.color_plane[aux_plane].offset - surf_addr;
> > + aux_dist = skl_surf_address(plane_state, aux_plane) - surf_addr;
> >
> > if (DISPLAY_VER(dev_priv) < 12)
> > aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > index 76a08b9c1f5c8..b9028c2ad3c7d 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > @@ -6,8 +6,15 @@
> > #ifndef __GEN8_PPGTT_H__
> > #define __GEN8_PPGTT_H__
> >
> > +#include <linux/kernel.h>
> > +
> > +struct i915_address_space;
> > struct intel_gt;
> > +enum i915_cache_level;
> >
> > struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
> > +u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> > + enum i915_cache_level level,
> > + u32 flags);
> >
> > #endif
> > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > index dcb3b299cf4aa..35069ca5d7deb 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > @@ -18,6 +18,7 @@
> > #include "i915_vgpu.h"
> >
> > #include "intel_gtt.h"
> > +#include "gen8_ppgtt.h"
> >
> > static int
> > i915_get_ggtt_vma_pages(struct i915_vma *vma);
> > @@ -187,9 +188,9 @@ static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
> > intel_gtt_chipset_flush();
> > }
> >
> > -static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> > - enum i915_cache_level level,
> > - u32 flags)
> > +u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> > + enum i915_cache_level level,
> > + u32 flags)
> > {
> > gen8_pte_t pte = addr | _PAGE_PRESENT;
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> > index 44ce27c516319..ca00b45827b74 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> > @@ -248,6 +248,7 @@ struct i915_address_space {
> > struct dma_resv resv; /* reservation lock for all pd objects, and buffer pool */
> > #define VM_CLASS_GGTT 0
> > #define VM_CLASS_PPGTT 1
> > +#define VM_CLASS_DPT 2
> >
> > struct drm_i915_gem_object *scratch[4];
> > /**
> > @@ -258,6 +259,9 @@ struct i915_address_space {
> > /* Global GTT */
> > bool is_ggtt:1;
> >
> > + /* Display page table */
> > + bool is_dpt:1;
> > +
> > /* Some systems support read-only mappings for GGTT and/or PPGTT */
> > bool has_read_only:1;
> >
> > @@ -354,6 +358,7 @@ struct i915_ppgtt {
> > };
> >
> > #define i915_is_ggtt(vm) ((vm)->is_ggtt)
> > +#define i915_is_dpt(vm) ((vm)->is_dpt)
> >
> > int __must_check
> > i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww);
> > --
> > 2.27.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support
2021-07-28 16:41 ` Rodrigo Vivi
@ 2021-07-28 19:06 ` Daniel Vetter
0 siblings, 0 replies; 25+ messages in thread
From: Daniel Vetter @ 2021-07-28 19:06 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Wilson Chris P, Auld Matthew, Bommu Krishnaiah, intel-gfx
On Wed, Jul 28, 2021 at 6:41 PM Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
>
> On Wed, Jul 28, 2021 at 08:50:20AM +0200, Daniel Vetter wrote:
> > On Thu, May 6, 2021 at 6:19 PM Imre Deak <imre.deak@intel.com> wrote:
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Add support for DPT (display page table). DPT is a
> > > slightly peculiar two level page table scheme used for
> > > tiled scanout buffers (linear uses direct ggtt mapping
> > > still). The plane surface address will point at a page
> > > in the DPT which holds the PTEs for 512 actual pages.
> > > Thus we require 1/512 of the ggttt address space
> > > compared to a direct ggtt mapping.
> > >
> > > We create a new DPT address space for each framebuffer and
> > > track two vmas (one for the DPT, another for the ggtt).
> > >
> > > TODO:
> > > - Is the i915_address_space approaach sane?
> > > - Maybe don't map the whole DPT to write the PTEs?
> > > - Deal with remapping/rotation? Need to create a
> > > separate DPT for each remapped/rotated plane I
> > > guess. Or else we'd need to make the per-fb DPT
> > > large enough to support potentially several
> > > remapped/rotated vmas. How large should that be?
> >
> > I know this code predates efforts to split up intel_display.c, but
> > adding entirely new feature to intel_display.c like this isn't cool.
> > Please move this to intel_display_pt.c or something like that and give
> > it a reasonable interface. Minimal kerneldoc as bonus would be great
> > too.
> >
> > I'm feeling like dim should reject any patch which has a positive
> > diffstat on intel_display.c until this file is in better shape. Would
> > be harsh, but we seem to be stuck in one step forward, one step back
> > mode.
>
> I like this idea, although that would mean more intel-only stuff in dim
> what is not good :/
Ok I've stumbled over this patch a 2nd time, and this time it's bad.
This wasn't properly converted over to the dma_resv_lock work from
Maarten, the intel_pin_fb_obj_dpt() function is still all copypasted
from the old style how this work. That's definitely not great at all.
Someone needs to fix this.
-Daniel
> > -Daniel
> >
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> > > Cc: Wilson Chris P <Chris.P.Wilson@intel.com>
> > > Cc: Tang CQ <cq.tang@intel.com>
> > > Cc: Auld Matthew <matthew.auld@intel.com>
> > > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> > > Reviewed-by: Wilson Chris P <Chris.P.Wilson@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > .../gpu/drm/i915/display/intel_atomic_plane.c | 7 +-
> > > drivers/gpu/drm/i915/display/intel_display.c | 352 +++++++++++++++++-
> > > drivers/gpu/drm/i915/display/intel_display.h | 1 +
> > > .../drm/i915/display/intel_display_types.h | 15 +-
> > > drivers/gpu/drm/i915/display/intel_fbc.c | 6 +-
> > > .../drm/i915/display/skl_universal_plane.c | 19 +-
> > > drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 7 +
> > > drivers/gpu/drm/i915/gt/intel_ggtt.c | 7 +-
> > > drivers/gpu/drm/i915/gt/intel_gtt.h | 5 +
> > > 9 files changed, 392 insertions(+), 27 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > index 7bfb26ca0bd07..36f52a1d7552f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> > > @@ -102,7 +102,8 @@ intel_plane_duplicate_state(struct drm_plane *plane)
> > >
> > > __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
> > >
> > > - intel_state->vma = NULL;
> > > + intel_state->ggtt_vma = NULL;
> > > + intel_state->dpt_vma = NULL;
> > > intel_state->flags = 0;
> > >
> > > /* add reference to fb */
> > > @@ -125,7 +126,9 @@ intel_plane_destroy_state(struct drm_plane *plane,
> > > struct drm_plane_state *state)
> > > {
> > > struct intel_plane_state *plane_state = to_intel_plane_state(state);
> > > - drm_WARN_ON(plane->dev, plane_state->vma);
> > > +
> > > + drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
> > > + drm_WARN_ON(plane->dev, plane_state->dpt_vma);
> > >
> > > __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
> > > if (plane_state->hw.fb)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 5d53ee4c58f5b..99a921ea2e81b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -67,6 +67,7 @@
> > > #include "gem/i915_gem_object.h"
> > >
> > > #include "gt/intel_rps.h"
> > > +#include "gt/gen8_ppgtt.h"
> > >
> > > #include "g4x_dp.h"
> > > #include "g4x_hdmi.h"
> > > @@ -124,6 +125,176 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
> > > static void intel_modeset_setup_hw_state(struct drm_device *dev,
> > > struct drm_modeset_acquire_ctx *ctx);
> > >
> > > +struct i915_dpt {
> > > + struct i915_address_space vm;
> > > +
> > > + struct drm_i915_gem_object *obj;
> > > + struct i915_vma *vma;
> > > + void __iomem *iomem;
> > > +};
> > > +
> > > +#define i915_is_dpt(vm) ((vm)->is_dpt)
> > > +
> > > +static inline struct i915_dpt *
> > > +i915_vm_to_dpt(struct i915_address_space *vm)
> > > +{
> > > + BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
> > > + GEM_BUG_ON(!i915_is_dpt(vm));
> > > + return container_of(vm, struct i915_dpt, vm);
> > > +}
> > > +
> > > +#define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
> > > +
> > > +static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
> > > +{
> > > + writeq(pte, addr);
> > > +}
> > > +
> > > +static void dpt_insert_page(struct i915_address_space *vm,
> > > + dma_addr_t addr,
> > > + u64 offset,
> > > + enum i915_cache_level level,
> > > + u32 flags)
> > > +{
> > > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > > + gen8_pte_t __iomem *base = dpt->iomem;
> > > +
> > > + gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
> > > + vm->pte_encode(addr, level, flags));
> > > +}
> > > +
> > > +static void dpt_insert_entries(struct i915_address_space *vm,
> > > + struct i915_vma *vma,
> > > + enum i915_cache_level level,
> > > + u32 flags)
> > > +{
> > > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > > + gen8_pte_t __iomem *base = dpt->iomem;
> > > + const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
> > > + struct sgt_iter sgt_iter;
> > > + dma_addr_t addr;
> > > + int i;
> > > +
> > > + /*
> > > + * Note that we ignore PTE_READ_ONLY here. The caller must be careful
> > > + * not to allow the user to override access to a read only page.
> > > + */
> > > +
> > > + i = vma->node.start / I915_GTT_PAGE_SIZE;
> > > + for_each_sgt_daddr(addr, sgt_iter, vma->pages)
> > > + gen8_set_pte(&base[i++], pte_encode | addr);
> > > +}
> > > +
> > > +static void dpt_clear_range(struct i915_address_space *vm,
> > > + u64 start, u64 length)
> > > +{
> > > +}
> > > +
> > > +static void dpt_bind_vma(struct i915_address_space *vm,
> > > + struct i915_vm_pt_stash *stash,
> > > + struct i915_vma *vma,
> > > + enum i915_cache_level cache_level,
> > > + u32 flags)
> > > +{
> > > + struct drm_i915_gem_object *obj = vma->obj;
> > > + u32 pte_flags;
> > > +
> > > + /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
> > > + pte_flags = 0;
> > > + if (vma->vm->has_read_only && i915_gem_object_is_readonly(obj))
> > > + pte_flags |= PTE_READ_ONLY;
> > > + if (i915_gem_object_is_lmem(obj))
> > > + pte_flags |= PTE_LM;
> > > +
> > > + vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
> > > +
> > > + vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
> > > +
> > > + /*
> > > + * Without aliasing PPGTT there's no difference between
> > > + * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
> > > + * upgrade to both bound if we bind either to avoid double-binding.
> > > + */
> > > + atomic_or(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND, &vma->flags);
> > > +}
> > > +
> > > +static void dpt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
> > > +{
> > > + vm->clear_range(vm, vma->node.start, vma->size);
> > > +}
> > > +
> > > +static void dpt_cleanup(struct i915_address_space *vm)
> > > +{
> > > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > > +
> > > + i915_gem_object_put(dpt->obj);
> > > +}
> > > +
> > > +static struct i915_address_space *
> > > +intel_dpt_create(struct drm_gem_object *obj)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(obj->dev);
> > > + size_t size = DIV_ROUND_UP_ULL(obj->size, 512);
> > > + struct drm_i915_gem_object *dpt_obj;
> > > + struct i915_address_space *vm;
> > > + struct i915_dpt *dpt;
> > > + int ret;
> > > +
> > > + size = round_up(size, 4096);
> > > +
> > > + if (HAS_LMEM(i915))
> > > + dpt_obj = i915_gem_object_create_lmem(i915, size, 0);
> > > + else
> > > + dpt_obj = i915_gem_object_create_stolen(i915, size);
> > > + if (IS_ERR(dpt_obj))
> > > + return ERR_CAST(dpt_obj);
> > > +
> > > + ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
> > > + if (ret) {
> > > + i915_gem_object_put(dpt_obj);
> > > + return ERR_PTR(ret);
> > > + }
> > > +
> > > + dpt = kzalloc(sizeof(*dpt), GFP_KERNEL);
> > > + if (!dpt) {
> > > + i915_gem_object_put(dpt_obj);
> > > + return ERR_PTR(-ENOMEM);
> > > + }
> > > +
> > > + vm = &dpt->vm;
> > > +
> > > + vm->gt = &i915->gt;
> > > + vm->i915 = i915;
> > > + vm->dma = i915->drm.dev;
> > > + vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
> > > + vm->is_dpt = true;
> > > +
> > > + i915_address_space_init(vm, VM_CLASS_DPT);
> > > +
> > > + vm->insert_page = dpt_insert_page;
> > > + vm->clear_range = dpt_clear_range;
> > > + vm->insert_entries = dpt_insert_entries;
> > > + vm->cleanup = dpt_cleanup;
> > > +
> > > + vm->vma_ops.bind_vma = dpt_bind_vma;
> > > + vm->vma_ops.unbind_vma = dpt_unbind_vma;
> > > + vm->vma_ops.set_pages = ggtt_set_pages;
> > > + vm->vma_ops.clear_pages = clear_pages;
> > > +
> > > + vm->pte_encode = gen8_ggtt_pte_encode;
> > > +
> > > + dpt->obj = dpt_obj;
> > > +
> > > + return &dpt->vm;
> > > +}
> > > +
> > > +static void intel_dpt_destroy(struct i915_address_space *vm)
> > > +{
> > > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > > +
> > > + i915_vm_close(&dpt->vm);
> > > +}
> > > +
> > > /* returns HPLL frequency in kHz */
> > > int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
> > > {
> > > @@ -974,6 +1145,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(fb->dev);
> > >
> > > + if (intel_fb_uses_dpt(fb))
> > > + return 512 * 4096;
> > > +
> > > /* AUX_DIST needs only 4K alignment */
> > > if (is_ccs_plane(fb, color_plane))
> > > return 4096;
> > > @@ -1027,6 +1201,62 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
> > > plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
> > > }
> > >
> > > +static struct i915_vma *
> > > +intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
> > > + const struct i915_ggtt_view *view,
> > > + bool uses_fence,
> > > + unsigned long *out_flags,
> > > + struct i915_address_space *vm)
> > > +{
> > > + struct drm_device *dev = fb->dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> > > + struct i915_vma *vma;
> > > + u32 alignment;
> > > + int ret;
> > > +
> > > + if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
> > > + return ERR_PTR(-EINVAL);
> > > +
> > > + alignment = 4096 * 512;
> > > +
> > > + atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
> > > +
> > > + ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
> > > + if (ret) {
> > > + vma = ERR_PTR(ret);
> > > + goto err;
> > > + }
> > > +
> > > + vma = i915_vma_instance(obj, vm, view);
> > > + if (IS_ERR(vma))
> > > + goto err;
> > > +
> > > + if (i915_vma_misplaced(vma, 0, alignment, 0)) {
> > > + ret = i915_vma_unbind(vma);
> > > + if (ret) {
> > > + vma = ERR_PTR(ret);
> > > + goto err;
> > > + }
> > > + }
> > > +
> > > + ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
> > > + if (ret) {
> > > + vma = ERR_PTR(ret);
> > > + goto err;
> > > + }
> > > +
> > > + vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
> > > +
> > > + i915_gem_object_flush_if_display(obj);
> > > +
> > > + i915_vma_get(vma);
> > > +err:
> > > + atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
> > > +
> > > + return vma;
> > > +}
> > > +
> > > struct i915_vma *
> > > intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> > > bool phys_cursor,
> > > @@ -1630,6 +1860,49 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> > > intel_wait_for_vblank(dev_priv, crtc->pipe);
> > > }
> > >
> > > +static struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
> > > +{
> > > + struct drm_i915_private *i915 = vm->i915;
> > > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > > + intel_wakeref_t wakeref;
> > > + struct i915_vma *vma;
> > > + void __iomem *iomem;
> > > +
> > > + wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> > > + atomic_inc(&i915->gpu_error.pending_fb_pin);
> > > +
> > > + vma = i915_gem_object_ggtt_pin(dpt->obj, NULL, 0, 4096,
> > > + HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);
> > > + if (IS_ERR(vma))
> > > + goto err;
> > > +
> > > + iomem = i915_vma_pin_iomap(vma);
> > > + i915_vma_unpin(vma);
> > > + if (IS_ERR(iomem)) {
> > > + vma = iomem;
> > > + goto err;
> > > + }
> > > +
> > > + dpt->vma = vma;
> > > + dpt->iomem = iomem;
> > > +
> > > + i915_vma_get(vma);
> > > +
> > > +err:
> > > + atomic_dec(&i915->gpu_error.pending_fb_pin);
> > > + intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> > > +
> > > + return vma;
> > > +}
> > > +
> > > +static void intel_dpt_unpin(struct i915_address_space *vm)
> > > +{
> > > + struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> > > +
> > > + i915_vma_unpin_iomap(dpt->vma);
> > > + i915_vma_put(dpt->vma);
> > > +}
> > > +
> > > static void
> > > intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > struct intel_initial_plane_config *plane_config)
> > > @@ -1675,12 +1948,12 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > continue;
> > >
> > > state = to_intel_plane_state(c->primary->state);
> > > - if (!state->vma)
> > > + if (!state->ggtt_vma)
> > > continue;
> > >
> > > if (intel_plane_ggtt_offset(state) == plane_config->base) {
> > > fb = state->hw.fb;
> > > - vma = state->vma;
> > > + vma = state->ggtt_vma;
> > > goto valid_fb;
> > > }
> > > }
> > > @@ -1707,7 +1980,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> > > &intel_state->view);
> > >
> > > __i915_vma_pin(vma);
> > > - intel_state->vma = i915_vma_get(vma);
> > > + intel_state->ggtt_vma = i915_vma_get(vma);
> > > if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
> > > if (vma->fence)
> > > intel_state->flags |= PLANE_HAS_FENCE;
> > > @@ -10551,25 +10824,60 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state)
> > > plane->id == PLANE_CURSOR &&
> > > INTEL_INFO(dev_priv)->display.cursor_needs_physical;
> > >
> > > - vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
> > > - &plane_state->view.gtt,
> > > - intel_plane_uses_fence(plane_state),
> > > - &plane_state->flags);
> > > - if (IS_ERR(vma))
> > > - return PTR_ERR(vma);
> > > -
> > > - plane_state->vma = vma;
> > > + if (!intel_fb_uses_dpt(fb)) {
> > > + vma = intel_pin_and_fence_fb_obj(fb, phys_cursor,
> > > + &plane_state->view.gtt,
> > > + intel_plane_uses_fence(plane_state),
> > > + &plane_state->flags);
> > > + if (IS_ERR(vma))
> > > + return PTR_ERR(vma);
> > > +
> > > + plane_state->ggtt_vma = vma;
> > > + } else {
> > > + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > > +
> > > + vma = intel_dpt_pin(intel_fb->dpt_vm);
> > > + if (IS_ERR(vma))
> > > + return PTR_ERR(vma);
> > > +
> > > + plane_state->ggtt_vma = vma;
> > > +
> > > + vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false,
> > > + &plane_state->flags, intel_fb->dpt_vm);
> > > + if (IS_ERR(vma)) {
> > > + intel_dpt_unpin(intel_fb->dpt_vm);
> > > + plane_state->ggtt_vma = NULL;
> > > + return PTR_ERR(vma);
> > > + }
> > > +
> > > + plane_state->dpt_vma = vma;
> > > +
> > > + WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma);
> > > + }
> > >
> > > return 0;
> > > }
> > >
> > > void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state)
> > > {
> > > + struct drm_framebuffer *fb = old_plane_state->hw.fb;
> > > struct i915_vma *vma;
> > >
> > > - vma = fetch_and_zero(&old_plane_state->vma);
> > > - if (vma)
> > > - intel_unpin_fb_vma(vma, old_plane_state->flags);
> > > + if (!intel_fb_uses_dpt(fb)) {
> > > + vma = fetch_and_zero(&old_plane_state->ggtt_vma);
> > > + if (vma)
> > > + intel_unpin_fb_vma(vma, old_plane_state->flags);
> > > + } else {
> > > + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > > +
> > > + vma = fetch_and_zero(&old_plane_state->dpt_vma);
> > > + if (vma)
> > > + intel_unpin_fb_vma(vma, old_plane_state->flags);
> > > +
> > > + vma = fetch_and_zero(&old_plane_state->ggtt_vma);
> > > + if (vma)
> > > + intel_dpt_unpin(intel_fb->dpt_vm);
> > > + }
> > > }
> > >
> > > /**
> > > @@ -11092,6 +11400,10 @@ static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
> > > struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> > >
> > > drm_framebuffer_cleanup(fb);
> > > +
> > > + if (intel_fb_uses_dpt(fb))
> > > + intel_dpt_destroy(intel_fb->dpt_vm);
> > > +
> > > intel_frontbuffer_put(intel_fb->frontbuffer);
> > >
> > > kfree(intel_fb);
> > > @@ -11262,6 +11574,18 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> > > if (ret)
> > > goto err;
> > >
> > > + if (intel_fb_uses_dpt(fb)) {
> > > + struct i915_address_space *vm;
> > > +
> > > + vm = intel_dpt_create(&obj->base);
> > > + if (IS_ERR(vm)) {
> > > + ret = PTR_ERR(vm);
> > > + goto err;
> > > + }
> > > +
> > > + intel_fb->dpt_vm = vm;
> > > + }
> > > +
> > > ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
> > > if (ret) {
> > > drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > > index fc0df4c63e8de..bf12e77bcd175 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > > @@ -44,6 +44,7 @@ struct drm_mode_fb_cmd2;
> > > struct drm_modeset_acquire_ctx;
> > > struct drm_plane;
> > > struct drm_plane_state;
> > > +struct i915_address_space;
> > > struct i915_ggtt_view;
> > > struct intel_atomic_state;
> > > struct intel_crtc;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 6d8cdaa367485..7fe96777dc671 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -128,6 +128,8 @@ struct intel_framebuffer {
> > > struct intel_fb_view normal_view;
> > > struct intel_fb_view rotated_view;
> > > struct intel_fb_view remapped_view;
> > > +
> > > + struct i915_address_space *dpt_vm;
> > > };
> > >
> > > struct intel_fbdev {
> > > @@ -610,7 +612,8 @@ struct intel_plane_state {
> > > enum drm_scaling_filter scaling_filter;
> > > } hw;
> > >
> > > - struct i915_vma *vma;
> > > + struct i915_vma *ggtt_vma;
> > > + struct i915_vma *dpt_vma;
> > > unsigned long flags;
> > > #define PLANE_HAS_FENCE BIT(0)
> > >
> > > @@ -1972,9 +1975,15 @@ intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pip
> > > intel_wait_for_vblank(dev_priv, pipe);
> > > }
> > >
> > > -static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
> > > +static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
> > > {
> > > - return i915_ggtt_offset(state->vma);
> > > + return fb && DISPLAY_VER(to_i915(fb->dev)) >= 13 &&
> > > + fb->modifier != DRM_FORMAT_MOD_LINEAR;
> > > +}
> > > +
> > > +static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
> > > +{
> > > + return i915_ggtt_offset(plane_state->ggtt_vma);
> > > }
> > >
> > > static inline struct intel_frontbuffer *
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > index b2f3ac846f5b6..1847a161cb374 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > @@ -737,11 +737,11 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> > > cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
> > >
> > > drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
> > > - !plane_state->vma->fence);
> > > + !plane_state->ggtt_vma->fence);
> > >
> > > if (plane_state->flags & PLANE_HAS_FENCE &&
> > > - plane_state->vma->fence)
> > > - cache->fence_id = plane_state->vma->fence->id;
> > > + plane_state->ggtt_vma->fence)
> > > + cache->fence_id = plane_state->ggtt_vma->fence->id;
> > > else
> > > cache->fence_id = -1;
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 0d34a5ad4e2b9..6df3e745f830d 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -934,6 +934,21 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> > > return plane_color_ctl;
> > > }
> > >
> > > +static u32 skl_surf_address(const struct intel_plane_state *plane_state,
> > > + int color_plane)
> > > +{
> > > + const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > + u32 offset = plane_state->view.color_plane[color_plane].offset;
> > > +
> > > + if (intel_fb_uses_dpt(fb)) {
> > > + WARN_ON(offset & 0x1fffff);
> > > + return offset >> 9;
> > > + } else {
> > > + WARN_ON(offset & 0xfff);
> > > + return offset;
> > > + }
> > > +}
> > > +
> > > static void
> > > skl_program_plane(struct intel_plane *plane,
> > > const struct intel_crtc_state *crtc_state,
> > > @@ -944,7 +959,7 @@ skl_program_plane(struct intel_plane *plane,
> > > enum plane_id plane_id = plane->id;
> > > enum pipe pipe = plane->pipe;
> > > const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
> > > - u32 surf_addr = plane_state->view.color_plane[color_plane].offset;
> > > + u32 surf_addr = skl_surf_address(plane_state, color_plane);
> > > u32 stride = skl_plane_stride(plane_state, color_plane);
> > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> > > @@ -983,7 +998,7 @@ skl_program_plane(struct intel_plane *plane,
> > > }
> > >
> > > if (aux_plane) {
> > > - aux_dist = plane_state->view.color_plane[aux_plane].offset - surf_addr;
> > > + aux_dist = skl_surf_address(plane_state, aux_plane) - surf_addr;
> > >
> > > if (DISPLAY_VER(dev_priv) < 12)
> > > aux_dist |= skl_plane_stride(plane_state, aux_plane);
> > > diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > > index 76a08b9c1f5c8..b9028c2ad3c7d 100644
> > > --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > > +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> > > @@ -6,8 +6,15 @@
> > > #ifndef __GEN8_PPGTT_H__
> > > #define __GEN8_PPGTT_H__
> > >
> > > +#include <linux/kernel.h>
> > > +
> > > +struct i915_address_space;
> > > struct intel_gt;
> > > +enum i915_cache_level;
> > >
> > > struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
> > > +u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> > > + enum i915_cache_level level,
> > > + u32 flags);
> > >
> > > #endif
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > index dcb3b299cf4aa..35069ca5d7deb 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> > > @@ -18,6 +18,7 @@
> > > #include "i915_vgpu.h"
> > >
> > > #include "intel_gtt.h"
> > > +#include "gen8_ppgtt.h"
> > >
> > > static int
> > > i915_get_ggtt_vma_pages(struct i915_vma *vma);
> > > @@ -187,9 +188,9 @@ static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
> > > intel_gtt_chipset_flush();
> > > }
> > >
> > > -static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> > > - enum i915_cache_level level,
> > > - u32 flags)
> > > +u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> > > + enum i915_cache_level level,
> > > + u32 flags)
> > > {
> > > gen8_pte_t pte = addr | _PAGE_PRESENT;
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> > > index 44ce27c516319..ca00b45827b74 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> > > @@ -248,6 +248,7 @@ struct i915_address_space {
> > > struct dma_resv resv; /* reservation lock for all pd objects, and buffer pool */
> > > #define VM_CLASS_GGTT 0
> > > #define VM_CLASS_PPGTT 1
> > > +#define VM_CLASS_DPT 2
> > >
> > > struct drm_i915_gem_object *scratch[4];
> > > /**
> > > @@ -258,6 +259,9 @@ struct i915_address_space {
> > > /* Global GTT */
> > > bool is_ggtt:1;
> > >
> > > + /* Display page table */
> > > + bool is_dpt:1;
> > > +
> > > /* Some systems support read-only mappings for GGTT and/or PPGTT */
> > > bool has_read_only:1;
> > >
> > > @@ -354,6 +358,7 @@ struct i915_ppgtt {
> > > };
> > >
> > > #define i915_is_ggtt(vm) ((vm)->is_ggtt)
> > > +#define i915_is_dpt(vm) ((vm)->is_dpt)
> > >
> > > int __must_check
> > > i915_vm_lock_objects(struct i915_address_space *vm, struct i915_gem_ww_ctx *ww);
> > > --
> > > 2.27.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 05/10] drm/i915/xelpd: Fallback to plane stride limitations when using DPT
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (3 preceding siblings ...)
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 06/10] drm/i915/xelpd: Support 128k plane stride Imre Deak
` (9 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
GTT remapping allow us to have planes with strides larger than HW
supports but DPT + GTT remapping is still not properly handled so
falling back to plane HW limitations for now.
This patch can be dropped when DPT + GTT remapping is correctly
handled but until then we need this limitation for all display13
platforms to avoid pipe faults.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++--------
.../gpu/drm/i915/display/intel_display_types.h | 8 ++++++--
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 99a921ea2e81b..292396058e75d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1607,14 +1607,13 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
*
* The new CCS hash mode makes remapping impossible
*/
- if (!is_ccs_modifier(modifier)) {
- if (DISPLAY_VER(dev_priv) >= 7)
- return 256*1024;
- else if (DISPLAY_VER(dev_priv) >= 4)
- return 128*1024;
- }
-
- return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+ if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
+ intel_modifier_uses_dpt(dev_priv, modifier))
+ return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+ else if (DISPLAY_VER(dev_priv) >= 7)
+ return 256 * 1024;
+ else
+ return 128 * 1024;
}
static u32
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7fe96777dc671..5f4c3e5beb2f4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1975,10 +1975,14 @@ intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pip
intel_wait_for_vblank(dev_priv, pipe);
}
+static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
+{
+ return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
+}
+
static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
{
- return fb && DISPLAY_VER(to_i915(fb->dev)) >= 13 &&
- fb->modifier != DRM_FORMAT_MOD_LINEAR;
+ return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
}
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* [Intel-gfx] [PATCH v2 06/10] drm/i915/xelpd: Support 128k plane stride
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (4 preceding siblings ...)
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 05/10] drm/i915/xelpd: Fallback to plane stride limitations when using DPT Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 07/10] drm/i915/adl_p: Add stride restriction when using DPT Imre Deak
` (8 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Juha-Pekka Heikkilä
From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
XE_LPD supports plane strides up to 128KB.
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 46 +++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 2 +
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6df3e745f830d..68a0c0a92fa1a 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -482,17 +482,35 @@ skl_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation)
{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
const struct drm_format_info *info = drm_format_info(pixel_format);
int cpp = info->cpp[0];
+ int max_horizontal_pixels = 8192;
+ int max_stride_bytes;
+
+ if (DISPLAY_VER(i915) >= 13) {
+ /*
+ * The stride in bytes must not exceed of the size
+ * of 128K bytes. For pixel formats of 64bpp will allow
+ * for a 16K pixel surface.
+ */
+ max_stride_bytes = 131072;
+ if (cpp == 8)
+ max_horizontal_pixels = 16384;
+ else
+ max_horizontal_pixels = 65536;
+ } else {
+ /*
+ * "The stride in bytes must not exceed the
+ * of the size of 8K pixels and 32K bytes."
+ */
+ max_stride_bytes = 32768;
+ }
- /*
- * "The stride in bytes must not exceed the
- * of the size of 8K pixels and 32K bytes."
- */
if (drm_rotation_90_or_270(rotation))
- return min(8192, 32768 / cpp);
+ return min(max_horizontal_pixels, max_stride_bytes / cpp);
else
- return min(8192 * cpp, 32768);
+ return min(max_horizontal_pixels * cpp, max_stride_bytes);
}
@@ -1452,7 +1470,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
}
}
- drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
+ if (DISPLAY_VER(dev_priv) >= 13)
+ drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535);
+ else
+ drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
plane_state->view.color_plane[0].offset = offset;
plane_state->view.color_plane[0].x = x;
@@ -1526,7 +1547,10 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
}
}
- drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
+ if (DISPLAY_VER(i915) >= 13)
+ drm_WARN_ON(&i915->drm, x > 65535 || y > 65535);
+ else
+ drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
plane_state->view.color_plane[uv_plane].offset = offset;
plane_state->view.color_plane[uv_plane].x = x;
@@ -2239,7 +2263,11 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
- fb->pitches[0] = (val & 0x3ff) * stride_mult;
+
+ if (DISPLAY_VER(dev_priv) >= 13)
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
+ else
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ffd173f8b7f9..846fa927a3d83 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7212,6 +7212,8 @@ enum {
_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
+#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
+#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* [Intel-gfx] [PATCH v2 07/10] drm/i915/adl_p: Add stride restriction when using DPT
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (5 preceding siblings ...)
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 06/10] drm/i915/xelpd: Support 128k plane stride Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-05-06 21:03 ` Clint Taylor
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 08/10] drm/i915/adl_p: Disable support for 90/270 FB rotation Imre Deak
` (7 subsequent siblings)
14 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx
From: José Roberto de Souza <jose.souza@intel.com>
Alderlake-P have a new stride restriction when using DPT and it is used
by non linear framebuffers. Stride needs to be a power of two to take
full DPT rows, but stride is a parameter set by userspace.
What we could do is use a fake stride when doing DPT allocation so
HW requirements are met and userspace don't need to be changed to
met this power of two restrictions but this change will take a while
to be implemented so for now adding this restriction in driver to
reject atomic commits that would cause visual corruptions.
BSpec: 53393
Acked-by: Matt Roper <matthew.d.roper@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 292396058e75d..70ac197746b1f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11566,6 +11566,15 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
}
}
+ if (IS_ALDERLAKE_P(dev_priv) &&
+ mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
+ !is_power_of_2(mode_cmd->pitches[i])) {
+ drm_dbg_kms(&dev_priv->drm,
+ "plane %d pitch (%d) must be power of two for tiled buffers\n",
+ i, mode_cmd->pitches[i]);
+ goto err;
+ }
+
fb->obj[i] = &obj->base;
}
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [Intel-gfx] [PATCH v2 07/10] drm/i915/adl_p: Add stride restriction when using DPT
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 07/10] drm/i915/adl_p: Add stride restriction when using DPT Imre Deak
@ 2021-05-06 21:03 ` Clint Taylor
0 siblings, 0 replies; 25+ messages in thread
From: Clint Taylor @ 2021-05-06 21:03 UTC (permalink / raw)
To: intel-gfx
On 5/6/21 9:19 AM, Imre Deak wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> Alderlake-P have a new stride restriction when using DPT and it is used
> by non linear framebuffers. Stride needs to be a power of two to take
> full DPT rows, but stride is a parameter set by userspace.
>
> What we could do is use a fake stride when doing DPT allocation so
> HW requirements are met and userspace don't need to be changed to
> met this power of two restrictions but this change will take a while
> to be implemented so for now adding this restriction in driver to
> reject atomic commits that would cause visual corruptions.
>
> BSpec: 53393
> Acked-by: Matt Roper <matthew.d.roper@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 292396058e75d..70ac197746b1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11566,6 +11566,15 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> }
> }
>
> + if (IS_ALDERLAKE_P(dev_priv) &&
> + mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
> + !is_power_of_2(mode_cmd->pitches[i])) {
> + drm_dbg_kms(&dev_priv->drm,
> + "plane %d pitch (%d) must be power of two for tiled buffers\n",
> + i, mode_cmd->pitches[i]);
> + goto err;
> + }
> +
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
> fb->obj[i] = &obj->base;
> }
>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 08/10] drm/i915/adl_p: Disable support for 90/270 FB rotation
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (6 preceding siblings ...)
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 07/10] drm/i915/adl_p: Add stride restriction when using DPT Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 09/10] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs Imre Deak
` (6 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx
The latest specification removed the support for 90/270 FB rotation on
ADL_P, even though legacy Y-tiled surfaces are supported. Align the code
accordingly.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_types.h | 6 +++--
drivers/gpu/drm/i915/display/intel_fb.c | 24 +++++++++++++++----
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c | 3 +--
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5f4c3e5beb2f4..9c0adfc60c6fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -126,8 +126,10 @@ struct intel_framebuffer {
/* Params to remap the FB pages and program the plane registers in each view. */
struct intel_fb_view normal_view;
- struct intel_fb_view rotated_view;
- struct intel_fb_view remapped_view;
+ union {
+ struct intel_fb_view rotated_view;
+ struct intel_fb_view remapped_view;
+ };
struct i915_address_space *dpt_vm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 21271a6976f14..927440ed14f48 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -735,6 +735,15 @@ static void intel_fb_view_init(struct intel_fb_view *view, enum i915_ggtt_view_t
view->gtt.type = view_type;
}
+bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb)
+{
+ if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13)
+ return false;
+
+ return fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
+ fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;
+}
+
int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb)
{
struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
@@ -745,8 +754,15 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *
unsigned int tile_size = intel_tile_size(i915);
intel_fb_view_init(&fb->normal_view, I915_GGTT_VIEW_NORMAL);
- intel_fb_view_init(&fb->rotated_view, I915_GGTT_VIEW_ROTATED);
- intel_fb_view_init(&fb->remapped_view, I915_GGTT_VIEW_REMAPPED);
+
+ drm_WARN_ON(&i915->drm,
+ intel_fb_supports_90_270_rotation(fb) &&
+ intel_fb_needs_pot_stride_remap(fb));
+
+ if (intel_fb_supports_90_270_rotation(fb))
+ intel_fb_view_init(&fb->rotated_view, I915_GGTT_VIEW_ROTATED);
+ if (intel_fb_needs_pot_stride_remap(fb))
+ intel_fb_view_init(&fb->remapped_view, I915_GGTT_VIEW_REMAPPED);
for (i = 0; i < num_planes; i++) {
struct fb_plane_view_dims view_dims;
@@ -787,9 +803,7 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *
offset = calc_plane_aligned_offset(fb, i, &x, &y);
- /* Y or Yf modifiers required for 90/270 rotation */
- if (fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
- fb->base.modifier == I915_FORMAT_MOD_Yf_TILED)
+ if (intel_fb_supports_90_270_rotation(fb))
gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims,
offset, gtt_offset_rotated, x, y,
&fb->rotated_view);
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 7cec77bb5046a..d77d9f914cf4c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -45,6 +45,8 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y,
const struct intel_plane_state *state,
int color_plane);
+bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb);
+
int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb);
void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation,
struct intel_fb_view *view);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 68a0c0a92fa1a..86730f3912b22 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1161,8 +1161,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
}
if (drm_rotation_90_or_270(rotation)) {
- if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
- fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
+ if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) {
drm_dbg_kms(&dev_priv->drm,
"Y/Yf tiling required for 90/270!\n");
return -EINVAL;
--
2.27.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* [Intel-gfx] [PATCH v2 09/10] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (7 preceding siblings ...)
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 08/10] drm/i915/adl_p: Disable support for 90/270 FB rotation Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 10/10] drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT Imre Deak
` (5 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx
The specification only requires DPT FB strides to be POT aligned, but
there seems to be also a minimum of 8 stride tile requirement. Scanning
out FBs with < 8 stride tiles will result in pipe faults (even though
the stride is POT aligned).
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 927440ed14f48..29c558fbb397a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -601,7 +601,11 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
unsigned int pitch_tiles)
{
if (intel_fb_needs_pot_stride_remap(fb))
- return roundup_pow_of_two(pitch_tiles);
+ /*
+ * ADL_P, the only platform needing a POT stride has a minimum
+ * of 8 stride tiles.
+ */
+ return roundup_pow_of_two(max(pitch_tiles, 8u));
else
return pitch_tiles;
}
--
2.27.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* [Intel-gfx] [PATCH v2 10/10] drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (8 preceding siblings ...)
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 09/10] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs Imre Deak
@ 2021-05-06 16:19 ` Imre Deak
2021-05-06 16:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adl_p: Add support for Display Page Tables (rev2) Patchwork
` (4 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2021-05-06 16:19 UTC (permalink / raw)
To: intel-gfx
Enable padding of DPT FB strides to POT, using the FB remapping logic.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++----
drivers/gpu/drm/i915/display/intel_fb.c | 7 +++++--
drivers/gpu/drm/i915/display/intel_fb.h | 1 +
3 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 70ac197746b1f..ff0cfdf1a90ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -231,16 +231,22 @@ static void dpt_cleanup(struct i915_address_space *vm)
}
static struct i915_address_space *
-intel_dpt_create(struct drm_gem_object *obj)
+intel_dpt_create(struct intel_framebuffer *fb)
{
+ struct drm_gem_object *obj = &intel_fb_obj(&fb->base)->base;
struct drm_i915_private *i915 = to_i915(obj->dev);
- size_t size = DIV_ROUND_UP_ULL(obj->size, 512);
struct drm_i915_gem_object *dpt_obj;
struct i915_address_space *vm;
struct i915_dpt *dpt;
+ size_t size;
int ret;
- size = round_up(size, 4096);
+ if (intel_fb_needs_pot_stride_remap(fb))
+ size = intel_remapped_info_size(&fb->remapped_view.gtt.remapped);
+ else
+ size = DIV_ROUND_UP_ULL(obj->size, I915_GTT_PAGE_SIZE);
+
+ size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE);
if (HAS_LMEM(i915))
dpt_obj = i915_gem_object_create_lmem(i915, size, 0);
@@ -11566,8 +11572,10 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
}
}
+ /* TODO: Add POT stride remapping support for CCS formats as well. */
if (IS_ALDERLAKE_P(dev_priv) &&
mode_cmd->modifier[i] != DRM_FORMAT_MOD_LINEAR &&
+ !intel_fb_needs_pot_stride_remap(intel_fb) &&
!is_power_of_2(mode_cmd->pitches[i])) {
drm_dbg_kms(&dev_priv->drm,
"plane %d pitch (%d) must be power of two for tiled buffers\n",
@@ -11585,7 +11593,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
if (intel_fb_uses_dpt(fb)) {
struct i915_address_space *vm;
- vm = intel_dpt_create(&obj->base);
+ vm = intel_dpt_create(intel_fb);
if (IS_ERR(vm)) {
ret = PTR_ERR(vm);
goto err;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 29c558fbb397a..a005c68889e7c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -478,9 +478,12 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
return true;
}
-static bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
+bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
{
- return false;
+ struct drm_i915_private *i915 = to_i915(fb->base.dev);
+
+ return IS_ALDERLAKE_P(i915) && fb->base.modifier != DRM_FORMAT_MOD_LINEAR &&
+ !is_ccs_modifier(fb->base.modifier);
}
static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index d77d9f914cf4c..739d1b91754bd 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -45,6 +45,7 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y,
const struct intel_plane_state *state,
int color_plane);
+bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb);
bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb);
int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb);
--
2.27.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adl_p: Add support for Display Page Tables (rev2)
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (9 preceding siblings ...)
2021-05-06 16:19 ` [Intel-gfx] [PATCH v2 10/10] drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT Imre Deak
@ 2021-05-06 16:32 ` Patchwork
2021-05-06 16:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-05-06 16:32 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/adl_p: Add support for Display Page Tables (rev2)
URL : https://patchwork.freedesktop.org/series/89078/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ff3b7dc8f685 drm/i915/xelpd: add XE_LPD display characteristics
a319d966c549 drm/i915/adl_p: Add PCI Devices IDs
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#26: FILE: include/drm/i915_pciids.h:651:
+#define INTEL_ADLP_IDS(info) \
+ INTEL_VGA_DEVICE(0x46A0, info), \
+ INTEL_VGA_DEVICE(0x46A1, info), \
+ INTEL_VGA_DEVICE(0x46A2, info), \
+ INTEL_VGA_DEVICE(0x46A3, info), \
+ INTEL_VGA_DEVICE(0x46A6, info), \
+ INTEL_VGA_DEVICE(0x46A8, info), \
+ INTEL_VGA_DEVICE(0x46AA, info), \
+ INTEL_VGA_DEVICE(0x462A, info), \
+ INTEL_VGA_DEVICE(0x4626, info), \
+ INTEL_VGA_DEVICE(0x4628, info), \
+ INTEL_VGA_DEVICE(0x46B0, info), \
+ INTEL_VGA_DEVICE(0x46B1, info), \
+ INTEL_VGA_DEVICE(0x46B2, info), \
+ INTEL_VGA_DEVICE(0x46B3, info), \
+ INTEL_VGA_DEVICE(0x46C0, info), \
+ INTEL_VGA_DEVICE(0x46C1, info), \
+ INTEL_VGA_DEVICE(0x46C2, info), \
+ INTEL_VGA_DEVICE(0x46C3, info)
-:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#26: FILE: include/drm/i915_pciids.h:651:
+#define INTEL_ADLP_IDS(info) \
+ INTEL_VGA_DEVICE(0x46A0, info), \
+ INTEL_VGA_DEVICE(0x46A1, info), \
+ INTEL_VGA_DEVICE(0x46A2, info), \
+ INTEL_VGA_DEVICE(0x46A3, info), \
+ INTEL_VGA_DEVICE(0x46A6, info), \
+ INTEL_VGA_DEVICE(0x46A8, info), \
+ INTEL_VGA_DEVICE(0x46AA, info), \
+ INTEL_VGA_DEVICE(0x462A, info), \
+ INTEL_VGA_DEVICE(0x4626, info), \
+ INTEL_VGA_DEVICE(0x4628, info), \
+ INTEL_VGA_DEVICE(0x46B0, info), \
+ INTEL_VGA_DEVICE(0x46B1, info), \
+ INTEL_VGA_DEVICE(0x46B2, info), \
+ INTEL_VGA_DEVICE(0x46B3, info), \
+ INTEL_VGA_DEVICE(0x46C0, info), \
+ INTEL_VGA_DEVICE(0x46C1, info), \
+ INTEL_VGA_DEVICE(0x46C2, info), \
+ INTEL_VGA_DEVICE(0x46C3, info)
total: 1 errors, 0 warnings, 1 checks, 25 lines checked
a35b4326f650 drm/i915/adl_p: ADL_P device info enabling
9c9b86ac6d1f drm/i915/xelpd: First stab at DPT support
-:589: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#589: FILE: drivers/gpu/drm/i915/display/skl_universal_plane.c:946:
+ return offset >> 9;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 591 lines checked
c248682ab7f3 drm/i915/xelpd: Fallback to plane stride limitations when using DPT
c14a9051e424 drm/i915/xelpd: Support 128k plane stride
c55b96cff231 drm/i915/adl_p: Add stride restriction when using DPT
f86259ff5f81 drm/i915/adl_p: Disable support for 90/270 FB rotation
6cc7df9cf93e drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
e83dba92cd47 drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/adl_p: Add support for Display Page Tables (rev2)
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (10 preceding siblings ...)
2021-05-06 16:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adl_p: Add support for Display Page Tables (rev2) Patchwork
@ 2021-05-06 16:34 ` Patchwork
2021-05-06 17:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-05-06 16:34 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/adl_p: Add support for Display Page Tables (rev2)
URL : https://patchwork.freedesktop.org/series/89078/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (11 preceding siblings ...)
2021-05-06 16:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-05-06 17:03 ` Patchwork
2021-05-06 17:58 ` Imre Deak
2021-05-06 18:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-06 20:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
14 siblings, 1 reply; 25+ messages in thread
From: Patchwork @ 2021-05-06 17:03 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3920 bytes --]
== Series Details ==
Series: drm/i915/adl_p: Add support for Display Page Tables (rev2)
URL : https://patchwork.freedesktop.org/series/89078/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10053 -> Patchwork_20077
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20077 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20077, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20077:
### IGT changes ###
#### Possible regressions ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
Known issues
------------
Here are the changes found in Patchwork_20077 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-tgl-y: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-tgl-y/igt@amdgpu/amd_prime@amd-to-i915.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][4] -> [INCOMPLETE][5] ([i915#2782])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
Participating hosts (44 -> 40)
------------------------------
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_10053 -> Patchwork_20077
CI-20190529: 20190529
CI_DRM_10053: 3e000bbf311ad04f734843e1ba6396b28ba44399 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6080: 1c450c3d4df19cf1087b8ccff3b62cb51addacae @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20077: e83dba92cd47bd2b5841fc8e7f66bbd7d376e7bd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e83dba92cd47 drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
6cc7df9cf93e drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
f86259ff5f81 drm/i915/adl_p: Disable support for 90/270 FB rotation
c55b96cff231 drm/i915/adl_p: Add stride restriction when using DPT
c14a9051e424 drm/i915/xelpd: Support 128k plane stride
c248682ab7f3 drm/i915/xelpd: Fallback to plane stride limitations when using DPT
9c9b86ac6d1f drm/i915/xelpd: First stab at DPT support
a35b4326f650 drm/i915/adl_p: ADL_P device info enabling
a319d966c549 drm/i915/adl_p: Add PCI Devices IDs
ff3b7dc8f685 drm/i915/xelpd: add XE_LPD display characteristics
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
[-- Attachment #1.2: Type: text/html, Size: 4378 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)
2021-05-06 17:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-05-06 17:58 ` Imre Deak
2021-05-06 19:12 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2021-05-06 17:58 UTC (permalink / raw)
To: intel-gfx, Lakshminarayana Vudum
On Thu, May 06, 2021 at 05:03:29PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/adl_p: Add support for Display Page Tables (rev2)
> URL : https://patchwork.freedesktop.org/series/89078/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10053 -> Patchwork_20077
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_20077 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_20077, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_20077:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-kbl-7500u: [PASS][1] -> [FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
Chamelium doesn't disconnect after deasserting manually its HPD signal
as expected. No idea how it would be related to the ADL_P specific
changes in this patchset. I found a few previous instances of the same
problem on the same machine:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10045/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20026/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20021/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5766/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7697/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
Lakshmi, could we open a ticket for this?
> Known issues
> ------------
>
> Here are the changes found in Patchwork_20077 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@amdgpu/amd_prime@amd-to-i915:
> - fi-tgl-y: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-tgl-y/igt@amdgpu/amd_prime@amd-to-i915.html
>
> * igt@i915_selftest@live@hangcheck:
> - fi-snb-2600: [PASS][4] -> [INCOMPLETE][5] ([i915#2782])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
> [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
> [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
> [i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
> [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
> [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
>
>
> Participating hosts (44 -> 40)
> ------------------------------
>
> Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_10053 -> Patchwork_20077
>
> CI-20190529: 20190529
> CI_DRM_10053: 3e000bbf311ad04f734843e1ba6396b28ba44399 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6080: 1c450c3d4df19cf1087b8ccff3b62cb51addacae @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_20077: e83dba92cd47bd2b5841fc8e7f66bbd7d376e7bd @ git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> e83dba92cd47 drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
> 6cc7df9cf93e drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
> f86259ff5f81 drm/i915/adl_p: Disable support for 90/270 FB rotation
> c55b96cff231 drm/i915/adl_p: Add stride restriction when using DPT
> c14a9051e424 drm/i915/xelpd: Support 128k plane stride
> c248682ab7f3 drm/i915/xelpd: Fallback to plane stride limitations when using DPT
> 9c9b86ac6d1f drm/i915/xelpd: First stab at DPT support
> a35b4326f650 drm/i915/adl_p: ADL_P device info enabling
> a319d966c549 drm/i915/adl_p: Add PCI Devices IDs
> ff3b7dc8f685 drm/i915/xelpd: add XE_LPD display characteristics
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)
2021-05-06 17:58 ` Imre Deak
@ 2021-05-06 19:12 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 25+ messages in thread
From: Vudum, Lakshminarayana @ 2021-05-06 19:12 UTC (permalink / raw)
To: Deak, Imre, intel-gfx
Re-reported.
-----Original Message-----
From: Deak, Imre <imre.deak@intel.com>
Sent: Thursday, May 6, 2021 10:58 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)
On Thu, May 06, 2021 at 05:03:29PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/adl_p: Add support for Display Page Tables (rev2)
> URL : https://patchwork.freedesktop.org/series/89078/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10053 -> Patchwork_20077
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_20077 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_20077, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_20077:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-kbl-7500u: [PASS][1] -> [FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-kbl-7500u/
> igt@kms_chamelium@common-hpd-after-suspend.html
Chamelium doesn't disconnect after deasserting manually its HPD signal as expected. No idea how it would be related to the ADL_P specific changes in this patchset. I found a few previous instances of the same problem on the same machine:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10045/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20026/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20021/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5766/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_7697/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
Lakshmi, could we open a ticket for this?
> Known issues
> ------------
>
> Here are the changes found in Patchwork_20077 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@amdgpu/amd_prime@amd-to-i915:
> - fi-tgl-y: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575])
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-tgl-y/igt@
> amdgpu/amd_prime@amd-to-i915.html
>
> * igt@i915_selftest@live@hangcheck:
> - fi-snb-2600: [PASS][4] -> [INCOMPLETE][5] ([i915#2782])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
> [5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-snb-2600/i
> gt@i915_selftest@live@hangcheck.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
> [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
> [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
> [i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
> [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
> [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
>
>
> Participating hosts (44 -> 40)
> ------------------------------
>
> Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_10053 -> Patchwork_20077
>
> CI-20190529: 20190529
> CI_DRM_10053: 3e000bbf311ad04f734843e1ba6396b28ba44399 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6080: 1c450c3d4df19cf1087b8ccff3b62cb51addacae @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_20077: e83dba92cd47bd2b5841fc8e7f66bbd7d376e7bd @
> git://anongit.freedesktop.org/gfx-ci/linux
>
>
> == Linux commits ==
>
> e83dba92cd47 drm/i915/adl_p: Enable remapping to pad DPT FB strides to
> POT 6cc7df9cf93e drm/i915/adl_p: Require a minimum of 8 tiles stride
> for DPT FBs
> f86259ff5f81 drm/i915/adl_p: Disable support for 90/270 FB rotation
> c55b96cff231 drm/i915/adl_p: Add stride restriction when using DPT
> c14a9051e424 drm/i915/xelpd: Support 128k plane stride
> c248682ab7f3 drm/i915/xelpd: Fallback to plane stride limitations when
> using DPT 9c9b86ac6d1f drm/i915/xelpd: First stab at DPT support
> a35b4326f650 drm/i915/adl_p: ADL_P device info enabling
> a319d966c549 drm/i915/adl_p: Add PCI Devices IDs
> ff3b7dc8f685 drm/i915/xelpd: add XE_LPD display characteristics
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: Add support for Display Page Tables (rev2)
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (12 preceding siblings ...)
2021-05-06 17:03 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-05-06 18:14 ` Patchwork
2021-05-06 20:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
14 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2021-05-06 18:14 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3522 bytes --]
== Series Details ==
Series: drm/i915/adl_p: Add support for Display Page Tables (rev2)
URL : https://patchwork.freedesktop.org/series/89078/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10053 -> Patchwork_20077
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
Known issues
------------
Here are the changes found in Patchwork_20077 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-tgl-y: NOTRUN -> [SKIP][1] ([fdo#109315] / [i915#2575])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-tgl-y/igt@amdgpu/amd_prime@amd-to-i915.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][2] -> [INCOMPLETE][3] ([i915#2782])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [PASS][4] -> [FAIL][5] ([i915#3449])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3449]: https://gitlab.freedesktop.org/drm/intel/issues/3449
Participating hosts (44 -> 40)
------------------------------
Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_10053 -> Patchwork_20077
CI-20190529: 20190529
CI_DRM_10053: 3e000bbf311ad04f734843e1ba6396b28ba44399 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6080: 1c450c3d4df19cf1087b8ccff3b62cb51addacae @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20077: e83dba92cd47bd2b5841fc8e7f66bbd7d376e7bd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e83dba92cd47 drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT
6cc7df9cf93e drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs
f86259ff5f81 drm/i915/adl_p: Disable support for 90/270 FB rotation
c55b96cff231 drm/i915/adl_p: Add stride restriction when using DPT
c14a9051e424 drm/i915/xelpd: Support 128k plane stride
c248682ab7f3 drm/i915/xelpd: Fallback to plane stride limitations when using DPT
9c9b86ac6d1f drm/i915/xelpd: First stab at DPT support
a35b4326f650 drm/i915/adl_p: ADL_P device info enabling
a319d966c549 drm/i915/adl_p: Add PCI Devices IDs
ff3b7dc8f685 drm/i915/xelpd: add XE_LPD display characteristics
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
[-- Attachment #1.2: Type: text/html, Size: 3968 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)
2021-05-06 16:19 [Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables Imre Deak
` (13 preceding siblings ...)
2021-05-06 18:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-05-06 20:17 ` Patchwork
2021-05-07 9:36 ` Imre Deak
14 siblings, 1 reply; 25+ messages in thread
From: Patchwork @ 2021-05-06 20:17 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30281 bytes --]
== Series Details ==
Series: drm/i915/adl_p: Add support for Display Page Tables (rev2)
URL : https://patchwork.freedesktop.org/series/89078/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10053_full -> Patchwork_20077_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20077_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20077_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20077_full:
### Piglit changes ###
#### Possible regressions ####
* spec@ext_transform_feedback@builtin-varyings gl_clipvertex (NEW):
- pig-glk-j5005: NOTRUN -> [INCOMPLETE][1]
[1]: None
New tests
---------
New tests have been introduced between CI_DRM_10053_full and Patchwork_20077_full:
### New Piglit tests (1) ###
* spec@ext_transform_feedback@builtin-varyings gl_clipvertex:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_20077_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-2x:
- shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@feature_discovery@display-2x.html
* igt@gem_ctx_persistence@clone:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +5 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb6/igt@gem_ctx_persistence@clone.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][4] ([i915#3354])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [PASS][13] -> [SKIP][14] ([fdo#109271])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][15] ([i915#2658])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl1/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271]) +38 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl4/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#768])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#3002])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl8/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109289])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@gen7_exec_parse@batch-without-end.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / [i915#716])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl8/igt@gen9_exec_parse@allowed-single.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl4/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-snb: NOTRUN -> [SKIP][22] ([fdo#109271]) +367 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb2/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_pm_sseu@full-enable:
- shard-iclb: NOTRUN -> [SKIP][23] ([fdo#109288])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@i915_pm_sseu@full-enable.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: NOTRUN -> [INCOMPLETE][24] ([i915#2782])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb5/igt@i915_selftest@live@hangcheck.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#1769])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271]) +108 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl6/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][27] ([fdo#110723])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_ccs@pipe-c-bad-pixel-format:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111304])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@kms_ccs@pipe-c-bad-pixel-format.html
* igt@kms_chamelium@dp-mode-timings:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +12 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl8/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +10 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl5/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color@pipe-a-ctm-green-to-red:
- shard-skl: [PASS][32] -> [DMESG-WARN][33] ([i915#1982]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl7/igt@kms_color@pipe-a-ctm-green-to-red.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl10/igt@kms_color@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +20 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_color_chamelium@pipe-d-ctm-max.html
* igt@kms_content_protection@atomic-dpms:
- shard-kbl: NOTRUN -> [TIMEOUT][37] ([i915#1319])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@mei_interface:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109300] / [fdo#111066])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-random:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278] / [fdo#109279])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding:
- shard-skl: [PASS][40] -> [FAIL][41] ([i915#3444])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109274] / [fdo#109278]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipa-atomic:
- shard-snb: [PASS][43] -> [SKIP][44] ([fdo#109271]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-snb2/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb2/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][45] ([i915#2346] / [i915#533])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
- shard-skl: [PASS][46] -> [FAIL][47] ([i915#2346])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][49] -> [FAIL][50] ([i915#79])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-kbl: [PASS][51] -> [DMESG-WARN][52] ([i915#180]) +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl4/igt@kms_flip@flip-vs-suspend@b-dp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl7/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [PASS][53] -> [FAIL][54] ([i915#2122])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-iclb: [PASS][55] -> [FAIL][56] ([i915#49])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271]) +86 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-glk: [PASS][58] -> [FAIL][59] ([i915#49])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +9 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][61] -> [FAIL][62] ([i915#1188])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109278]) +7 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#533]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][67] ([fdo#108145] / [i915#265])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][68] -> [FAIL][69] ([fdo#108145] / [i915#265]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_properties@connector-properties-atomic:
- shard-glk: [PASS][70] -> [DMESG-WARN][71] ([i915#118] / [i915#95]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@kms_properties@connector-properties-atomic.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk7/igt@kms_properties@connector-properties-atomic.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
- shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
- shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl9/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][75] -> [SKIP][76] ([fdo#109441]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2437])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html
- shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2437])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl4/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-ctx-flip-detection:
- shard-iclb: NOTRUN -> [SKIP][80] ([i915#2530])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][81] -> [FAIL][82] ([i915#1542])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@perf@polling-parameterized.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk4/igt@perf@polling-parameterized.html
- shard-skl: [PASS][83] -> [FAIL][84] ([i915#1542])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl4/igt@perf@polling-parameterized.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl1/igt@perf@polling-parameterized.html
* igt@prime_nv_api@i915_nv_double_import:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@prime_nv_api@i915_nv_double_import.html
* igt@prime_vgem@basic-userptr:
- shard-iclb: NOTRUN -> [SKIP][86] ([i915#3301])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@fence-read-hang:
- shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109295])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@prime_vgem@fence-read-hang.html
* igt@sysfs_clients@create:
- shard-iclb: NOTRUN -> [SKIP][88] ([i915#2994])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@sysfs_clients@create.html
* igt@sysfs_clients@sema-10:
- shard-skl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994]) +3 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl9/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@sema-25:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2994])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl1/igt@sysfs_clients@sema-25.html
* igt@sysfs_clients@sema-50:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_ctx_shared@q-smoketest-all:
- shard-glk: [DMESG-WARN][92] ([i915#118] / [i915#95]) -> [PASS][93] +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk9/igt@gem_ctx_shared@q-smoketest-all.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk5/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][94] ([i915#2842]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-tglb5/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_vm_create@destroy-race:
- shard-tglb: [TIMEOUT][98] ([i915#2795]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-tglb5/igt@gem_vm_create@destroy-race.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-tglb5/igt@gem_vm_create@destroy-race.html
* igt@i915_pm_dc@dc5-psr:
- shard-skl: [INCOMPLETE][100] ([i915#198]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl2/igt@i915_pm_dc@dc5-psr.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@i915_pm_dc@dc5-psr.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [INCOMPLETE][102] ([i915#151]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl7/igt@i915_pm_rpm@system-suspend-execbuf.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl5/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][104] ([i915#180]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [DMESG-WARN][106] ([i915#180]) -> [PASS][107] +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
- shard-iclb: [FAIL][108] -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb5/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][110] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- shard-skl: [FAIL][112] ([i915#53]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][114] ([fdo#108145] / [i915#265]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_lowres@pipe-c-tiling-none:
- shard-glk: [FAIL][116] ([i915#899]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@kms_plane_lowres@pipe-c-tiling-none.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk7/igt@kms_plane_lowres@pipe-c-tiling-none.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][118] ([fdo#109441]) -> [PASS][119] +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@perf@blocking:
- shard-skl: [FAIL][120] ([i915#1542]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl9/igt@perf@blocking.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl6/igt@perf@blocking.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][122] ([i915#1722]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl8/igt@perf@polling-small-buf.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl6/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][124] ([i915#1804] / [i915#2684]) -> [WARN][125] ([i915#2684])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: [INCOMPLETE][126] ([i915#2405]) -> [DMESG-WARN][127] ([i915#180])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: [SKIP][128] ([i915#658]) -> [SKIP][129] ([i915#2920]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb8/igt@kms_psr2_sf@cursor-plane-update-sf.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][130] ([i915#2920]) -> [SKIP][131] ([i915#658]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#92]) -> ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([i915#180] / [i915#1814] / [i915#2292] / [i915#3002] / [i915#3363])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl6/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl7/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl2/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl7/igt@runner@aborted.html
- shard-apl: ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][149], [FAIL][150]) ([i915#3002] / [i915#3363])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl6/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl6/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl1/igt@runner@
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
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^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)
2021-05-06 20:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-05-07 9:36 ` Imre Deak
2021-05-07 14:56 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2021-05-07 9:36 UTC (permalink / raw)
To: intel-gfx, Matt Roper, Clint A Taylor, Ville Syrjälä,
Juha-Pekka Heikkilä,
Jose Souza, Chris Wilson, Lucas De Marchi, Lakshminarayana Vudum,
Jani Nikula, Rodrigo Vivi
On Thu, May 06, 2021 at 08:17:37PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/adl_p: Add support for Display Page Tables (rev2)
> URL : https://patchwork.freedesktop.org/series/89078/
> State : failure
Merged to -din, thanks for the patches and reviews.
The failure is unrelated see below.
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10053_full -> Patchwork_20077_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_20077_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_20077_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_20077_full:
>
> ### Piglit changes ###
>
> #### Possible regressions ####
>
> * spec@ext_transform_feedback@builtin-varyings gl_clipvertex (NEW):
> - pig-glk-j5005: NOTRUN -> [INCOMPLETE][1]
I didn't find a way to match dmesg to the test, but looks like:
<3>[ 290.820108] intel_rps_park:864 GEM_BUG_ON(atomic_read(&rps->num_waiters))
Previous instances of the above issue on the same machine during Piglit runs:
CI_DIN_195/pig-glk-j5005
CI_DRM_10019/pig-glk-j5005
Patchwork_20044/pig-glk-j5005
on SKL-6260u:
Patchwork_20068/pig-skl-6260u
during IGT runs on GLK:
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5785/shard-glk4/igt@gem_exec_flush@basic-uc-rw-default.html
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20032/shard-glk1/igt@gem_exec_flush@basic-wb-ro-before-default.html
CI_DIN_193/shard-glk8
Trybot_7699/shard-glk3
on other platforms:
kasan_247/fi-bsw-kefka
kasan_250/fi-kbl-r
kasan_250/fi-jsl-1
kasan_251/fi-bsw-kefka
kasan_252/fi-bsw-kefka
The changes in the patchset are not relevant on GLK.
> [1]: None
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_10053_full and Patchwork_20077_full:
>
> ### New Piglit tests (1) ###
>
> * spec@ext_transform_feedback@builtin-varyings gl_clipvertex:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_20077_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@feature_discovery@display-2x:
> - shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839])
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@feature_discovery@display-2x.html
>
> * igt@gem_ctx_persistence@clone:
> - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +5 similar issues
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb6/igt@gem_ctx_persistence@clone.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-snb: NOTRUN -> [FAIL][4] ([i915#3354])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb6/igt@gem_eio@unwedge-stress.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
> - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@rcs0:
> - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs1:
> - shard-kbl: [PASS][13] -> [SKIP][14] ([fdo#109271])
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
>
> * igt@gem_pwrite@basic-exhaustion:
> - shard-apl: NOTRUN -> [WARN][15] ([i915#2658])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl1/igt@gem_pwrite@basic-exhaustion.html
>
> * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
> - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271]) +38 similar issues
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl4/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
>
> * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
> - shard-iclb: NOTRUN -> [SKIP][17] ([i915#768])
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
>
> * igt@gem_userptr_blits@input-checking:
> - shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#3002])
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl8/igt@gem_userptr_blits@input-checking.html
>
> * igt@gen7_exec_parse@batch-without-end:
> - shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109289])
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@gen7_exec_parse@batch-without-end.html
>
> * igt@gen9_exec_parse@allowed-single:
> - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / [i915#716])
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl8/igt@gen9_exec_parse@allowed-single.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl4/igt@gen9_exec_parse@allowed-single.html
>
> * igt@gen9_exec_parse@batch-invalid-length:
> - shard-snb: NOTRUN -> [SKIP][22] ([fdo#109271]) +367 similar issues
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb2/igt@gen9_exec_parse@batch-invalid-length.html
>
> * igt@i915_pm_sseu@full-enable:
> - shard-iclb: NOTRUN -> [SKIP][23] ([fdo#109288])
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@i915_pm_sseu@full-enable.html
>
> * igt@i915_selftest@live@hangcheck:
> - shard-snb: NOTRUN -> [INCOMPLETE][24] ([i915#2782])
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb5/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_atomic_transition@plane-all-modeset-transition:
> - shard-iclb: NOTRUN -> [SKIP][25] ([i915#1769])
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_atomic_transition@plane-all-modeset-transition.html
>
> * igt@kms_big_fb@linear-16bpp-rotate-90:
> - shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271]) +108 similar issues
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl6/igt@kms_big_fb@linear-16bpp-rotate-90.html
>
> * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
> - shard-iclb: NOTRUN -> [SKIP][27] ([fdo#110723])
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
>
> * igt@kms_ccs@pipe-c-bad-pixel-format:
> - shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111304])
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@kms_ccs@pipe-c-bad-pixel-format.html
>
> * igt@kms_chamelium@dp-mode-timings:
> - shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +12 similar issues
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl8/igt@kms_chamelium@dp-mode-timings.html
>
> * igt@kms_chamelium@vga-hpd-after-suspend:
> - shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +10 similar issues
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl5/igt@kms_chamelium@vga-hpd-after-suspend.html
>
> * igt@kms_chamelium@vga-hpd-without-ddc:
> - shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +2 similar issues
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_chamelium@vga-hpd-without-ddc.html
>
> * igt@kms_color@pipe-a-ctm-green-to-red:
> - shard-skl: [PASS][32] -> [DMESG-WARN][33] ([i915#1982]) +2 similar issues
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl7/igt@kms_color@pipe-a-ctm-green-to-red.html
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl10/igt@kms_color@pipe-a-ctm-green-to-red.html
>
> * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
> - shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +20 similar issues
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
> - shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827]) +2 similar issues
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
>
> * igt@kms_color_chamelium@pipe-d-ctm-max:
> - shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109278] / [fdo#109284] / [fdo#111827])
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_color_chamelium@pipe-d-ctm-max.html
>
> * igt@kms_content_protection@atomic-dpms:
> - shard-kbl: NOTRUN -> [TIMEOUT][37] ([i915#1319])
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_content_protection@atomic-dpms.html
>
> * igt@kms_content_protection@mei_interface:
> - shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109300] / [fdo#111066])
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_content_protection@mei_interface.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-512x170-random:
> - shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278] / [fdo#109279])
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding:
> - shard-skl: [PASS][40] -> [FAIL][41] ([i915#3444])
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl1/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html
>
> * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
> - shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109274] / [fdo#109278]) +1 similar issue
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
>
> * igt@kms_cursor_legacy@cursora-vs-flipa-atomic:
> - shard-snb: [PASS][43] -> [SKIP][44] ([fdo#109271]) +1 similar issue
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-snb2/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb2/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
> - shard-skl: NOTRUN -> [FAIL][45] ([i915#2346] / [i915#533])
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
> - shard-skl: [PASS][46] -> [FAIL][47] ([i915#2346])
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
>
> * igt@kms_cursor_legacy@pipe-d-torture-bo:
> - shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533])
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
> - shard-skl: [PASS][49] -> [FAIL][50] ([i915#79])
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
>
> * igt@kms_flip@flip-vs-suspend@b-dp1:
> - shard-kbl: [PASS][51] -> [DMESG-WARN][52] ([i915#180]) +4 similar issues
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl4/igt@kms_flip@flip-vs-suspend@b-dp1.html
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl7/igt@kms_flip@flip-vs-suspend@b-dp1.html
>
> * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
> - shard-skl: [PASS][53] -> [FAIL][54] ([i915#2122])
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
> - shard-iclb: [PASS][55] -> [FAIL][56] ([i915#49])
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
>
> * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
> - shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271]) +86 similar issues
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@fbc-stridechange:
> - shard-glk: [PASS][58] -> [FAIL][59] ([i915#49])
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
> - shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +9 similar issues
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
>
> * igt@kms_hdr@bpc-switch-dpms:
> - shard-skl: [PASS][61] -> [FAIL][62] ([i915#1188])
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
>
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
> - shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109278]) +7 similar issues
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
> - shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#533]) +1 similar issue
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
> - shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
>
> * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
> - shard-skl: NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265])
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
>
> * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
> - shard-apl: NOTRUN -> [FAIL][67] ([fdo#108145] / [i915#265])
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][68] -> [FAIL][69] ([fdo#108145] / [i915#265]) +2 similar issues
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_properties@connector-properties-atomic:
> - shard-glk: [PASS][70] -> [DMESG-WARN][71] ([i915#118] / [i915#95]) +2 similar issues
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@kms_properties@connector-properties-atomic.html
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk7/igt@kms_properties@connector-properties-atomic.html
>
> * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
> - shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658])
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
> - shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +1 similar issue
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl9/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
>
> * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
> - shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658]) +2 similar issues
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
>
> * igt@kms_psr@psr2_cursor_plane_onoff:
> - shard-iclb: [PASS][75] -> [SKIP][76] ([fdo#109441]) +1 similar issue
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
>
> * igt@kms_writeback@writeback-check-output:
> - shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2437])
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl6/igt@kms_writeback@writeback-check-output.html
>
> * igt@kms_writeback@writeback-pixel-formats:
> - shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437])
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html
> - shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2437])
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl4/igt@kms_writeback@writeback-pixel-formats.html
>
> * igt@nouveau_crc@pipe-a-ctx-flip-detection:
> - shard-iclb: NOTRUN -> [SKIP][80] ([i915#2530])
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
>
> * igt@perf@polling-parameterized:
> - shard-glk: [PASS][81] -> [FAIL][82] ([i915#1542])
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@perf@polling-parameterized.html
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk4/igt@perf@polling-parameterized.html
> - shard-skl: [PASS][83] -> [FAIL][84] ([i915#1542])
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl4/igt@perf@polling-parameterized.html
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl1/igt@perf@polling-parameterized.html
>
> * igt@prime_nv_api@i915_nv_double_import:
> - shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291])
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@prime_nv_api@i915_nv_double_import.html
>
> * igt@prime_vgem@basic-userptr:
> - shard-iclb: NOTRUN -> [SKIP][86] ([i915#3301])
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@prime_vgem@basic-userptr.html
>
> * igt@prime_vgem@fence-read-hang:
> - shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109295])
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@prime_vgem@fence-read-hang.html
>
> * igt@sysfs_clients@create:
> - shard-iclb: NOTRUN -> [SKIP][88] ([i915#2994])
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@sysfs_clients@create.html
>
> * igt@sysfs_clients@sema-10:
> - shard-skl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994]) +3 similar issues
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl9/igt@sysfs_clients@sema-10.html
>
> * igt@sysfs_clients@sema-25:
> - shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2994])
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl1/igt@sysfs_clients@sema-25.html
>
> * igt@sysfs_clients@sema-50:
> - shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994]) +1 similar issue
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@sysfs_clients@sema-50.html
>
>
> #### Possible fixes ####
>
> * igt@gem_ctx_shared@q-smoketest-all:
> - shard-glk: [DMESG-WARN][92] ([i915#118] / [i915#95]) -> [PASS][93] +2 similar issues
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk9/igt@gem_ctx_shared@q-smoketest-all.html
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk5/igt@gem_ctx_shared@q-smoketest-all.html
>
> * igt@gem_exec_fair@basic-none-share@rcs0:
> - shard-iclb: [FAIL][94] ([i915#2842]) -> [PASS][95]
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vecs0:
> - shard-tglb: [FAIL][96] ([i915#2842]) -> [PASS][97]
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-tglb5/igt@gem_exec_fair@basic-pace@vecs0.html
>
> * igt@gem_vm_create@destroy-race:
> - shard-tglb: [TIMEOUT][98] ([i915#2795]) -> [PASS][99]
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-tglb5/igt@gem_vm_create@destroy-race.html
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-tglb5/igt@gem_vm_create@destroy-race.html
>
> * igt@i915_pm_dc@dc5-psr:
> - shard-skl: [INCOMPLETE][100] ([i915#198]) -> [PASS][101]
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl2/igt@i915_pm_dc@dc5-psr.html
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@i915_pm_dc@dc5-psr.html
>
> * igt@i915_pm_rpm@system-suspend-execbuf:
> - shard-skl: [INCOMPLETE][102] ([i915#151]) -> [PASS][103]
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl7/igt@i915_pm_rpm@system-suspend-execbuf.html
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl5/igt@i915_pm_rpm@system-suspend-execbuf.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-suspend:
> - shard-kbl: [DMESG-WARN][104] ([i915#180]) -> [PASS][105]
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-apl: [DMESG-WARN][106] ([i915#180]) -> [PASS][107] +1 similar issue
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
> - shard-iclb: [FAIL][108] -> [PASS][109]
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb5/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
>
> * igt@kms_fbcon_fbt@fbc-suspend:
> - shard-kbl: [INCOMPLETE][110] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][111]
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
>
> * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
> - shard-skl: [FAIL][112] ([i915#53]) -> [PASS][113]
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
>
> * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> - shard-skl: [FAIL][114] ([fdo#108145] / [i915#265]) -> [PASS][115]
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
>
> * igt@kms_plane_lowres@pipe-c-tiling-none:
> - shard-glk: [FAIL][116] ([i915#899]) -> [PASS][117]
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@kms_plane_lowres@pipe-c-tiling-none.html
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk7/igt@kms_plane_lowres@pipe-c-tiling-none.html
>
> * igt@kms_psr@psr2_primary_page_flip:
> - shard-iclb: [SKIP][118] ([fdo#109441]) -> [PASS][119] +1 similar issue
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
>
> * igt@perf@blocking:
> - shard-skl: [FAIL][120] ([i915#1542]) -> [PASS][121]
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl9/igt@perf@blocking.html
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl6/igt@perf@blocking.html
>
> * igt@perf@polling-small-buf:
> - shard-skl: [FAIL][122] ([i915#1722]) -> [PASS][123]
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl8/igt@perf@polling-small-buf.html
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl6/igt@perf@polling-small-buf.html
>
>
> #### Warnings ####
>
> * igt@i915_pm_rc6_residency@rc6-fence:
> - shard-iclb: [WARN][124] ([i915#1804] / [i915#2684]) -> [WARN][125] ([i915#2684])
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
>
> * igt@kms_cursor_crc@pipe-b-cursor-suspend:
> - shard-kbl: [INCOMPLETE][126] ([i915#2405]) -> [DMESG-WARN][127] ([i915#180])
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
>
> * igt@kms_psr2_sf@cursor-plane-update-sf:
> - shard-iclb: [SKIP][128] ([i915#658]) -> [SKIP][129] ([i915#2920]) +1 similar issue
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb8/igt@kms_psr2_sf@cursor-plane-update-sf.html
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
> - shard-iclb: [SKIP][130] ([i915#2920]) -> [SKIP][131] ([i915#658]) +1 similar issue
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
>
> * igt@runner@aborted:
> - shard-kbl: ([FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#92]) -> ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([i915#180] / [i915#1814] / [i915#2292] / [i915#3002] / [i915#3363])
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@runner@aborted.html
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@runner@aborted.html
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@runner@aborted.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@runner@aborted.html
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl6/igt@runner@aborted.html
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl7/igt@runner@aborted.html
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@runner@aborted.html
> [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@runner@aborted.html
> [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@runner@aborted.html
> [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@runner@aborted.html
> [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl2/igt@runner@aborted.html
> [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@runner@aborted.html
> [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl7/igt@runner@aborted.html
> - shard-apl: ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][149], [FAIL][150]) ([i915#3002] / [i915#3363])
> [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl6/igt@runner@aborted.html
> [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl6/igt@runner@aborted.html
> [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl1/igt@runner@
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)
2021-05-07 9:36 ` Imre Deak
@ 2021-05-07 14:56 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 25+ messages in thread
From: Vudum, Lakshminarayana @ 2021-05-07 14:56 UTC (permalink / raw)
To: Deak, Imre, intel-gfx, Roper, Matthew D, Taylor, Clinton A,
Ville Syrjälä,
Heikkila, Juha-pekka, Souza, Jose, Chris Wilson, De Marchi,
Lucas, Nikula, Jani, Vivi, Rodrigo
spec@ext_transform_feedback@builtin-varyings gl_clipvertex (NEW):
This test is not available in CI bug log. So, I cannot re-report.
Lakshmi.
-----Original Message-----
From: Deak, Imre <imre.deak@intel.com>
Sent: Friday, May 7, 2021 2:36 AM
To: intel-gfx@lists.freedesktop.org; Roper, Matthew D <matthew.d.roper@intel.com>; Taylor, Clinton A <clinton.a.taylor@intel.com>; Ville Syrjälä <ville.syrjala@linux.intel.com>; Heikkila, Juha-pekka <juha-pekka.heikkila@intel.com>; Souza, Jose <jose.souza@intel.com>; Chris Wilson <chris@chris-wilson.co.uk>; De Marchi, Lucas <lucas.demarchi@intel.com>; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>; Nikula, Jani <jani.nikula@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)
On Thu, May 06, 2021 at 08:17:37PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/adl_p: Add support for Display Page Tables (rev2)
> URL : https://patchwork.freedesktop.org/series/89078/
> State : failure
Merged to -din, thanks for the patches and reviews.
The failure is unrelated see below.
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_10053_full -> Patchwork_20077_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_20077_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_20077_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_20077_full:
>
> ### Piglit changes ###
>
> #### Possible regressions ####
>
> * spec@ext_transform_feedback@builtin-varyings gl_clipvertex (NEW):
> - pig-glk-j5005: NOTRUN -> [INCOMPLETE][1]
I didn't find a way to match dmesg to the test, but looks like:
<3>[ 290.820108] intel_rps_park:864 GEM_BUG_ON(atomic_read(&rps->num_waiters))
Previous instances of the above issue on the same machine during Piglit runs:
CI_DIN_195/pig-glk-j5005
CI_DRM_10019/pig-glk-j5005
Patchwork_20044/pig-glk-j5005
on SKL-6260u:
Patchwork_20068/pig-skl-6260u
during IGT runs on GLK:
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_5785/shard-glk4/igt@gem_exec_flush@basic-uc-rw-default.html
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20032/shard-glk1/igt@gem_exec_flush@basic-wb-ro-before-default.html
CI_DIN_193/shard-glk8
Trybot_7699/shard-glk3
on other platforms:
kasan_247/fi-bsw-kefka
kasan_250/fi-kbl-r
kasan_250/fi-jsl-1
kasan_251/fi-bsw-kefka
kasan_252/fi-bsw-kefka
The changes in the patchset are not relevant on GLK.
> [1]: None
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_10053_full and Patchwork_20077_full:
>
> ### New Piglit tests (1) ###
>
> * spec@ext_transform_feedback@builtin-varyings gl_clipvertex:
> - Statuses : 1 incomplete(s)
> - Exec time: [0.0] s
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_20077_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@feature_discovery@display-2x:
> - shard-iclb: NOTRUN -> [SKIP][2] ([i915#1839])
> [2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@feature_discovery@display-2x.html
>
> * igt@gem_ctx_persistence@clone:
> - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +5 similar issues
> [3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb6/ig
> t@gem_ctx_persistence@clone.html
>
> * igt@gem_eio@unwedge-stress:
> - shard-snb: NOTRUN -> [FAIL][4] ([i915#3354])
> [4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb6/ig
> t@gem_eio@unwedge-stress.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
> - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk5/ig
> t@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> [10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb7/i
> gt@gem_exec_fair@basic-pace-solo@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@rcs0:
> - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
> [12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/ig
> t@gem_exec_fair@basic-pace@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vcs1:
> - shard-kbl: [PASS][13] -> [SKIP][14] ([fdo#109271])
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
> [14]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/ig
> t@gem_exec_fair@basic-pace@vcs1.html
>
> * igt@gem_pwrite@basic-exhaustion:
> - shard-apl: NOTRUN -> [WARN][15] ([i915#2658])
> [15]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl1/ig
> t@gem_pwrite@basic-exhaustion.html
>
> * igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
> - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271]) +38 similar issues
> [16]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl4/ig
> t@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
>
> * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
> - shard-iclb: NOTRUN -> [SKIP][17] ([i915#768])
> [17]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs.html
>
> * igt@gem_userptr_blits@input-checking:
> - shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#3002])
> [18]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl8/ig
> t@gem_userptr_blits@input-checking.html
>
> * igt@gen7_exec_parse@batch-without-end:
> - shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109289])
> [19]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@gen7_exec_parse@batch-without-end.html
>
> * igt@gen9_exec_parse@allowed-single:
> - shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / [i915#716])
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl8/igt@gen9_exec_parse@allowed-single.html
> [21]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl4/ig
> t@gen9_exec_parse@allowed-single.html
>
> * igt@gen9_exec_parse@batch-invalid-length:
> - shard-snb: NOTRUN -> [SKIP][22] ([fdo#109271]) +367 similar issues
> [22]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb2/ig
> t@gen9_exec_parse@batch-invalid-length.html
>
> * igt@i915_pm_sseu@full-enable:
> - shard-iclb: NOTRUN -> [SKIP][23] ([fdo#109288])
> [23]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@i915_pm_sseu@full-enable.html
>
> * igt@i915_selftest@live@hangcheck:
> - shard-snb: NOTRUN -> [INCOMPLETE][24] ([i915#2782])
> [24]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb5/ig
> t@i915_selftest@live@hangcheck.html
>
> * igt@kms_atomic_transition@plane-all-modeset-transition:
> - shard-iclb: NOTRUN -> [SKIP][25] ([i915#1769])
> [25]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_atomic_transition@plane-all-modeset-transition.html
>
> * igt@kms_big_fb@linear-16bpp-rotate-90:
> - shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271]) +108 similar issues
> [26]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl6/ig
> t@kms_big_fb@linear-16bpp-rotate-90.html
>
> * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
> - shard-iclb: NOTRUN -> [SKIP][27] ([fdo#110723])
> [27]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
>
> * igt@kms_ccs@pipe-c-bad-pixel-format:
> - shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111304])
> [28]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/ig
> t@kms_ccs@pipe-c-bad-pixel-format.html
>
> * igt@kms_chamelium@dp-mode-timings:
> - shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +12 similar issues
> [29]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl8/ig
> t@kms_chamelium@dp-mode-timings.html
>
> * igt@kms_chamelium@vga-hpd-after-suspend:
> - shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +10 similar issues
> [30]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl5/ig
> t@kms_chamelium@vga-hpd-after-suspend.html
>
> * igt@kms_chamelium@vga-hpd-without-ddc:
> - shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +2 similar issues
> [31]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/ig
> t@kms_chamelium@vga-hpd-without-ddc.html
>
> * igt@kms_color@pipe-a-ctm-green-to-red:
> - shard-skl: [PASS][32] -> [DMESG-WARN][33] ([i915#1982]) +2 similar issues
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl7/igt@kms_color@pipe-a-ctm-green-to-red.html
> [33]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl10/i
> gt@kms_color@pipe-a-ctm-green-to-red.html
>
> * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
> - shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +20 similar issues
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
> - shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827]) +2 similar issues
> [35]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
>
> * igt@kms_color_chamelium@pipe-d-ctm-max:
> - shard-iclb: NOTRUN -> [SKIP][36] ([fdo#109278] / [fdo#109284] / [fdo#111827])
> [36]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_color_chamelium@pipe-d-ctm-max.html
>
> * igt@kms_content_protection@atomic-dpms:
> - shard-kbl: NOTRUN -> [TIMEOUT][37] ([i915#1319])
> [37]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/ig
> t@kms_content_protection@atomic-dpms.html
>
> * igt@kms_content_protection@mei_interface:
> - shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109300] / [fdo#111066])
> [38]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_content_protection@mei_interface.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-512x170-random:
> - shard-iclb: NOTRUN -> [SKIP][39] ([fdo#109278] / [fdo#109279])
> [39]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_cursor_crc@pipe-a-cursor-512x170-random.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding:
> - shard-skl: [PASS][40] -> [FAIL][41] ([i915#3444])
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html
> [41]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl1/ig
> t@kms_cursor_crc@pipe-c-cursor-128x42-sliding.html
>
> * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
> - shard-iclb: NOTRUN -> [SKIP][42] ([fdo#109274] / [fdo#109278]) +1 similar issue
> [42]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
>
> * igt@kms_cursor_legacy@cursora-vs-flipa-atomic:
> - shard-snb: [PASS][43] -> [SKIP][44] ([fdo#109271]) +1 similar issue
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-snb2/igt@kms_cursor_legacy@cursora-vs-flipa-atomic.html
> [44]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-snb2/ig
> t@kms_cursor_legacy@cursora-vs-flipa-atomic.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
> - shard-skl: NOTRUN -> [FAIL][45] ([i915#2346] / [i915#533])
> [45]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/ig
> t@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.htm
> l
>
> * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
> - shard-skl: [PASS][46] -> [FAIL][47] ([i915#2346])
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
> [47]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/ig
> t@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
>
> * igt@kms_cursor_legacy@pipe-d-torture-bo:
> - shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533])
> [48]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl1/ig
> t@kms_cursor_legacy@pipe-d-torture-bo.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
> - shard-skl: [PASS][49] -> [FAIL][50] ([i915#79])
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
> [50]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/ig
> t@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
>
> * igt@kms_flip@flip-vs-suspend@b-dp1:
> - shard-kbl: [PASS][51] -> [DMESG-WARN][52] ([i915#180]) +4 similar issues
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl4/igt@kms_flip@flip-vs-suspend@b-dp1.html
> [52]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl7/ig
> t@kms_flip@flip-vs-suspend@b-dp1.html
>
> * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
> - shard-skl: [PASS][53] -> [FAIL][54] ([i915#2122])
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
> [54]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl8/ig
> t@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc:
> - shard-iclb: [PASS][55] -> [FAIL][56] ([i915#49])
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.html
> [56]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb3/i
> gt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc.htm
> l
>
> * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
> - shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271]) +86 similar issues
> [57]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/ig
> t@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
>
> * igt@kms_frontbuffer_tracking@fbc-stridechange:
> - shard-glk: [PASS][58] -> [FAIL][59] ([i915#49])
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@kms_frontbuffer_tracking@fbc-stridechange.html
> [59]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk7/ig
> t@kms_frontbuffer_tracking@fbc-stridechange.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
> - shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +9 similar issues
> [60]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu
> .html
>
> * igt@kms_hdr@bpc-switch-dpms:
> - shard-skl: [PASS][61] -> [FAIL][62] ([i915#1188])
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
> [62]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl1/ig
> t@kms_hdr@bpc-switch-dpms.html
>
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
> - shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109278]) +7 similar issues
> [63]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
>
> * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
> - shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#533]) +1 similar issue
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
> - shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533])
> [65]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/ig
> t@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
>
> * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
> - shard-skl: NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265])
> [66]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl8/ig
> t@kms_plane_alpha_blend@pipe-a-alpha-basic.html
>
> * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
> - shard-apl: NOTRUN -> [FAIL][67] ([fdo#108145] / [i915#265])
> [67]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl6/ig
> t@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][68] -> [FAIL][69] ([fdo#108145] / [i915#265]) +2 similar issues
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [69]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/ig
> t@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_properties@connector-properties-atomic:
> - shard-glk: [PASS][70] -> [DMESG-WARN][71] ([i915#118] / [i915#95]) +2 similar issues
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@kms_properties@connector-properties-atomic.html
> [71]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk7/ig
> t@kms_properties@connector-properties-atomic.html
>
> * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2:
> - shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658])
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
> - shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658]) +1 similar issue
> [73]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl9/ig
> t@kms_psr2_sf@overlay-plane-update-sf-dmg-area-2.html
>
> * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
> - shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#658]) +2 similar issues
> [74]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl2/ig
> t@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
>
> * igt@kms_psr@psr2_cursor_plane_onoff:
> - shard-iclb: [PASS][75] -> [SKIP][76] ([fdo#109441]) +1 similar issue
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
> [76]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb3/i
> gt@kms_psr@psr2_cursor_plane_onoff.html
>
> * igt@kms_writeback@writeback-check-output:
> - shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2437])
> [77]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl6/ig
> t@kms_writeback@writeback-check-output.html
>
> * igt@kms_writeback@writeback-pixel-formats:
> - shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437])
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html
> - shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#2437])
> [79]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl4/ig
> t@kms_writeback@writeback-pixel-formats.html
>
> * igt@nouveau_crc@pipe-a-ctx-flip-detection:
> - shard-iclb: NOTRUN -> [SKIP][80] ([i915#2530])
> [80]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@nouveau_crc@pipe-a-ctx-flip-detection.html
>
> * igt@perf@polling-parameterized:
> - shard-glk: [PASS][81] -> [FAIL][82] ([i915#1542])
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@perf@polling-parameterized.html
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk4/igt@perf@polling-parameterized.html
> - shard-skl: [PASS][83] -> [FAIL][84] ([i915#1542])
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl4/igt@perf@polling-parameterized.html
> [84]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl1/ig
> t@perf@polling-parameterized.html
>
> * igt@prime_nv_api@i915_nv_double_import:
> - shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291])
> [85]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@prime_nv_api@i915_nv_double_import.html
>
> * igt@prime_vgem@basic-userptr:
> - shard-iclb: NOTRUN -> [SKIP][86] ([i915#3301])
> [86]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@prime_vgem@basic-userptr.html
>
> * igt@prime_vgem@fence-read-hang:
> - shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109295])
> [87]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@prime_vgem@fence-read-hang.html
>
> * igt@sysfs_clients@create:
> - shard-iclb: NOTRUN -> [SKIP][88] ([i915#2994])
> [88]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@sysfs_clients@create.html
>
> * igt@sysfs_clients@sema-10:
> - shard-skl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2994]) +3 similar issues
> [89]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl9/ig
> t@sysfs_clients@sema-10.html
>
> * igt@sysfs_clients@sema-25:
> - shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2994])
> [90]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl1/ig
> t@sysfs_clients@sema-25.html
>
> * igt@sysfs_clients@sema-50:
> - shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2994]) +1 similar issue
> [91]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/ig
> t@sysfs_clients@sema-50.html
>
>
> #### Possible fixes ####
>
> * igt@gem_ctx_shared@q-smoketest-all:
> - shard-glk: [DMESG-WARN][92] ([i915#118] / [i915#95]) -> [PASS][93] +2 similar issues
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk9/igt@gem_ctx_shared@q-smoketest-all.html
> [93]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk5/ig
> t@gem_ctx_shared@q-smoketest-all.html
>
> * igt@gem_exec_fair@basic-none-share@rcs0:
> - shard-iclb: [FAIL][94] ([i915#2842]) -> [PASS][95]
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
> [95]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb7/i
> gt@gem_exec_fair@basic-none-share@rcs0.html
>
> * igt@gem_exec_fair@basic-pace@vecs0:
> - shard-tglb: [FAIL][96] ([i915#2842]) -> [PASS][97]
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-tglb2/igt@gem_exec_fair@basic-pace@vecs0.html
> [97]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-tglb5/i
> gt@gem_exec_fair@basic-pace@vecs0.html
>
> * igt@gem_vm_create@destroy-race:
> - shard-tglb: [TIMEOUT][98] ([i915#2795]) -> [PASS][99]
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-tglb5/igt@gem_vm_create@destroy-race.html
> [99]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-tglb5/i
> gt@gem_vm_create@destroy-race.html
>
> * igt@i915_pm_dc@dc5-psr:
> - shard-skl: [INCOMPLETE][100] ([i915#198]) -> [PASS][101]
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl2/igt@i915_pm_dc@dc5-psr.html
> [101]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl7/ig
> t@i915_pm_dc@dc5-psr.html
>
> * igt@i915_pm_rpm@system-suspend-execbuf:
> - shard-skl: [INCOMPLETE][102] ([i915#151]) -> [PASS][103]
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl7/igt@i915_pm_rpm@system-suspend-execbuf.html
> [103]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl5/ig
> t@i915_pm_rpm@system-suspend-execbuf.html
>
> * igt@kms_cursor_crc@pipe-a-cursor-suspend:
> - shard-kbl: [DMESG-WARN][104] ([i915#180]) -> [PASS][105]
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
> [105]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl6/ig
> t@kms_cursor_crc@pipe-a-cursor-suspend.html
>
> * igt@kms_cursor_crc@pipe-c-cursor-suspend:
> - shard-apl: [DMESG-WARN][106] ([i915#180]) -> [PASS][107] +1 similar issue
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
> [107]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-apl8/ig
> t@kms_cursor_crc@pipe-c-cursor-suspend.html
>
> * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
> - shard-iclb: [FAIL][108] -> [PASS][109]
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
> [109]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb5/i
> gt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
>
> * igt@kms_fbcon_fbt@fbc-suspend:
> - shard-kbl: [INCOMPLETE][110] ([i915#155] / [i915#180] / [i915#636]) -> [PASS][111]
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
> [111]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl4/ig
> t@kms_fbcon_fbt@fbc-suspend.html
>
> * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
> - shard-skl: [FAIL][112] ([i915#53]) -> [PASS][113]
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
> [113]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/ig
> t@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
>
> * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> - shard-skl: [FAIL][114] ([fdo#108145] / [i915#265]) -> [PASS][115]
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> [115]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl2/ig
> t@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
>
> * igt@kms_plane_lowres@pipe-c-tiling-none:
> - shard-glk: [FAIL][116] ([i915#899]) -> [PASS][117]
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-glk7/igt@kms_plane_lowres@pipe-c-tiling-none.html
> [117]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-glk7/ig
> t@kms_plane_lowres@pipe-c-tiling-none.html
>
> * igt@kms_psr@psr2_primary_page_flip:
> - shard-iclb: [SKIP][118] ([fdo#109441]) -> [PASS][119] +1 similar issue
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
> [119]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_psr@psr2_primary_page_flip.html
>
> * igt@perf@blocking:
> - shard-skl: [FAIL][120] ([i915#1542]) -> [PASS][121]
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl9/igt@perf@blocking.html
> [121]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl6/ig
> t@perf@blocking.html
>
> * igt@perf@polling-small-buf:
> - shard-skl: [FAIL][122] ([i915#1722]) -> [PASS][123]
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-skl8/igt@perf@polling-small-buf.html
> [123]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-skl6/ig
> t@perf@polling-small-buf.html
>
>
> #### Warnings ####
>
> * igt@i915_pm_rc6_residency@rc6-fence:
> - shard-iclb: [WARN][124] ([i915#1804] / [i915#2684]) -> [WARN][125] ([i915#2684])
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
> [125]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb8/i
> gt@i915_pm_rc6_residency@rc6-fence.html
>
> * igt@kms_cursor_crc@pipe-b-cursor-suspend:
> - shard-kbl: [INCOMPLETE][126] ([i915#2405]) -> [DMESG-WARN][127] ([i915#180])
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
> [127]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/ig
> t@kms_cursor_crc@pipe-b-cursor-suspend.html
>
> * igt@kms_psr2_sf@cursor-plane-update-sf:
> - shard-iclb: [SKIP][128] ([i915#658]) -> [SKIP][129] ([i915#2920]) +1 similar issue
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb8/igt@kms_psr2_sf@cursor-plane-update-sf.html
> [129]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb2/i
> gt@kms_psr2_sf@cursor-plane-update-sf.html
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
> - shard-iclb: [SKIP][130] ([i915#2920]) -> [SKIP][131] ([i915#658]) +1 similar issue
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
> [131]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-iclb3/i
> gt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
>
> * igt@runner@aborted:
> - shard-kbl: ([FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#92]) -> ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([i915#180] / [i915#1814] / [i915#2292] / [i915#3002] / [i915#3363])
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@runner@aborted.html
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@runner@aborted.html
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl3/igt@runner@aborted.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl1/igt@runner@aborted.html
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-kbl6/igt@runner@aborted.html
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl7/igt@runner@aborted.html
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@runner@aborted.html
> [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@runner@aborted.html
> [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl3/igt@runner@aborted.html
> [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@runner@aborted.html
> [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl2/igt@runner@aborted.html
> [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl1/igt@runner@aborted.html
> [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/shard-kbl7/igt@runner@aborted.html
> - shard-apl: ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][149], [FAIL][150]) ([i915#3002] / [i915#3363])
> [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl6/igt@runner@aborted.html
> [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl6/igt@runner@aborted.html
> [147]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10053/shard-apl1/igt@r
> unner@
>
> == Logs ==
>
> For more details see:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20077/index.html
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