From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH 2/2] drm/i915: create a race-free reset detection Date: Wed, 5 Dec 2012 16:35:59 +0000 Message-ID: References: <1352909648-21514-1-git-send-email-daniel.vetter@ffwll.ch> <1352996243-15590-1-git-send-email-daniel.vetter@ffwll.ch> <1352996243-15590-2-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fmsmga102.fm.intel.com (mga10.intel.com [192.55.52.92]) by gabe.freedesktop.org (Postfix) with ESMTP id 84A24E656D for ; Wed, 5 Dec 2012 08:36:01 -0800 (PST) Received: by mail-oa0-f69.google.com with SMTP id j6so24504747oag.0 for ; Wed, 05 Dec 2012 08:36:00 -0800 (PST) In-Reply-To: <1352996243-15590-2-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Thu, Nov 15, 2012 at 4:17 PM, Daniel Vetter wrote: > + * Note: It is of utmost importance that the passed in seqno and reset_counter > + * values have been read by the caller in an smb safe manner. Where read-side smp? > + * locks are involved, it is sufficient to read the reset_counter before > + * unlocking the lock that protects the seqno. For lockless tricks, the > + * reset_counter _must_ be read before, and an appropriate smb_rmb must be smp_rmb()? > if (!i915_reset(dev)) { > - atomic_set(&error->reset_counter, 0); > kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); > } else { > atomic_set(&error->reset_counter, I915_WEDGED); > } > > + /* > + * After all the gem state is reset, increment the reset counter > + * and wake up everyone waiting for the reset to complete. > + * > + * Since unlock operations are a one-sided barrier only, we need > + * to insert a barrier here to order any seqno updates before > + * the counter increment. > + */ > + smp_mb__before_atomic_inc(); > + atomic_inc(&dev_priv->gpu_error.reset_counter); It seems that if the GPU can't reset, reset_counter is set to I915_WEDGED ie 0xffffffff and we increment that to 0? -- Damien