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Thu, 21 Jan 2021 20:50:19 +0000 From: "Gaurav, Kumar" To: =?iso-8859-1?Q?Ville_Syrj=E4l=E4?= , "Gupta, Anshuman" Thread-Topic: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support Thread-Index: AQHW7jbIH9N2MRh6tkiniInCJdu+rKousF4AgAPb0QCAAALfMA== Date: Thu, 21 Jan 2021 20:50:18 +0000 Message-ID: References: <20210119074320.28768-1-sean.z.huang@intel.com> <20210119074320.28768-14-sean.z.huang@intel.com> <9babc226536544f7aa7ec98e80de4b21@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: linux.intel.com; dkim=none (message not signed) header.d=none;linux.intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [98.208.38.76] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c02a1a2c-489a-4946-006a-08d8be4e29e7 x-ms-traffictypediagnostic: DM5PR11MB0057: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:10000; 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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: =?iso-8859-1?Q?lOkSz3stGt5cgxrV8yD0Xx0EXihsfZyzOr2BhqYwOIsQ8htRz0WxqyCeTM?= =?iso-8859-1?Q?ek8Iy7DHxKA1FuoHRL7BJNPvnH3C5udwfGLb7IuH3EonrEGWoZZNpiLwc9?= =?iso-8859-1?Q?IEVbS9OEsJ9Syoh30gVLwzaeWj9QO1Jm7puFZXD6B+aYfV1CaARi56vV7Z?= =?iso-8859-1?Q?0Yuj+KdnvOn+ephYhfeLb1AThg4boNWor+7OOnSiarus40AaKMFdiPcGiR?= =?iso-8859-1?Q?CwuLP/44IvQpsDired5iM4uyczhERiIsz9e4Vf/HyfkttRpWkijYj28mMI?= =?iso-8859-1?Q?v5DBFCrUvMpJGwxcasEh4OXepc3M+fRaTm+xQtgTVgr0uh+BhzqdIKZA2M?= =?iso-8859-1?Q?6LBmKrrXQhCoXMXMplK0GzM0PpxV4qJvRFSmq2ax7GmlIg3+9NgD4kMrP+?= =?iso-8859-1?Q?xTOBSqk4Qg+OpMx+cEjXB2768nNLbxT2Cz4PWKvS3FSpGMYjEB4Lr1LAFF?= =?iso-8859-1?Q?5P6c96qlwUy+iPH7ea2JXhOg60Z9IXnQd+nNEkmxErnW9eTfo9InLP/dkB?= =?iso-8859-1?Q?db0QFzFQlHqOlIOBTXH4Z44VCcdRQIR0cMiJ0pHi8jdKSw19TMcmduUjGr?= =?iso-8859-1?Q?czaFKaWMAJWDBJIMSMN/153QF8PNBPKTCzdd2KtPQflRdY2KyQOGkOzEVW?= =?iso-8859-1?Q?5VyESyQAeh6dBZHKbrmmgEuc1B+samx7WV7BRtTQ49bQj6foknSaKBgxfA?= =?iso-8859-1?Q?DTOCl6fdcll9nt12FxxugTAmVRrsgYON2Hj1EKPjR91Yu6zGd/HofnvpzW?= =?iso-8859-1?Q?OHc+dsoLRKVxH9hdid6d195atsFLehuwUtkme1auz4uz+4jl35T/DFrdgH?= =?iso-8859-1?Q?gXUnoZxxJGuXElR8uWZnKZxu5taL8Cbq0Yb7iO68k6EzoLMeOTS5dXhCgh?= =?iso-8859-1?Q?qdt4GDP26PYeVouUaUPM9bA81NS6PcCkw35JNRWijHJyYPdPyE1yIWuQkO?= =?iso-8859-1?Q?sJVbmhlgMCwvJkHDNqXE9c+8Ma0BcV9MQqH3b53P7fbbQnd4Xh2kdWyJ5o?= =?iso-8859-1?Q?MwH26C98vHdmRwDBw=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB2683.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c02a1a2c-489a-4946-006a-08d8be4e29e7 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Jan 2021 20:50:19.0797 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Z9yFFIC35Vx/cgt9uCsZFCcTOx6QiBEFLkEZke6SV6UmNHIjXRwY+m7bmpQjbEZvuRvryKfOW/wGsgmM7zl8/Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB0057 X-OriginatorOrg: intel.com Subject: Re: [Intel-gfx] [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Nikula, Jani" , "Bommu, Krishnaiah" , "Intel-gfx@lists.freedesktop.org" , "Huang, Sean Z" , "Vetter, Daniel" Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Thanks Anshuman for adding me for review. Actually, using plane Gamma is good idea to show black frame. Another optio= n could be alpha value since we know for ChromeOS protected buffer will alw= ays be flipped on overlays. Below explanation captures need for black frame in i915 Display for HWDRM p= rotected surfaces - Problem Statement - There is race condition between Ring3 and Ring0 where encrypted frame could= be flipped by i915 Display despite Ring3 checking if HWDRM session keys ar= e valid for encrypted frame. = Google Bug - BUG1 -[Intel] i915 framebuffer tracking (protected surfaces that can't be d= ecrypted are being rendered as encrypted) -b/155511255 Background - There are 4 high level pipelines working together in HWDRM playback. 1. CDM Pipeline - App CDM SW Stack -> LibVA/iHD -> i915 -> MEI -> CSME-FW = 2. Media(Audio/Video) Pipeline App Media SW Stack -> LibVA/iHD -> i915 -> GPU = 3. 3D Pipeline in Compositor App Composition SW Stack -> OpenGL/MESA/MiniGBM -> i915 -> GPU/Display 4. Display Pipeline in Compositor App Composition SW Stack -> Ozone/MiniGBM -> i915 -> Display Discussion Point - Even after Pipeline #4 is context robustness compliant there is a corner ca= se/race condition for corruption as following - BUG1 App's Composition SW Stack -> Creates Protected Context and Protected Buffe= r(MiniGBM) App's Composition SW Stack -> Supplies Protected Buffer to LibVA/iHD -> i91= 5 -> GPU -> Encrypted decoded output App's Composition SW Stack -> Gets back decode output -> Checks for context= robustness -> Submits frame for flip -> i915 Display(by the time i915 Disp= lay gets flip PAVP session is invalid despite being atomic since invalidati= on of PAVP is HW async event) -> Display HW -> Shows corruption -----Original Message----- From: Ville Syrj=E4l=E4 = Sent: Thursday, January 21, 2021 12:31 PM To: Gupta, Anshuman Cc: Huang, Sean Z ; Intel-gfx@lists.freedesktop.org= ; Nikula, Jani ; Gaurav, Kumar ; Bommu, Krishnaiah ; Vetter, Daniel Subject: Re: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support On Tue, Jan 19, 2021 at 09:35:18AM +0000, Gupta, Anshuman wrote: > Jani/Ville > I had received an offline comment form Gaurav on this patch, See = > below, > > -----Original Message----- > > From: Huang, Sean Z > > Sent: Tuesday, January 19, 2021 1:13 PM > > To: Intel-gfx@lists.freedesktop.org > > Cc: Gaurav, Kumar ; Gupta, Anshuman = > > ; Bommu, Krishnaiah = > > ; Huang, Sean Z > > Subject: [RFC-v23 13/13] drm/i915/pxp: Add plane decryption support > > = > > From: Anshuman Gupta > > = > > Add support to enable/disable PLANE_SURF Decryption Request bit. > > It requires only to enable plane decryption support when following = > > condition met. > > 1. PXP session is enabled. > > 2. Buffer object is protected. > > = > > v2: > > - Rebased to libva_cp-drm-tip_tgl_cp tree. > > - Used gen fb obj user_flags instead gem_object_metadata. [Krishna] > > = > > v3: > > - intel_pxp_gem_object_status() API changes. > > = > > Cc: Bommu Krishnaiah > > Cc: Huang Sean Z > > Cc: Gaurav Kumar > > Signed-off-by: Anshuman Gupta > > --- > > drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++--- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > 2 files changed, 19 insertions(+), 3 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c > > b/drivers/gpu/drm/i915/display/intel_sprite.c > > index cf3589fd0ddb..39f8c922ce66 100644 > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > > @@ -39,6 +39,8 @@ > > #include > > #include > > = > > +#include "pxp/intel_pxp.h" > > + > > #include "i915_drv.h" > > #include "i915_trace.h" > > #include "i915_vgpu.h" > > @@ -768,6 +770,11 @@ icl_program_input_csc(struct intel_plane *plane, > > PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } > > = > > +static bool intel_fb_obj_protected(const struct drm_i915_gem_object > > +*obj) { > > + return obj->user_flags & I915_BO_PROTECTED ? true : false; } > > + > > static void > > skl_plane_async_flip(struct intel_plane *plane, > > const struct intel_crtc_state *crtc_state, @@ -804,6 > > +811,7 @@ skl_program_plane(struct intel_plane *plane, > > u32 surf_addr =3D plane_state->color_plane[color_plane].offset; > > u32 stride =3D skl_plane_stride(plane_state, color_plane); > > const struct drm_framebuffer *fb =3D plane_state->hw.fb; > > + const struct drm_i915_gem_object *obj =3D intel_fb_obj(fb); > > int aux_plane =3D intel_main_to_aux_plane(fb, color_plane); > > int crtc_x =3D plane_state->uapi.dst.x1; > > int crtc_y =3D plane_state->uapi.dst.y1; @@ -814,7 +822,7 @@ = > > skl_program_plane(struct intel_plane *plane, > > u8 alpha =3D plane_state->hw.alpha >> 8; > > u32 plane_color_ctl =3D 0, aux_dist =3D 0; > > unsigned long irqflags; > > - u32 keymsk, keymax; > > + u32 keymsk, keymax, plane_surf; > > u32 plane_ctl =3D plane_state->ctl; > > = > > plane_ctl |=3D skl_plane_ctl_crtc(crtc_state); @@ -890,8 +898,15 @@ = > > skl_program_plane(struct intel_plane *plane, > > * the control register just before the surface register. > > */ > > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); > > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), > > - intel_plane_ggtt_offset(plane_state) + surf_addr); > > + plane_surf =3D intel_plane_ggtt_offset(plane_state) + surf_addr; > > + > > + if (intel_pxp_gem_object_status(dev_priv) && > > + intel_fb_obj_protected(obj)) > > + plane_surf |=3D PLANE_SURF_DECRYPTION_ENABLED; > Here in case of if fb obj is protected but pxp session is not enabled i.e= intel_pxp_gem_object_status() returns false, request to show the black fra= me buffer on display instead of corrupted data. > plane_surf =3D 0xXXX; //Pointer to black = > framebuffer But above approach would be a hack. > @Jani and @Ville could you please guide with the general way of handling = this as pxp session keys can be invalidated at any time. Would need such a black buffer to be always pinned into the gtt, which is s= eems a bit wasteful. We could perhaps just force the plane to output black = eg. by using the plane gamma. I think we should always have the per-plane g= amma available on skl+ universal planes. Cursor may be a different story. -- Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx