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boundary="===============0355638537==" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" --===============0355638537== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MW3PR11MB4522E99061866F53DEEFB60BA1159MW3PR11MB4522namp_" --_000_MW3PR11MB4522E99061866F53DEEFB60BA1159MW3PR11MB4522namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Tested and confirmed working on TGL-H Dell platforms. David Box Linux Power Management IAGS/SSE ________________________________ From: Gupta, Anshuman Sent: Monday, July 12, 2021 12:09 AM To: intel-gfx@lists.freedesktop.org Cc: Box, David E ; Gupta, Anshuman ; Roper, Matthew D ; Vivi, Rodrigo ; Deak, Imre Subject: [REBASED v2] drm/i915: Tweaked Wa_14010685332 for all PCHs dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform despite Wa_14010685332 original sequence, thus blocks entry to deeper s0ix = state. The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked Wa_14010685332 sequence for every PCH since PCH_CNP. v2: - removed RKL from comment and simplified condition. [Rodrigo] Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen= 11 platforms") Cc: Matt Roper Cc: Rodrigo Vivi Cc: Imre Deak Signed-off-by: Anshuman Gupta Reviewed-by: Rodrigo Vivi --- .../drm/i915/display/intel_display_power.c | 16 +++++++------- drivers/gpu/drm/i915/i915_irq.c | 21 ------------------- 2 files changed, 8 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/g= pu/drm/i915/display/intel_display_power.c index 285380079aab..28a363119560 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -6388,13 +6388,13 @@ void intel_display_power_suspend_late(struct drm_i9= 15_private *i915) if (DISPLAY_VER(i915) >=3D 11 || IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { bxt_enable_dc9(i915); - /* Tweaked Wa_14010685332:icp,jsp,mcc */ - if (INTEL_PCH_TYPE(i915) >=3D PCH_ICP && INTEL_PCH_TYPE(i91= 5) <=3D PCH_MCC) - intel_de_rmw(i915, SOUTH_CHICKEN1, - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK= _DIS); } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { hsw_enable_pc8(i915); } + + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ + if (INTEL_PCH_TYPE(i915) >=3D PCH_CNP && INTEL_PCH_TYPE(i915) < PCH= _DG1) + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SB= CLK_RUN_REFCLK_DIS); } void intel_display_power_resume_early(struct drm_i915_private *i915) @@ -6403,13 +6403,13 @@ void intel_display_power_resume_early(struct drm_i9= 15_private *i915) IS_BROXTON(i915)) { gen9_sanitize_dc_state(i915); bxt_disable_dc9(i915); - /* Tweaked Wa_14010685332:icp,jsp,mcc */ - if (INTEL_PCH_TYPE(i915) >=3D PCH_ICP && INTEL_PCH_TYPE(i91= 5) <=3D PCH_MCC) - intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK= _DIS, 0); - } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { hsw_disable_pc8(i915); } + + /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ + if (INTEL_PCH_TYPE(i915) >=3D PCH_CNP && INTEL_PCH_TYPE(i915) < PCH= _DG1) + intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0)= ; } void intel_display_power_suspend(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_ir= q.c index 1d4c683c9de9..99c75a9d7ffa 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3064,24 +3064,6 @@ static void valleyview_irq_reset(struct drm_i915_pri= vate *dev_priv) spin_unlock_irq(&dev_priv->irq_lock); } -static void cnp_display_clock_wa(struct drm_i915_private *dev_priv) -{ - struct intel_uncore *uncore =3D &dev_priv->uncore; - - /* - * Wa_14010685332:cnp/cmp,tgp,adp - * TODO: Clarify which platforms this applies to - * TODO: Figure out if this workaround can be applied in the s0ix s= uspend/resume handlers as - * on earlier platforms and whether the workaround is also needed f= or runtime suspend/resume - */ - if (INTEL_PCH_TYPE(dev_priv) =3D=3D PCH_CNP || - (INTEL_PCH_TYPE(dev_priv) >=3D PCH_TGP && INTEL_PCH_TYPE(dev_pr= iv) < PCH_DG1)) { - intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_D= IS, - SBCLK_RUN_REFCLK_DIS); - intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_D= IS, 0); - } -} - static void gen8_display_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore =3D &dev_priv->uncore; @@ -3115,7 +3097,6 @@ static void gen8_irq_reset(struct drm_i915_private *d= ev_priv) if (HAS_PCH_SPLIT(dev_priv)) ibx_irq_reset(dev_priv); - cnp_display_clock_wa(dev_priv); } static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) @@ -3159,8 +3140,6 @@ static void gen11_display_irq_reset(struct drm_i915_p= rivate *dev_priv) if (INTEL_PCH_TYPE(dev_priv) >=3D PCH_ICP) GEN3_IRQ_RESET(uncore, SDE); - - cnp_display_clock_wa(dev_priv); } static void gen11_irq_reset(struct drm_i915_private *dev_priv) -- 2.26.2 --_000_MW3PR11MB4522E99061866F53DEEFB60BA1159MW3PR11MB4522namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Tested and confirmed working on TGL-H Dell platforms.

David Box
Li= nux Power Management
IA= GS/SSE
From: Gupta, Anshuman <a= nshuman.gupta@intel.com>
Sent: Monday, July 12, 2021 12:09 AM
To: intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.= org>
Cc: Box, David E <david.e.box@intel.com>; Gupta, Anshuman <= anshuman.gupta@intel.com>; Roper, Matthew D <matthew.d.roper@intel.co= m>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; Deak, Imre <imre.de= ak@intel.com>
Subject: [REBASED v2] drm/i915: Tweaked Wa_14010685332 for all PCHs<= /font>
 
dispcnlunit1_cp_xosc_clkreq clock observed to be a= ctive on TGL-H platform
despite Wa_14010685332 original sequence, thus blocks entry to deeper s0ix = state.

The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked=
Wa_14010685332 sequence for every PCH since PCH_CNP.

v2:
- removed RKL from comment and simplified condition. [Rodrigo]

Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used o= n gen11 platforms")
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 16 +++= ++++-------
 drivers/gpu/drm/i915/i915_irq.c      &n= bsp;        | 21 -------------------
 2 files changed, 8 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/g= pu/drm/i915/display/intel_display_power.c
index 285380079aab..28a363119560 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -6388,13 +6388,13 @@ void intel_display_power_suspend_late(struct drm_i9= 15_private *i915)
         if (DISPLAY_VER(i915) >= =3D 11 || IS_GEMINILAKE(i915) ||
             IS= _BROXTON(i915)) {
            &nb= sp;    bxt_enable_dc9(i915);
-            &n= bsp;  /* Tweaked Wa_14010685332:icp,jsp,mcc */
-            &n= bsp;  if (INTEL_PCH_TYPE(i915) >=3D PCH_ICP && INTEL_PCH_TY= PE(i915) <=3D PCH_MCC)
-            &n= bsp;          intel_de_rmw(i91= 5, SOUTH_CHICKEN1,
-            &n= bsp;            = ;           SBCLK_RUN_REF= CLK_DIS, SBCLK_RUN_REFCLK_DIS);
         } else if (IS_HASWELL(i915= ) || IS_BROADWELL(i915)) {
            &nb= sp;    hsw_enable_pc8(i915);
         }
+
+       /* Tweaked Wa_14010685332:cnp,icp,jsp= ,mcc,tgp,adp */
+       if (INTEL_PCH_TYPE(i915) >=3D PCH_= CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
+            &n= bsp;  intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_R= UN_REFCLK_DIS);
 }
 
 void intel_display_power_resume_early(struct drm_i915_private *i915)<= br> @@ -6403,13 +6403,13 @@ void intel_display_power_resume_early(struct drm_i9= 15_private *i915)
             IS= _BROXTON(i915)) {
            &nb= sp;    gen9_sanitize_dc_state(i915);
            &nb= sp;    bxt_disable_dc9(i915);
-            &n= bsp;  /* Tweaked Wa_14010685332:icp,jsp,mcc */
-            &n= bsp;  if (INTEL_PCH_TYPE(i915) >=3D PCH_ICP && INTEL_PCH_TY= PE(i915) <=3D PCH_MCC)
-            &n= bsp;          intel_de_rmw(i91= 5, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
-
         } else if (IS_HASWELL(i915= ) || IS_BROADWELL(i915)) {
            &nb= sp;    hsw_disable_pc8(i915);
         }
+
+       /* Tweaked Wa_14010685332:cnp,icp,jsp= ,mcc,tgp,adp */
+       if (INTEL_PCH_TYPE(i915) >=3D PCH_= CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)
+            &n= bsp;  intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
 }
 
 void intel_display_power_suspend(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_ir= q.c
index 1d4c683c9de9..99c75a9d7ffa 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3064,24 +3064,6 @@ static void valleyview_irq_reset(struct drm_i915_pri= vate *dev_priv)
         spin_unlock_irq(&dev_p= riv->irq_lock);
 }
 
-static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
-{
-       struct intel_uncore *uncore =3D &= dev_priv->uncore;
-
-       /*
-        * Wa_14010685332:cnp/cmp,tgp,ad= p
-        * TODO: Clarify which platforms= this applies to
-        * TODO: Figure out if this work= around can be applied in the s0ix suspend/resume handlers as
-        * on earlier platforms and whet= her the workaround is also needed for runtime suspend/resume
-        */
-       if (INTEL_PCH_TYPE(dev_priv) =3D=3D P= CH_CNP ||
-           (INTEL_PCH_TY= PE(dev_priv) >=3D PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_D= G1)) {
-            &n= bsp;  intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, -            &n= bsp;            = ;       SBCLK_RUN_REFCLK_DIS);
-            &n= bsp;  intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0= );
-       }
-}
-
 static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)=
 {
         struct intel_uncore *uncor= e =3D &dev_priv->uncore;
@@ -3115,7 +3097,6 @@ static void gen8_irq_reset(struct drm_i915_private *d= ev_priv)
         if (HAS_PCH_SPLIT(dev_priv= ))
            &nb= sp;    ibx_irq_reset(dev_priv);
 
-       cnp_display_clock_wa(dev_priv);
 }
 
 static void gen11_display_irq_reset(struct drm_i915_private *dev_priv= )
@@ -3159,8 +3140,6 @@ static void gen11_display_irq_reset(struct drm_i915_p= rivate *dev_priv)
 
         if (INTEL_PCH_TYPE(dev_pri= v) >=3D PCH_ICP)
            &nb= sp;    GEN3_IRQ_RESET(uncore, SDE);
-
-       cnp_display_clock_wa(dev_priv);
 }
 
 static void gen11_irq_reset(struct drm_i915_private *dev_priv)
--
2.26.2

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