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From: Andi Shyti <andi.shyti@linux.intel.com>
To: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	"Wilson, Chris P" <chris.p.wilson@intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: limit double GT reset to pre-MTL
Date: Thu, 23 Mar 2023 01:16:08 +0100	[thread overview]
Message-ID: <ZBuaSHIRkZh3Ot6x@ashyti-mobl2.lan> (raw)
In-Reply-To: <0296ba17-6e91-76f2-4866-179feb94074b@intel.com>

Hi,

> On 3/22/2023 12:44 PM, John Harrison wrote:
> > On 3/20/2023 14:10, Daniele Ceraolo Spurio wrote:
> > > Commit 3db9d590557d ("drm/i915/gt: Reset twice") modified the code to
> > > always hit the GDRST register twice when doing a reset, with the
> > > reported aim to fix invalid post-reset engine state on some platforms
> > > (Jasperlake being the only one actually mentioned).
> >
> > It still concerns me that there are no actual details about this issue
> > from a hardware perspective as to what/why it goes wrong, the comment is
> > fully of non-definitive language - 'appears to', 'should', 'is still a
> > concern that'. And there is no w/a number associated with it. It all
> > feels extremely suspect and warrants a great big FIXME tag as a minimum.
> 
> I agree that the whole thing is unclear and we could add a FIXME, but IMO
> that is outside the scope of this patch as I'm not adding the code in
> question. This should be discussed with the original author/reviewers.

Sorry for chiming in a bit late. I'm with Daniele on this one;
the patch just takes things back to how they were before Chris's
patch, so we should look into the reasoning behind Chris's patch
itself.

As mentioned in the commit log, in Jasperlake (and only
Jasperlake), a second reset attempt is needed to clear the
register state. If I remember right, Chris discovered this
through experimentation, and I don't think any hardware folks
have documented it.

Chris can probably give more details on this.

In general, I'm on board with Daniele's patch since it's doing
what the driver has always done, which is why I gave it a quick
review already in V1.

On the other hand, the price to pay having something like this:

  loops = GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70) ? 2 : 1;

Is the following perhaps a bit more self-explanatory?

  /*
   * The big comment with explanation
   */
  if (IS_PLATFORM(i915, INTEL_JASPERLAKE))
  	/* try again */ ;

Andi

      reply	other threads:[~2023-03-23  0:16 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-20 21:10 [Intel-gfx] [PATCH 1/2] drm/i915: limit double GT reset to pre-MTL Daniele Ceraolo Spurio
2023-03-20 21:10 ` [Intel-gfx] [PATCH 2/2] drm/i915/gsc: implement wa 14015076503 Daniele Ceraolo Spurio
2023-03-22 19:44   ` John Harrison
2023-03-22 20:59     ` Ceraolo Spurio, Daniele
2023-03-22 21:09       ` John Harrison
2023-03-20 21:41 ` [Intel-gfx] [PATCH 1/2] drm/i915: limit double GT reset to pre-MTL Andi Shyti
2023-03-21 13:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] " Patchwork
2023-03-21 13:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-21 13:33 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2023-03-21 13:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-21 18:29 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-22 19:44 ` [Intel-gfx] [PATCH 1/2] " John Harrison
2023-03-22 21:03   ` Ceraolo Spurio, Daniele
2023-03-23  0:16     ` Andi Shyti [this message]

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