* [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
@ 2020-09-18 1:02 José Roberto de Souza
2020-09-18 1:02 ` [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: José Roberto de Souza @ 2020-09-18 1:02 UTC (permalink / raw)
To: intel-gfx
For platforms without selective fetch this register is reserved so
do not write 0 to it.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8a9d0bdde1bf..4e09ae61d4aa 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -942,7 +942,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
}
- if (HAS_PSR_HW_TRACKING(dev_priv))
+ if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
dev_priv->psr.psr2_sel_fetch_enabled ?
IGNORE_PSR2_HW_TRACKING : 0);
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase
2020-09-18 1:02 [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
@ 2020-09-18 1:02 ` José Roberto de Souza
2020-09-18 1:02 ` [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers José Roberto de Souza
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: José Roberto de Souza @ 2020-09-18 1:02 UTC (permalink / raw)
To: intel-gfx
Due to the debugfs flag, has_psr2 in CRTC state could have a different
value than psr.psr2_enabled and it was causing PSR2 subfeatures(DC3CO
and selective fetch) to be set to not a expected state.
So here only taking in consideration the parameter and debugfs flag
when computing PSR state, this way the CRTC state will also have
the correct state.
intel_psr_fastset_force() was already broken as
intel_psr_compute_config() was already only enabling PSR when
psr_global_enabled() and all other PSR requirements are met.
So some changes was required in this function, now it iterates over
all connectors, if it is a eDP connector and is active force a modeset
in the CRTC driving this connector, what will cause the new PSR state
to be set based on the debugfs flag.
v2:
- end connector iterator in error cases
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 73 +++++++++++++-----------
1 file changed, 41 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4e09ae61d4aa..02f74b0ddec1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -91,19 +91,14 @@ static bool psr_global_enabled(struct drm_i915_private *i915)
}
}
-static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
- const struct intel_crtc_state *crtc_state)
+static bool psr2_global_enabled(struct drm_i915_private *dev_priv)
{
- /* Cannot enable DSC and PSR2 simultaneously */
- drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable &&
- crtc_state->has_psr2);
-
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
case I915_PSR_DEBUG_DISABLE:
case I915_PSR_DEBUG_FORCE_PSR1:
return false;
default:
- return crtc_state->has_psr2;
+ return true;
}
}
@@ -729,6 +724,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
+ if (!psr2_global_enabled(dev_priv)) {
+ drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
+ return false;
+ }
+
/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
@@ -817,8 +817,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (intel_dp != dev_priv->psr.dp)
return;
- if (!psr_global_enabled(dev_priv))
+ if (!psr_global_enabled(dev_priv)) {
+ drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
return;
+ }
+
/*
* HSW spec explicitly says PSR is tied to port A.
* BDW+ platforms have a instance of PSR registers per transcoder but
@@ -959,7 +962,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled);
- dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
+ dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
@@ -1029,15 +1032,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp);
mutex_lock(&dev_priv->psr.lock);
-
- if (!psr_global_enabled(dev_priv)) {
- drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
- goto unlock;
- }
-
intel_psr_enable_locked(dev_priv, crtc_state, conn_state);
-
-unlock:
mutex_unlock(&dev_priv->psr.lock);
}
@@ -1222,8 +1217,8 @@ void intel_psr_update(struct intel_dp *intel_dp,
mutex_lock(&dev_priv->psr.lock);
- enable = crtc_state->has_psr && psr_global_enabled(dev_priv);
- psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
+ enable = crtc_state->has_psr;
+ psr2_enable = crtc_state->has_psr2;
if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
/* Force a PSR exit when enabling CRC to avoid CRC timeouts */
@@ -1320,11 +1315,12 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
{
+ struct drm_connector_list_iter conn_iter;
struct drm_device *dev = &dev_priv->drm;
struct drm_modeset_acquire_ctx ctx;
struct drm_atomic_state *state;
- struct intel_crtc *crtc;
- int err;
+ struct drm_connector *conn;
+ int err = 0;
state = drm_atomic_state_alloc(dev);
if (!state)
@@ -1334,25 +1330,38 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
state->acquire_ctx = &ctx;
retry:
- for_each_intel_crtc(dev, crtc) {
- struct intel_crtc_state *crtc_state =
- intel_atomic_get_crtc_state(state, crtc);
- if (IS_ERR(crtc_state)) {
- err = PTR_ERR(crtc_state);
- goto error;
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_for_each_connector_iter(conn, &conn_iter) {
+ struct drm_connector_state *conn_state;
+ struct drm_crtc_state *crtc_state;
+
+ if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
+ continue;
+
+ conn_state = drm_atomic_get_connector_state(state, conn);
+ if (IS_ERR(conn_state)) {
+ err = PTR_ERR(conn_state);
+ break;
}
- if (crtc_state->hw.active && crtc_state->has_psr) {
- /* Mark mode as changed to trigger a pipe->update() */
- crtc_state->uapi.mode_changed = true;
+ if (!conn_state->crtc)
+ continue;
+
+ crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
+ if (IS_ERR(crtc_state)) {
+ err = PTR_ERR(crtc_state);
break;
}
+
+ /* Mark mode as changed to trigger a pipe->update() */
+ crtc_state->mode_changed = true;
}
+ drm_connector_list_iter_end(&conn_iter);
- err = drm_atomic_commit(state);
+ if (err == 0)
+ err = drm_atomic_commit(state);
-error:
if (err == -EDEADLK) {
drm_atomic_state_clear(state);
err = drm_modeset_backoff(&ctx);
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-09-18 1:02 [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
2020-09-18 1:02 ` [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
@ 2020-09-18 1:02 ` José Roberto de Souza
2020-09-23 13:02 ` Mun, Gwan-gyeong
2020-09-18 1:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: José Roberto de Souza @ 2020-09-18 1:02 UTC (permalink / raw)
To: intel-gfx
Another step towards PSR2 selective fetch, here programming plane
selective fetch registers and MAN_TRK_CTL enabling selective fetch but
for now it is fetching the whole area of the planes.
The damaged area calculation will come as next and final step.
v2:
- removed warn on when no plane is visible in state
- removed calculations using plane damaged area in
intel_psr2_program_plane_sel_fetch()
v3:
- do not shift 16 positions the plane dst coordinates, only src is shifted
BSpec: 55229
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
drivers/gpu/drm/i915/display/intel_psr.c | 120 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
4 files changed, 134 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5a9d933e425a..96bc515497c1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct intel_plane *plane,
if (INTEL_GEN(dev_priv) >= 9)
skl_write_cursor_wm(plane, crtc_state);
+ if (!needs_modeset(crtc_state))
+ intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);
+
if (plane->cursor.base != base ||
plane->cursor.size != fbc_ctl ||
plane->cursor.cntl != cntl) {
@@ -12823,8 +12826,11 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
}
- if (!mode_changed)
- intel_psr2_sel_fetch_update(state, crtc);
+ if (!mode_changed) {
+ ret = intel_psr2_sel_fetch_update(state, crtc);
+ if (ret)
+ return ret;
+ }
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 02f74b0ddec1..deb0523f9f29 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1166,6 +1166,41 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
intel_psr_exit(dev_priv);
}
+void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum pipe pipe = plane->pipe;
+ u32 val;
+
+ if (!crtc_state->enable_psr2_sel_fetch)
+ return;
+
+ /*
+ * skl_plane_ctl_crtc()/i9xx_cursor_ctl_crtc() return 0 for gen11+, so
+ * plane_state->ctl is the right value
+ */
+ val = plane_state ? plane_state->ctl : 0;
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);
+ if (!val || plane->id == PLANE_CURSOR)
+ return;
+
+ val = plane_state->uapi.dst.y1 << 16 | plane_state->uapi.dst.x1;
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
+
+ val = plane_state->color_plane[color_plane].y << 16;
+ val |= plane_state->color_plane[color_plane].x;
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
+ val);
+
+ /* Sizes are 0 based */
+ val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) << 16;
+ val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
+ intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
+}
+
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1180,16 +1215,91 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
crtc_state->psr2_man_track_ctl);
}
-void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
+ struct drm_rect *clip, bool full_update)
+{
+ u32 val = PSR2_MAN_TRK_CTL_ENABLE;
+
+ if (full_update) {
+ val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ goto exit;
+ }
+
+ if (clip->y1 == -1)
+ goto exit;
+
+ val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
+ val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + 1);
+exit:
+ crtc_state->psr2_man_track_ctl = val;
+}
+
+static void clip_area_update(struct drm_rect *overlap_damage_area,
+ struct drm_rect *damage_area)
+{
+ if (overlap_damage_area->y1 == -1) {
+ overlap_damage_area->y1 = damage_area->y1;
+ overlap_damage_area->y2 = damage_area->y2;
+ return;
+ }
+
+ if (damage_area->y1 < overlap_damage_area->y1)
+ overlap_damage_area->y1 = damage_area->y1;
+
+ if (damage_area->y2 > overlap_damage_area->y2)
+ overlap_damage_area->y2 = damage_area->y2;
+}
+
+int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_plane_state *new_plane_state, *old_plane_state;
+ struct drm_rect pipe_clip = { .y1 = -1 };
+ struct intel_plane *plane;
+ bool full_update = false;
+ int i, ret;
if (!crtc_state->enable_psr2_sel_fetch)
- return;
+ return 0;
+
+ ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
+ if (ret)
+ return ret;
+
+ for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
+ new_plane_state, i) {
+ struct drm_rect temp;
+
+ if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
+ continue;
- crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |
- PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
+ /*
+ * TODO: Not clear how to handle planes with negative position,
+ * also planes are not updated if they have a negative X
+ * position so for now doing a full update in this cases
+ */
+ if (new_plane_state->uapi.dst.y1 < 0 ||
+ new_plane_state->uapi.dst.x1 < 0) {
+ full_update = true;
+ break;
+ }
+
+ if (!new_plane_state->uapi.visible)
+ continue;
+
+ /*
+ * For now doing a selective fetch in the whole plane area,
+ * optimizations will come in the future.
+ */
+ temp.y1 = new_plane_state->uapi.dst.y1;
+ temp.y2 = new_plane_state->uapi.dst.y2;
+ clip_area_update(&pipe_clip, &temp);
+ }
+
+ psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
+ return 0;
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 6a83c8e682e6..3eca9dcec3c0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -15,6 +15,8 @@ struct intel_crtc_state;
struct intel_dp;
struct intel_crtc;
struct intel_atomic_state;
+struct intel_plane_state;
+struct intel_plane;
#define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
@@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
-void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
+int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state);
+void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state,
+ int color_plane);
#endif /* __INTEL_PSR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 63040cb0d4e1..f12425b90607 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
(plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x);
+ if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
+ intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
+
/*
* The control register self-arms if the plane was previously
* disabled. Try to make the plane enable atomic by writing
--
2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
2020-09-18 1:02 [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
2020-09-18 1:02 ` [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
2020-09-18 1:02 ` [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers José Roberto de Souza
@ 2020-09-18 1:51 ` Patchwork
2020-09-18 3:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-09-18 1:51 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 8448 bytes --]
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
URL : https://patchwork.freedesktop.org/series/81824/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9023 -> Patchwork_18525
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/index.html
Known issues
------------
Here are the changes found in Patchwork_18525 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@basic:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-tgl-y/igt@gem_flink_basic@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-tgl-y/igt@gem_flink_basic@basic.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
- fi-skl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#2203])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
#### Possible fixes ####
* igt@gem_flink_basic@flink-lifetime:
- fi-tgl-y: [DMESG-WARN][7] ([i915#402]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-tgl-y/igt@gem_flink_basic@flink-lifetime.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][9] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-bsw-n3050: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
- fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c:
- fi-tgl-y: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-tgl-y/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
* igt@vgem_basic@unload:
- fi-skl-guc: [DMESG-WARN][19] ([i915#2203]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-skl-guc/igt@vgem_basic@unload.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-skl-guc/igt@vgem_basic@unload.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][22] ([i915#1982] / [i915#62] / [i915#92] / [i915#95])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@i915_pm_rpm@module-reload:
- fi-tgl-y: [DMESG-WARN][23] ([i915#2411]) -> [DMESG-WARN][24] ([i915#1982] / [i915#2411]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][25] ([i915#62] / [i915#92]) -> [DMESG-WARN][26] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-edid:
- fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][28] ([i915#62] / [i915#92]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92]) -> [DMESG-WARN][30] ([i915#1982] / [i915#62] / [i915#92] / [i915#95])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [DMESG-WARN][31] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][32] ([i915#95])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/fi-kbl-x1275/igt@vgem_basic@unload.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/fi-kbl-x1275/igt@vgem_basic@unload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (46 -> 40)
------------------------------
Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9023 -> Patchwork_18525
CI-20190529: 20190529
CI_DRM_9023: 5887fa2d8b9b7f6a278f9a1bc8642cb9d5d0279a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5787: 0ec962017c8131de14e0cb038f7f76b1f17ed637 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18525: 224cc64f164cdd7cddd175fa494c4cd7581859f1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
224cc64f164c drm/i915/display: Program PSR2 selective fetch registers
f0590dd9fa41 drm/i915/display: Check PSR parameter and flag only in state compute phase
d0e43279acc8 drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/index.html
[-- Attachment #1.2: Type: text/html, Size: 11658 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
2020-09-18 1:02 [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
` (2 preceding siblings ...)
2020-09-18 1:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch Patchwork
@ 2020-09-18 3:44 ` Patchwork
2020-09-18 17:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch (rev2) Patchwork
2020-09-18 18:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-09-18 3:44 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
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== Series Details ==
Series: series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
URL : https://patchwork.freedesktop.org/series/81824/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9023_full -> Patchwork_18525_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18525_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18525_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18525_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen:
- shard-hsw: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-hsw2/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-hsw2/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
Known issues
------------
Here are the changes found in Patchwork_18525_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-glk8/igt@gem_exec_whisper@basic-fds-forked-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-glk3/igt@gem_exec_whisper@basic-fds-forked-all.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-skl: [PASS][5] -> [TIMEOUT][6] ([i915#1958] / [i915#2424])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl2/igt@gem_userptr_blits@sync-unmap-cycles.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl7/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@i915_module_load@reload:
- shard-tglb: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-tglb2/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-tglb2/igt@i915_module_load@reload.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][9] -> [FAIL][10] ([i915#96])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1:
- shard-hsw: [PASS][13] -> [DMESG-WARN][14] ([i915#1982])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-hsw6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-hsw6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@ab-vga1-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-kbl3/igt@kms_flip@flip-vs-suspend@b-dp1.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-kbl2/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#2122])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#1188]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-skl: [PASS][25] -> [INCOMPLETE][26] ([i915#198])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-query-busy:
- shard-apl: [PASS][27] -> [DMESG-WARN][28] ([i915#1635] / [i915#1982]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-apl6/igt@kms_vblank@pipe-b-query-busy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-apl8/igt@kms_vblank@pipe-b-query-busy.html
* igt@prime_vgem@sync@bcs0:
- shard-tglb: [PASS][29] -> [INCOMPLETE][30] ([i915#409])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-tglb1/igt@prime_vgem@sync@bcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-tglb6/igt@prime_vgem@sync@bcs0.html
#### Possible fixes ####
* {igt@core_hotunplug@hotunbind-rebind}:
- shard-iclb: [DMESG-WARN][31] ([i915#1982]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-iclb1/igt@core_hotunplug@hotunbind-rebind.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-iclb7/igt@core_hotunplug@hotunbind-rebind.html
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-skl: [INCOMPLETE][33] ([i915#198]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl8/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_param@vm:
- shard-skl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +6 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl7/igt@gem_ctx_param@vm.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl8/igt@gem_ctx_param@vm.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [TIMEOUT][37] ([i915#1958]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl9/igt@gem_userptr_blits@unsync-unmap-cycles.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl7/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][39] ([i915#1899]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-hsw: [INCOMPLETE][41] ([CI#80]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-hsw2/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-hsw2/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [FAIL][43] ([i915#96]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1:
- shard-hsw: [DMESG-WARN][45] ([i915#1982]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-hsw6/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-hsw7/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][47] ([i915#2122]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-glk9/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50] +5 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-iclb: [INCOMPLETE][51] ([i915#2357]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-iclb2/igt@kms_flip@flip-vs-suspend@a-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-iclb6/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-kbl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen:
- shard-tglb: [DMESG-WARN][55] ([i915#1982]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [DMESG-FAIL][57] ([fdo#108145] / [i915#1982]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][61] ([i915#31]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl6/igt@kms_setmode@basic.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl5/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-query-forked-hang:
- shard-apl: [DMESG-WARN][63] ([i915#1635] / [i915#1982]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-apl7/igt@kms_vblank@pipe-c-query-forked-hang.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-apl7/igt@kms_vblank@pipe-c-query-forked-hang.html
* igt@perf@polling-parameterized:
- shard-kbl: [FAIL][65] ([i915#1542]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-kbl2/igt@perf@polling-parameterized.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-kbl6/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [FAIL][67] ([i915#1899]) -> [FAIL][68] ([i915#454])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl1/igt@i915_pm_dc@dc6-psr.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl4/igt@i915_pm_dc@dc6-psr.html
* igt@kms_flip@plain-flip-ts-check@a-edp1:
- shard-skl: [FAIL][69] ([i915#2122]) -> [DMESG-WARN][70] ([i915#1982])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9023/shard-skl10/igt@kms_flip@plain-flip-ts-check@a-edp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/shard-skl2/igt@kms_flip@plain-flip-ts-check@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2357]: https://gitlab.freedesktop.org/drm/intel/issues/2357
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
Participating hosts (11 -> 12)
------------------------------
Additional (1): pig-snb-2600
Build changes
-------------
* Linux: CI_DRM_9023 -> Patchwork_18525
CI-20190529: 20190529
CI_DRM_9023: 5887fa2d8b9b7f6a278f9a1bc8642cb9d5d0279a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5787: 0ec962017c8131de14e0cb038f7f76b1f17ed637 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18525: 224cc64f164cdd7cddd175fa494c4cd7581859f1 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18525/index.html
[-- Attachment #1.2: Type: text/html, Size: 19201 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch (rev2)
2020-09-18 1:02 [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
` (3 preceding siblings ...)
2020-09-18 3:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-09-18 17:33 ` Patchwork
2020-09-18 18:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-09-18 17:33 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 7879 bytes --]
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch (rev2)
URL : https://patchwork.freedesktop.org/series/81824/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9025 -> Patchwork_18533
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/index.html
Known issues
------------
Here are the changes found in Patchwork_18533 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@vgem_basic@sysfs:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-y/igt@vgem_basic@sysfs.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-tgl-y/igt@vgem_basic@sysfs.html
* igt@vgem_basic@unload:
- fi-kbl-x1275: [PASS][5] -> [DMESG-WARN][6] ([i915#62] / [i915#92])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@vgem_basic@unload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-kbl-x1275/igt@vgem_basic@unload.html
#### Possible fixes ####
* {igt@core_hotunplug@unbind-rebind}:
- fi-kbl-x1275: [DMESG-WARN][7] ([i915#62] / [i915#92]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-apl-guc: [DMESG-WARN][9] ([i915#1635] / [i915#1982]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-apl-guc/igt@i915_module_load@reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-apl-guc/igt@i915_module_load@reload.html
* igt@kms_busy@basic@flip:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@kms_busy@basic@flip.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-kbl-x1275/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7500u: [DMESG-WARN][13] ([i915#2203]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-kbl-7500u/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-dpms@d-dsi1:
- {fi-tgl-dsi}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-dpms@d-dsi1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-dpms@d-dsi1.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
- fi-skl-guc: [DMESG-WARN][19] ([i915#2203]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
* igt@prime_vgem@basic-read:
- fi-tgl-y: [DMESG-WARN][21] ([i915#402]) -> [PASS][22] +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-y/igt@prime_vgem@basic-read.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-tgl-y/igt@prime_vgem@basic-read.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#1982] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92] / [i915#95])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@i915_pm_rpm@module-reload:
- fi-tgl-y: [DMESG-WARN][25] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][26] ([i915#2411]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-tgl-y/igt@i915_pm_rpm@module-reload.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][27] ([i915#62] / [i915#92]) -> [DMESG-WARN][28] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-kbl-x1275: [DMESG-WARN][29] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][30] ([i915#62] / [i915#92]) +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (45 -> 40)
------------------------------
Missing (5): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9025 -> Patchwork_18533
CI-20190529: 20190529
CI_DRM_9025: 955d04e2ed0cf4bb4679f594a852cc2eebe8266b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5787: 0ec962017c8131de14e0cb038f7f76b1f17ed637 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18533: a6cca781d1311a096982b5f92e569c8f6f7ff973 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a6cca781d131 drm/i915/display: Program PSR2 selective fetch registers
94456d671376 drm/i915/display: Check PSR parameter and flag only in state compute phase
a62e4234fd43 drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/index.html
[-- Attachment #1.2: Type: text/html, Size: 10685 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch (rev2)
2020-09-18 1:02 [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
` (4 preceding siblings ...)
2020-09-18 17:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch (rev2) Patchwork
@ 2020-09-18 18:46 ` Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-09-18 18:46 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 15438 bytes --]
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch (rev2)
URL : https://patchwork.freedesktop.org/series/81824/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9025_full -> Patchwork_18533_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18533_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18533_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18533_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_backlight@fade_with_suspend:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl7/igt@i915_pm_backlight@fade_with_suspend.html
Known issues
------------
Here are the changes found in Patchwork_18533_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2389]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-glk2/igt@gem_exec_reloc@basic-many-active@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-glk7/igt@gem_exec_reloc@basic-many-active@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][5] -> [SKIP][6] ([i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-all:
- shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#1436] / [i915#716])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-kbl2/igt@gen9_exec_parse@allowed-all.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-kbl6/igt@gen9_exec_parse@allowed-all.html
* igt@i915_selftest@mock@requests:
- shard-skl: [PASS][9] -> [INCOMPLETE][10] ([i915#198] / [i915#2278])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl1/igt@i915_selftest@mock@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl3/igt@i915_selftest@mock@requests.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#180])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-kbl7/igt@i915_suspend@sysfs-reader.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-kbl3/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#177] / [i915#52] / [i915#54])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1:
- shard-hsw: [PASS][17] -> [INCOMPLETE][18] ([i915#2055])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-hsw8/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-hsw6/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#2122]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-skl: [PASS][21] -> [FAIL][22] ([i915#49])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#1188])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl8/igt@kms_hdr@bpc-switch.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl5/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@perf@polling-small-buf:
- shard-iclb: [PASS][29] -> [FAIL][30] ([i915#1722])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb6/igt@perf@polling-small-buf.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-iclb3/igt@perf@polling-small-buf.html
* igt@perf_pmu@module-unload:
- shard-tglb: [PASS][31] -> [DMESG-WARN][32] ([i915#1982]) +5 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-tglb2/igt@perf_pmu@module-unload.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-tglb5/igt@perf_pmu@module-unload.html
#### Possible fixes ####
* igt@gem_eio@suspend:
- shard-iclb: [INCOMPLETE][33] -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb3/igt@gem_eio@suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-iclb8/igt@gem_eio@suspend.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][35] ([i915#1899]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@mock@contexts:
- shard-apl: [INCOMPLETE][37] ([i915#1635] / [i915#2278]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-apl2/igt@i915_selftest@mock@contexts.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-apl7/igt@i915_selftest@mock@contexts.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][41] ([i915#72]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1:
- shard-hsw: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-hsw6/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-hsw7/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1:
- shard-hsw: [INCOMPLETE][45] ([i915#2055]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-hsw8/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-hsw8/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-vga1-hdmi-a1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: [FAIL][47] ([i915#2122]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-iclb: [DMESG-WARN][49] ([i915#1982]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][51] ([i915#1188]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [DMESG-WARN][53] ([i915#1982]) -> [PASS][54] +4 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][55] ([fdo#109642] / [fdo#111068]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb6/igt@kms_psr2_su@page_flip.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-b-query-busy:
- shard-apl: [DMESG-WARN][59] ([i915#1635] / [i915#1982]) -> [PASS][60] +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-apl7/igt@kms_vblank@pipe-b-query-busy.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-apl3/igt@kms_vblank@pipe-b-query-busy.html
#### Warnings ####
* igt@i915_pm_dc@dc6-psr:
- shard-skl: [FAIL][61] ([i915#1899]) -> [FAIL][62] ([i915#454])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl3/igt@i915_pm_dc@dc6-psr.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl10/igt@i915_pm_dc@dc6-psr.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-skl: [INCOMPLETE][63] ([i915#198] / [i915#1982]) -> [DMESG-WARN][64] ([i915#1982])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl2/igt@kms_flip@flip-vs-suspend@a-edp1.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl7/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@runner@aborted:
- shard-skl: [FAIL][65] ([i915#1436]) -> [FAIL][66] ([i915#1436] / [i915#2439])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9025/shard-skl1/igt@runner@aborted.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/shard-skl3/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
Participating hosts (11 -> 10)
------------------------------
Missing (1): pig-icl-1065g7
Build changes
-------------
* Linux: CI_DRM_9025 -> Patchwork_18533
CI-20190529: 20190529
CI_DRM_9025: 955d04e2ed0cf4bb4679f594a852cc2eebe8266b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5787: 0ec962017c8131de14e0cb038f7f76b1f17ed637 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18533: a6cca781d1311a096982b5f92e569c8f6f7ff973 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18533/index.html
[-- Attachment #1.2: Type: text/html, Size: 18059 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-09-18 1:02 ` [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers José Roberto de Souza
@ 2020-09-23 13:02 ` Mun, Gwan-gyeong
2020-09-23 17:07 ` Souza, Jose
0 siblings, 1 reply; 12+ messages in thread
From: Mun, Gwan-gyeong @ 2020-09-23 13:02 UTC (permalink / raw)
To: intel-gfx, Souza, Jose
On Thu, 2020-09-17 at 18:02 -0700, José Roberto de Souza wrote:
> Another step towards PSR2 selective fetch, here programming plane
> selective fetch registers and MAN_TRK_CTL enabling selective fetch
> but
> for now it is fetching the whole area of the planes.
> The damaged area calculation will come as next and final step.
>
> v2:
> - removed warn on when no plane is visible in state
> - removed calculations using plane damaged area in
> intel_psr2_program_plane_sel_fetch()
>
> v3:
> - do not shift 16 positions the plane dst coordinates, only src is
> shifted
>
> BSpec: 55229
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 120
> ++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> 4 files changed, 134 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5a9d933e425a..96bc515497c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> intel_plane *plane,
> if (INTEL_GEN(dev_priv) >= 9)
> skl_write_cursor_wm(plane, crtc_state);
>
> + if (!needs_modeset(crtc_state))
> + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> plane_state, 0);
> +
> if (plane->cursor.base != base ||
> plane->cursor.size != fbc_ctl ||
> plane->cursor.cntl != cntl) {
> @@ -12823,8 +12826,11 @@ static int intel_crtc_atomic_check(struct
> intel_atomic_state *state,
>
> }
>
> - if (!mode_changed)
> - intel_psr2_sel_fetch_update(state, crtc);
> + if (!mode_changed) {
> + ret = intel_psr2_sel_fetch_update(state, crtc);
> + if (ret)
> + return ret;
> + }
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 02f74b0ddec1..deb0523f9f29 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1166,6 +1166,41 @@ static void psr_force_hw_tracking_exit(struct
> drm_i915_private *dev_priv)
> intel_psr_exit(dev_priv);
> }
>
> +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> + const struct intel_crtc_state
> *crtc_state,
> + const struct intel_plane_state
> *plane_state,
> + int color_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + enum pipe pipe = plane->pipe;
> + u32 val;
> +
> + if (!crtc_state->enable_psr2_sel_fetch)
> + return;
> +
> + /*
> + * skl_plane_ctl_crtc()/i9xx_cursor_ctl_crtc() return 0 for
> gen11+, so
> + * plane_state->ctl is the right value
> + */
> + val = plane_state ? plane_state->ctl : 0;
IMHO, skl_plane_ctl() might set other ctl bits, it would be better to
have separated ctl bit value for "selective fetch ctl".
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> >id), val);
> + if (!val || plane->id == PLANE_CURSOR)
> + return;
> +
> + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> >uapi.dst.x1;
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> >id), val);
> +
> + val = plane_state->color_plane[color_plane].y << 16;
> + val |= plane_state->color_plane[color_plane].x;
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> >id),
> + val);
> +
> + /* Sizes are 0 based */
> + val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) <<
> 16;
> + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> >id), val);
> +}
> +
> void intel_psr2_program_trans_man_trk_ctl(const struct
> intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -1180,16 +1215,91 @@ void
> intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> *crtc_st
> crtc_state->psr2_man_track_ctl);
> }
>
> -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> +static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> *crtc_state,
> + struct drm_rect *clip, bool
> full_update)
> +{
> + u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> +
> + if (full_update) {
> + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> + goto exit;
> + }
> +
> + if (clip->y1 == -1)
> + goto exit;
> +
> + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
I think the start address block would be like this too.
PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(DIV_ROUND_UP(clip->y1 , 4));
> + val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip-
> >y2, 4) + 1);
> +exit:
> + crtc_state->psr2_man_track_ctl = val;
> +}
> +
> +static void clip_area_update(struct drm_rect *overlap_damage_area,
> + struct drm_rect *damage_area)
> +{
> + if (overlap_damage_area->y1 == -1) {
> + overlap_damage_area->y1 = damage_area->y1;
> + overlap_damage_area->y2 = damage_area->y2;
> + return;
> + }
> +
> + if (damage_area->y1 < overlap_damage_area->y1)
> + overlap_damage_area->y1 = damage_area->y1;
> +
> + if (damage_area->y2 > overlap_damage_area->y2)
> + overlap_damage_area->y2 = damage_area->y2;
> +}
> +
> +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_plane_state *new_plane_state, *old_plane_state;
> + struct drm_rect pipe_clip = { .y1 = -1 };
> + struct intel_plane *plane;
> + bool full_update = false;
> + int i, ret;
>
> if (!crtc_state->enable_psr2_sel_fetch)
> - return;
> + return 0;
> +
> + ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> >base);
> + if (ret)
> + return ret;
> +
> + for_each_oldnew_intel_plane_in_state(state, plane,
> old_plane_state,
> + new_plane_state, i) {
> + struct drm_rect temp;
> +
> + if (new_plane_state->uapi.crtc != crtc_state-
> >uapi.crtc)
> + continue;
>
> - crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |
> - PSR2_MAN_TRK_CTL_SF_SINGLE_FUL
> L_FRAME;
> + /*
> + * TODO: Not clear how to handle planes with negative
> position,
> + * also planes are not updated if they have a negative
> X
> + * position so for now doing a full update in this
> cases
> + */
> + if (new_plane_state->uapi.dst.y1 < 0 ||
> + new_plane_state->uapi.dst.x1 < 0) {
> + full_update = true;
> + break;
> + }
> +
> + if (!new_plane_state->uapi.visible)
> + continue;
> +
> + /*
> + * For now doing a selective fetch in the whole plane
> area,
> + * optimizations will come in the future.
> + */
> + temp.y1 = new_plane_state->uapi.dst.y1;
> + temp.y2 = new_plane_state->uapi.dst.y2;
> + clip_area_update(&pipe_clip, &temp);
> + }
> +
> + psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
> + return 0;
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 6a83c8e682e6..3eca9dcec3c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -15,6 +15,8 @@ struct intel_crtc_state;
> struct intel_dp;
> struct intel_crtc;
> struct intel_atomic_state;
> +struct intel_plane_state;
> +struct intel_plane;
>
> #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv-
> >psr.sink_support)
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> @@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct drm_connector
> *connector,
> struct drm_connector_state *old_state,
> struct drm_connector_state *new_state);
> void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
> -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> void intel_psr2_program_trans_man_trk_ctl(const struct
> intel_crtc_state *crtc_state);
> +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> + const struct intel_crtc_state
> *crtc_state,
> + const struct intel_plane_state
> *plane_state,
> + int color_plane);
>
> #endif /* __INTEL_PSR_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 63040cb0d4e1..f12425b90607 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe,
> plane_id),
> (plane_state->color_plane[1].y << 16)
> | plane_state->color_plane[1].x);
>
> + if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> plane_state, color_plane);
> +
> /*
> * The control register self-arms if the plane was previously
> * disabled. Try to make the plane enable atomic by writing
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-09-23 13:02 ` Mun, Gwan-gyeong
@ 2020-09-23 17:07 ` Souza, Jose
2020-09-23 17:09 ` Souza, Jose
0 siblings, 1 reply; 12+ messages in thread
From: Souza, Jose @ 2020-09-23 17:07 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx
On Wed, 2020-09-23 at 14:02 +0100, Mun, Gwan-gyeong wrote:
> On Thu, 2020-09-17 at 18:02 -0700, José Roberto de Souza wrote:
> > Another step towards PSR2 selective fetch, here programming plane
> > selective fetch registers and MAN_TRK_CTL enabling selective fetch
> > but
> > for now it is fetching the whole area of the planes.
> > The damaged area calculation will come as next and final step.
> >
> > v2:
> > - removed warn on when no plane is visible in state
> > - removed calculations using plane damaged area in
> > intel_psr2_program_plane_sel_fetch()
> >
> > v3:
> > - do not shift 16 positions the plane dst coordinates, only src is
> > shifted
> >
> > BSpec: 55229
> > Cc: Gwan-gyeong Mun <
> > gwan-gyeong.mun@intel.com
> > >
> > Cc: Ville Syrjälä <
> > ville.syrjala@linux.intel.com
> > >
> > Signed-off-by: José Roberto de Souza <
> > jose.souza@intel.com
> > >
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> > drivers/gpu/drm/i915/display/intel_psr.c | 120
> > ++++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> > drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> > 4 files changed, 134 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 5a9d933e425a..96bc515497c1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> > intel_plane *plane,
> > if (INTEL_GEN(dev_priv) >= 9)
> > skl_write_cursor_wm(plane, crtc_state);
> >
> > + if (!needs_modeset(crtc_state))
> > + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> > plane_state, 0);
> > +
> > if (plane->cursor.base != base ||
> > plane->cursor.size != fbc_ctl ||
> > plane->cursor.cntl != cntl) {
> > @@ -12823,8 +12826,11 @@ static int intel_crtc_atomic_check(struct
> > intel_atomic_state *state,
> >
> > }
> >
> > - if (!mode_changed)
> > - intel_psr2_sel_fetch_update(state, crtc);
> > + if (!mode_changed) {
> > + ret = intel_psr2_sel_fetch_update(state, crtc);
> > + if (ret)
> > + return ret;
> > + }
> >
> > return 0;
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 02f74b0ddec1..deb0523f9f29 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1166,6 +1166,41 @@ static void psr_force_hw_tracking_exit(struct
> > drm_i915_private *dev_priv)
> > intel_psr_exit(dev_priv);
> > }
> >
> > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct intel_plane_state
> > *plane_state,
> > + int color_plane)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + enum pipe pipe = plane->pipe;
> > + u32 val;
> > +
> > + if (!crtc_state->enable_psr2_sel_fetch)
> > + return;
> > +
> > + /*
> > + * skl_plane_ctl_crtc()/i9xx_cursor_ctl_crtc() return 0 for
> > gen11+, so
> > + * plane_state->ctl is the right value
> > + */
> > + val = plane_state ? plane_state->ctl : 0;
>
> IMHO, skl_plane_ctl() might set other ctl bits, it would be better to
> have separated ctl bit value for "selective fetch ctl".
Like said all other bits are spares so can be set without issues but okay will a "plane_state->ctl & PLANE_SEL_FETCH_CTL_ENABLE".
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> > > id), val);
> >
> > + if (!val || plane->id == PLANE_CURSOR)
> > + return;
> > +
> > + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> > > uapi.dst.x1;
> >
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> > > id), val);
> >
> > +
> > + val = plane_state->color_plane[color_plane].y << 16;
> > + val |= plane_state->color_plane[color_plane].x;
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> > > id),
> >
> > + val);
> > +
> > + /* Sizes are 0 based */
> > + val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) <<
> > 16;
> > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> > > id), val);
> >
> > +}
> > +
> > void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state)
> > {
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > @@ -1180,16 +1215,91 @@ void
> > intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> > *crtc_st
> > crtc_state->psr2_man_track_ctl);
> > }
> >
> > -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc)
> > +static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> > *crtc_state,
> > + struct drm_rect *clip, bool
> > full_update)
> > +{
> > + u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > +
> > + if (full_update) {
> > + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > + goto exit;
> > + }
> > +
> > + if (clip->y1 == -1)
> > + goto exit;
> > +
> > + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
>
> I think the start address block would be like this too.
> PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(DIV_ROUND_UP(clip->y1 , 4));
This would not match for numbers that divide by 4.
y pos 0 = region 1y pos 1 = region 1
y pos 4 = region 2
> > + val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip-
> > > y2, 4) + 1);
> >
> > +exit:
> > + crtc_state->psr2_man_track_ctl = val;
> > +}
> > +
> > +static void clip_area_update(struct drm_rect *overlap_damage_area,
> > + struct drm_rect *damage_area)
> > +{
> > + if (overlap_damage_area->y1 == -1) {
> > + overlap_damage_area->y1 = damage_area->y1;
> > + overlap_damage_area->y2 = damage_area->y2;
> > + return;
> > + }
> > +
> > + if (damage_area->y1 < overlap_damage_area->y1)
> > + overlap_damage_area->y1 = damage_area->y1;
> > +
> > + if (damage_area->y2 > overlap_damage_area->y2)
> > + overlap_damage_area->y2 = damage_area->y2;
> > +}
> > +
> > +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc)
> > {
> > struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + struct intel_plane_state *new_plane_state, *old_plane_state;
> > + struct drm_rect pipe_clip = { .y1 = -1 };
> > + struct intel_plane *plane;
> > + bool full_update = false;
> > + int i, ret;
> >
> > if (!crtc_state->enable_psr2_sel_fetch)
> > - return;
> > + return 0;
> > +
> > + ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> > > base);
> >
> > + if (ret)
> > + return ret;
> > +
> > + for_each_oldnew_intel_plane_in_state(state, plane,
> > old_plane_state,
> > + new_plane_state, i) {
> > + struct drm_rect temp;
> > +
> > + if (new_plane_state->uapi.crtc != crtc_state-
> > > uapi.crtc)
> >
> > + continue;
> >
> > - crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |
> > - PSR2_MAN_TRK_CTL_SF_SINGLE_FUL
> > L_FRAME;
> > + /*
> > + * TODO: Not clear how to handle planes with negative
> > position,
> > + * also planes are not updated if they have a negative
> > X
> > + * position so for now doing a full update in this
> > cases
> > + */
> > + if (new_plane_state->uapi.dst.y1 < 0 ||
> > + new_plane_state->uapi.dst.x1 < 0) {
> > + full_update = true;
> > + break;
> > + }
> > +
> > + if (!new_plane_state->uapi.visible)
> > + continue;
> > +
> > + /*
> > + * For now doing a selective fetch in the whole plane
> > area,
> > + * optimizations will come in the future.
> > + */
> > + temp.y1 = new_plane_state->uapi.dst.y1;
> > + temp.y2 = new_plane_state->uapi.dst.y2;
> > + clip_area_update(&pipe_clip, &temp);
> > + }
> > +
> > + psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
> > + return 0;
> > }
> >
> > /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 6a83c8e682e6..3eca9dcec3c0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -15,6 +15,8 @@ struct intel_crtc_state;
> > struct intel_dp;
> > struct intel_crtc;
> > struct intel_atomic_state;
> > +struct intel_plane_state;
> > +struct intel_plane;
> >
> > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv-
> > > psr.sink_support)
> >
> > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > @@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct drm_connector
> > *connector,
> > struct drm_connector_state *old_state,
> > struct drm_connector_state *new_state);
> > void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
> > -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc);
> > +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc);
> > void intel_psr2_program_trans_man_trk_ctl(const struct
> > intel_crtc_state *crtc_state);
> > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > + const struct intel_crtc_state
> > *crtc_state,
> > + const struct intel_plane_state
> > *plane_state,
> > + int color_plane);
> >
> > #endif /* __INTEL_PSR_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 63040cb0d4e1..f12425b90607 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane *plane,
> > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe,
> > plane_id),
> > (plane_state->color_plane[1].y << 16)
> > > plane_state->color_plane[1].x);
> >
> >
> > + if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> > + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> > plane_state, color_plane);
> > +
> > /*
> > * The control register self-arms if the plane was previously
> > * disabled. Try to make the plane enable atomic by writing
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-09-23 17:07 ` Souza, Jose
@ 2020-09-23 17:09 ` Souza, Jose
2020-09-24 13:27 ` Mun, Gwan-gyeong
0 siblings, 1 reply; 12+ messages in thread
From: Souza, Jose @ 2020-09-23 17:09 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx
On Wed, 2020-09-23 at 10:10 -0700, José Roberto de Souza wrote:
> On Wed, 2020-09-23 at 14:02 +0100, Mun, Gwan-gyeong wrote:
> > On Thu, 2020-09-17 at 18:02 -0700, José Roberto de Souza wrote:
> > > Another step towards PSR2 selective fetch, here programming plane
> > > selective fetch registers and MAN_TRK_CTL enabling selective fetch
> > > but
> > > for now it is fetching the whole area of the planes.
> > > The damaged area calculation will come as next and final step.
> > >
> > > v2:
> > > - removed warn on when no plane is visible in state
> > > - removed calculations using plane damaged area in
> > > intel_psr2_program_plane_sel_fetch()
> > >
> > > v3:
> > > - do not shift 16 positions the plane dst coordinates, only src is
> > > shifted
> > >
> > > BSpec: 55229
> > > Cc: Gwan-gyeong Mun <
> > > gwan-gyeong.mun@intel.com
> > >
> > >
> > > Cc: Ville Syrjälä <
> > > ville.syrjala@linux.intel.com
> > >
> > >
> > > Signed-off-by: José Roberto de Souza <
> > > jose.souza@intel.com
> > >
> > >
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> > > drivers/gpu/drm/i915/display/intel_psr.c | 120
> > > ++++++++++++++++++-
> > > drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> > > 4 files changed, 134 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 5a9d933e425a..96bc515497c1 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> > > intel_plane *plane,
> > > if (INTEL_GEN(dev_priv) >= 9)
> > > skl_write_cursor_wm(plane, crtc_state);
> > >
> > > + if (!needs_modeset(crtc_state))
> > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> > > plane_state, 0);
> > > +
> > > if (plane->cursor.base != base ||
> > > plane->cursor.size != fbc_ctl ||
> > > plane->cursor.cntl != cntl) {
> > > @@ -12823,8 +12826,11 @@ static int intel_crtc_atomic_check(struct
> > > intel_atomic_state *state,
> > >
> > > }
> > >
> > > - if (!mode_changed)
> > > - intel_psr2_sel_fetch_update(state, crtc);
> > > + if (!mode_changed) {
> > > + ret = intel_psr2_sel_fetch_update(state, crtc);
> > > + if (ret)
> > > + return ret;
> > > + }
> > >
> > > return 0;
> > > }
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 02f74b0ddec1..deb0523f9f29 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1166,6 +1166,41 @@ static void psr_force_hw_tracking_exit(struct
> > > drm_i915_private *dev_priv)
> > > intel_psr_exit(dev_priv);
> > > }
> > >
> > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > > + const struct intel_crtc_state
> > > *crtc_state,
> > > + const struct intel_plane_state
> > > *plane_state,
> > > + int color_plane)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > + enum pipe pipe = plane->pipe;
> > > + u32 val;
> > > +
> > > + if (!crtc_state->enable_psr2_sel_fetch)
> > > + return;
> > > +
> > > + /*
> > > + * skl_plane_ctl_crtc()/i9xx_cursor_ctl_crtc() return 0 for
> > > gen11+, so
> > > + * plane_state->ctl is the right value
> > > + */
> > > + val = plane_state ? plane_state->ctl : 0;
> >
> > IMHO, skl_plane_ctl() might set other ctl bits, it would be better to
> > have separated ctl bit value for "selective fetch ctl".
>
> Like said all other bits are spares so can be set without issues but okay will a "plane_state->ctl & PLANE_SEL_FETCH_CTL_ENABLE".
Please take a look to the answer of your other comment bellow, with the change above can I have your rv-b?
>
> > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane-
> > > > id), val);
> > >
> > > + if (!val || plane->id == PLANE_CURSOR)
> > > + return;
> > > +
> > > + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> > > > uapi.dst.x1;
> > >
> > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane-
> > > > id), val);
> > >
> > > +
> > > + val = plane_state->color_plane[color_plane].y << 16;
> > > + val |= plane_state->color_plane[color_plane].x;
> > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane-
> > > > id),
> > >
> > > + val);
> > > +
> > > + /* Sizes are 0 based */
> > > + val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) <<
> > > 16;
> > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane-
> > > > id), val);
> > >
> > > +}
> > > +
> > > void intel_psr2_program_trans_man_trk_ctl(const struct
> > > intel_crtc_state *crtc_state)
> > > {
> > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > @@ -1180,16 +1215,91 @@ void
> > > intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> > > *crtc_st
> > > crtc_state->psr2_man_track_ctl);
> > > }
> > >
> > > -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > > - struct intel_crtc *crtc)
> > > +static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> > > *crtc_state,
> > > + struct drm_rect *clip, bool
> > > full_update)
> > > +{
> > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > > +
> > > + if (full_update) {
> > > + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > + goto exit;
> > > + }
> > > +
> > > + if (clip->y1 == -1)
> > > + goto exit;
> > > +
> > > + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
> >
> > I think the start address block would be like this too.
> > PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(DIV_ROUND_UP(clip->y1 , 4));
>
> This would not match for numbers that divide by 4.
> y pos 0 = region 1y pos 1 = region 1
> y pos 4 = region 2
>
>
> > > + val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip-
> > > > y2, 4) + 1);
> > >
> > > +exit:
> > > + crtc_state->psr2_man_track_ctl = val;
> > > +}
> > > +
> > > +static void clip_area_update(struct drm_rect *overlap_damage_area,
> > > + struct drm_rect *damage_area)
> > > +{
> > > + if (overlap_damage_area->y1 == -1) {
> > > + overlap_damage_area->y1 = damage_area->y1;
> > > + overlap_damage_area->y2 = damage_area->y2;
> > > + return;
> > > + }
> > > +
> > > + if (damage_area->y1 < overlap_damage_area->y1)
> > > + overlap_damage_area->y1 = damage_area->y1;
> > > +
> > > + if (damage_area->y2 > overlap_damage_area->y2)
> > > + overlap_damage_area->y2 = damage_area->y2;
> > > +}
> > > +
> > > +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > > + struct intel_crtc *crtc)
> > > {
> > > struct intel_crtc_state *crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > > + struct intel_plane_state *new_plane_state, *old_plane_state;
> > > + struct drm_rect pipe_clip = { .y1 = -1 };
> > > + struct intel_plane *plane;
> > > + bool full_update = false;
> > > + int i, ret;
> > >
> > > if (!crtc_state->enable_psr2_sel_fetch)
> > > - return;
> > > + return 0;
> > > +
> > > + ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> > > > base);
> > >
> > > + if (ret)
> > > + return ret;
> > > +
> > > + for_each_oldnew_intel_plane_in_state(state, plane,
> > > old_plane_state,
> > > + new_plane_state, i) {
> > > + struct drm_rect temp;
> > > +
> > > + if (new_plane_state->uapi.crtc != crtc_state-
> > > > uapi.crtc)
> > >
> > > + continue;
> > >
> > > - crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE |
> > > - PSR2_MAN_TRK_CTL_SF_SINGLE_FUL
> > > L_FRAME;
> > > + /*
> > > + * TODO: Not clear how to handle planes with negative
> > > position,
> > > + * also planes are not updated if they have a negative
> > > X
> > > + * position so for now doing a full update in this
> > > cases
> > > + */
> > > + if (new_plane_state->uapi.dst.y1 < 0 ||
> > > + new_plane_state->uapi.dst.x1 < 0) {
> > > + full_update = true;
> > > + break;
> > > + }
> > > +
> > > + if (!new_plane_state->uapi.visible)
> > > + continue;
> > > +
> > > + /*
> > > + * For now doing a selective fetch in the whole plane
> > > area,
> > > + * optimizations will come in the future.
> > > + */
> > > + temp.y1 = new_plane_state->uapi.dst.y1;
> > > + temp.y2 = new_plane_state->uapi.dst.y2;
> > > + clip_area_update(&pipe_clip, &temp);
> > > + }
> > > +
> > > + psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
> > > + return 0;
> > > }
> > >
> > > /**
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index 6a83c8e682e6..3eca9dcec3c0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -15,6 +15,8 @@ struct intel_crtc_state;
> > > struct intel_dp;
> > > struct intel_crtc;
> > > struct intel_atomic_state;
> > > +struct intel_plane_state;
> > > +struct intel_plane;
> > >
> > > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv-
> > > > psr.sink_support)
> > >
> > > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > > @@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct drm_connector
> > > *connector,
> > > struct drm_connector_state *old_state,
> > > struct drm_connector_state *new_state);
> > > void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp);
> > > -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > > - struct intel_crtc *crtc);
> > > +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > > + struct intel_crtc *crtc);
> > > void intel_psr2_program_trans_man_trk_ctl(const struct
> > > intel_crtc_state *crtc_state);
> > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> > > + const struct intel_crtc_state
> > > *crtc_state,
> > > + const struct intel_plane_state
> > > *plane_state,
> > > + int color_plane);
> > >
> > > #endif /* __INTEL_PSR_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index 63040cb0d4e1..f12425b90607 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane *plane,
> > > intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe,
> > > plane_id),
> > > (plane_state->color_plane[1].y << 16)
> > > > plane_state->color_plane[1].x);
> > >
> > >
> > > + if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> > > + intel_psr2_program_plane_sel_fetch(plane, crtc_state,
> > > plane_state, color_plane);
> > > +
> > > /*
> > > * The control register self-arms if the plane was previously
> > > * disabled. Try to make the plane enable atomic by writing
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-09-23 17:09 ` Souza, Jose
@ 2020-09-24 13:27 ` Mun, Gwan-gyeong
2020-09-24 17:38 ` Souza, Jose
0 siblings, 1 reply; 12+ messages in thread
From: Mun, Gwan-gyeong @ 2020-09-24 13:27 UTC (permalink / raw)
To: intel-gfx, Souza, Jose
On Wed, 2020-09-23 at 10:09 -0700, Souza, Jose wrote:
> On Wed, 2020-09-23 at 10:10 -0700, José Roberto de Souza wrote:
> > On Wed, 2020-09-23 at 14:02 +0100, Mun, Gwan-gyeong wrote:
> > > On Thu, 2020-09-17 at 18:02 -0700, José Roberto de Souza wrote:
> > > > Another step towards PSR2 selective fetch, here programming
> > > > plane
> > > > selective fetch registers and MAN_TRK_CTL enabling selective
> > > > fetch
> > > > but
> > > > for now it is fetching the whole area of the planes.
> > > > The damaged area calculation will come as next and final step.
> > > >
> > > > v2:
> > > > - removed warn on when no plane is visible in state
> > > > - removed calculations using plane damaged area in
> > > > intel_psr2_program_plane_sel_fetch()
> > > >
> > > > v3:
> > > > - do not shift 16 positions the plane dst coordinates, only src
> > > > is
> > > > shifted
> > > >
> > > > BSpec: 55229
> > > > Cc: Gwan-gyeong Mun <
> > > > gwan-gyeong.mun@intel.com
> > > >
> > > >
> > > > Cc: Ville Syrjälä <
> > > > ville.syrjala@linux.intel.com
> > > >
> > > >
> > > > Signed-off-by: José Roberto de Souza <
> > > > jose.souza@intel.com
> > > >
> > > >
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 120
> > > > ++++++++++++++++++-
> > > > drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> > > > drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> > > > 4 files changed, 134 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 5a9d933e425a..96bc515497c1 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> > > > intel_plane *plane,
> > > > if (INTEL_GEN(dev_priv) >= 9)
> > > > skl_write_cursor_wm(plane, crtc_state);
> > > >
> > > > + if (!needs_modeset(crtc_state))
> > > > + intel_psr2_program_plane_sel_fetch(plane,
> > > > crtc_state,
> > > > plane_state, 0);
> > > > +
> > > > if (plane->cursor.base != base ||
> > > > plane->cursor.size != fbc_ctl ||
> > > > plane->cursor.cntl != cntl) {
> > > > @@ -12823,8 +12826,11 @@ static int
> > > > intel_crtc_atomic_check(struct
> > > > intel_atomic_state *state,
> > > >
> > > > }
> > > >
> > > > - if (!mode_changed)
> > > > - intel_psr2_sel_fetch_update(state, crtc);
> > > > + if (!mode_changed) {
> > > > + ret = intel_psr2_sel_fetch_update(state, crtc);
> > > > + if (ret)
> > > > + return ret;
> > > > + }
> > > >
> > > > return 0;
> > > > }
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 02f74b0ddec1..deb0523f9f29 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -1166,6 +1166,41 @@ static void
> > > > psr_force_hw_tracking_exit(struct
> > > > drm_i915_private *dev_priv)
> > > > intel_psr_exit(dev_priv);
> > > > }
> > > >
> > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane
> > > > *plane,
> > > > + const struct
> > > > intel_crtc_state
> > > > *crtc_state,
> > > > + const struct
> > > > intel_plane_state
> > > > *plane_state,
> > > > + int color_plane)
> > > > +{
> > > > + struct drm_i915_private *dev_priv = to_i915(plane-
> > > > >base.dev);
> > > > + enum pipe pipe = plane->pipe;
> > > > + u32 val;
> > > > +
> > > > + if (!crtc_state->enable_psr2_sel_fetch)
> > > > + return;
> > > > +
> > > > + /*
> > > > + * skl_plane_ctl_crtc()/i9xx_cursor_ctl_crtc() return 0
> > > > for
> > > > gen11+, so
> > > > + * plane_state->ctl is the right value
> > > > + */
> > > > + val = plane_state ? plane_state->ctl : 0;
> > >
> > > IMHO, skl_plane_ctl() might set other ctl bits, it would be
> > > better to
> > > have separated ctl bit value for "selective fetch ctl".
> >
> > Like said all other bits are spares so can be set without issues
> > but okay will a "plane_state->ctl & PLANE_SEL_FETCH_CTL_ENABLE".
>
> Please take a look to the answer of your other comment bellow, with
> the change above can I have your rv-b?
The purpose and composition of bits of Register_SEL_FETCH_PLANE_CTL is
different from Register_PLANE_CTL.
And the Spares bits of Register_SEL_FETCH_PLANE_CTL might be used for
other purpose.
(And we current don't know the side effect of setting of Spares bit of
Register_SEL_FETCH_PLANE_CTL )
therefor I recommend "Read and Modify" to SEL_FETCH_PLANE_CTL.
>
> > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe,
> > > > plane-
> > > > > id), val);
> > > >
> > > > + if (!val || plane->id == PLANE_CURSOR)
> > > > + return;
> > > > +
> > > > + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> > > > > uapi.dst.x1;
> > > >
> > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe,
> > > > plane-
> > > > > id), val);
> > > >
> > > > +
> > > > + val = plane_state->color_plane[color_plane].y << 16;
> > > > + val |= plane_state->color_plane[color_plane].x;
> > > > + intel_de_write_fw(dev_priv,
> > > > PLANE_SEL_FETCH_OFFSET(pipe, plane-
> > > > > id),
> > > >
> > > > + val);
> > > > +
> > > > + /* Sizes are 0 based */
> > > > + val = ((drm_rect_height(&plane_state->uapi.src) >> 16)
> > > > - 1) <<
> > > > 16;
> > > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) -
> > > > 1;
> > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe,
> > > > plane-
> > > > > id), val);
> > > >
> > > > +}
> > > > +
> > > > void intel_psr2_program_trans_man_trk_ctl(const struct
> > > > intel_crtc_state *crtc_state)
> > > > {
> > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> > > > >uapi.crtc);
> > > > @@ -1180,16 +1215,91 @@ void
> > > > intel_psr2_program_trans_man_trk_ctl(const struct
> > > > intel_crtc_state
> > > > *crtc_st
> > > > crtc_state->psr2_man_track_ctl);
> > > > }
> > > >
> > > > -void intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > > *state,
> > > > - struct intel_crtc *crtc)
> > > > +static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> > > > *crtc_state,
> > > > + struct drm_rect *clip, bool
> > > > full_update)
> > > > +{
> > > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > > > +
> > > > + if (full_update) {
> > > > + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > > + goto exit;
> > > > + }
> > > > +
> > > > + if (clip->y1 == -1)
> > > > + goto exit;
> > > > +
> > > > + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > > + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 /
> > > > 4 + 1);
> > >
> > > I think the start address block would be like this too.
> > > PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(DIV_ROUND_UP(clip->y1 ,
> > > 4));
> >
> > This would not match for numbers that divide by 4.
> > y pos 0 = region 1y pos 1 = region 1
> > y pos 4 = region 2
> >
yes. you are right.
> >
> > > > + val |=
> > > > PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip-
> > > > > y2, 4) + 1);
> > > >
> > > > +exit:
> > > > + crtc_state->psr2_man_track_ctl = val;
> > > > +}
> > > > +
> > > > +static void clip_area_update(struct drm_rect
> > > > *overlap_damage_area,
> > > > + struct drm_rect *damage_area)
> > > > +{
> > > > + if (overlap_damage_area->y1 == -1) {
> > > > + overlap_damage_area->y1 = damage_area->y1;
> > > > + overlap_damage_area->y2 = damage_area->y2;
> > > > + return;
> > > > + }
> > > > +
> > > > + if (damage_area->y1 < overlap_damage_area->y1)
> > > > + overlap_damage_area->y1 = damage_area->y1;
> > > > +
> > > > + if (damage_area->y2 > overlap_damage_area->y2)
> > > > + overlap_damage_area->y2 = damage_area->y2;
> > > > +}
> > > > +
> > > > +int intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > > *state,
> > > > + struct intel_crtc *crtc)
> > > > {
> > > > struct intel_crtc_state *crtc_state =
> > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > > + struct intel_plane_state *new_plane_state,
> > > > *old_plane_state;
> > > > + struct drm_rect pipe_clip = { .y1 = -1 };
> > > > + struct intel_plane *plane;
> > > > + bool full_update = false;
> > > > + int i, ret;
> > > >
> > > > if (!crtc_state->enable_psr2_sel_fetch)
> > > > - return;
> > > > + return 0;
> > > > +
> > > > + ret = drm_atomic_add_affected_planes(&state->base,
> > > > &crtc-
> > > > > base);
> > > >
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + for_each_oldnew_intel_plane_in_state(state, plane,
> > > > old_plane_state,
> > > > + new_plane_state,
> > > > i) {
> > > > + struct drm_rect temp;
> > > > +
> > > > + if (new_plane_state->uapi.crtc != crtc_state-
> > > > > uapi.crtc)
> > > >
> > > > + continue;
> > > >
> > > > - crtc_state->psr2_man_track_ctl =
> > > > PSR2_MAN_TRK_CTL_ENABLE |
> > > > - PSR2_MAN_TRK_CTL_SF_SI
> > > > NGLE_FUL
> > > > L_FRAME;
> > > > + /*
> > > > + * TODO: Not clear how to handle planes with
> > > > negative
> > > > position,
> > > > + * also planes are not updated if they have a
> > > > negative
> > > > X
> > > > + * position so for now doing a full update in
> > > > this
> > > > cases
> > > > + */
> > > > + if (new_plane_state->uapi.dst.y1 < 0 ||
> > > > + new_plane_state->uapi.dst.x1 < 0) {
> > > > + full_update = true;
> > > > + break;
> > > > + }
> > > > +
> > > > + if (!new_plane_state->uapi.visible)
> > > > + continue;
> > > > +
> > > > + /*
> > > > + * For now doing a selective fetch in the whole
> > > > plane
> > > > area,
> > > > + * optimizations will come in the future.
> > > > + */
> > > > + temp.y1 = new_plane_state->uapi.dst.y1;
> > > > + temp.y2 = new_plane_state->uapi.dst.y2;
> > > > + clip_area_update(&pipe_clip, &temp);
> > > > + }
> > > > +
> > > > + psr2_man_trk_ctl_calc(crtc_state, &pipe_clip,
> > > > full_update);
> > > > + return 0;
> > > > }
> > > >
> > > > /**
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > index 6a83c8e682e6..3eca9dcec3c0 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > @@ -15,6 +15,8 @@ struct intel_crtc_state;
> > > > struct intel_dp;
> > > > struct intel_crtc;
> > > > struct intel_atomic_state;
> > > > +struct intel_plane_state;
> > > > +struct intel_plane;
> > > >
> > > > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv-
> > > > > psr.sink_support)
> > > >
> > > > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > > > @@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct
> > > > drm_connector
> > > > *connector,
> > > > struct drm_connector_state
> > > > *old_state,
> > > > struct drm_connector_state
> > > > *new_state);
> > > > void intel_psr_set_force_mode_changed(struct intel_dp
> > > > *intel_dp);
> > > > -void intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > > *state,
> > > > - struct intel_crtc *crtc);
> > > > +int intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > > *state,
> > > > + struct intel_crtc *crtc);
> > > > void intel_psr2_program_trans_man_trk_ctl(const struct
> > > > intel_crtc_state *crtc_state);
> > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane
> > > > *plane,
> > > > + const struct
> > > > intel_crtc_state
> > > > *crtc_state,
> > > > + const struct
> > > > intel_plane_state
> > > > *plane_state,
> > > > + int color_plane);
> > > >
> > > > #endif /* __INTEL_PSR_H__ */
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > index 63040cb0d4e1..f12425b90607 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > @@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane
> > > > *plane,
> > > > intel_de_write_fw(dev_priv,
> > > > PLANE_AUX_OFFSET(pipe,
> > > > plane_id),
> > > > (plane_state-
> > > > >color_plane[1].y << 16)
> > > > > plane_state->color_plane[1].x);
> > > >
> > > >
> > > > + if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> > > > + intel_psr2_program_plane_sel_fetch(plane,
> > > > crtc_state,
> > > > plane_state, color_plane);
> > > > +
> > > > /*
> > > > * The control register self-arms if the plane was
> > > > previously
> > > > * disabled. Try to make the plane enable atomic by
> > > > writing
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers
2020-09-24 13:27 ` Mun, Gwan-gyeong
@ 2020-09-24 17:38 ` Souza, Jose
0 siblings, 0 replies; 12+ messages in thread
From: Souza, Jose @ 2020-09-24 17:38 UTC (permalink / raw)
To: Mun, Gwan-gyeong, intel-gfx
On Thu, 2020-09-24 at 14:27 +0100, Mun, Gwan-gyeong wrote:
> On Wed, 2020-09-23 at 10:09 -0700, Souza, Jose wrote:
> > On Wed, 2020-09-23 at 10:10 -0700, José Roberto de Souza wrote:
> > > On Wed, 2020-09-23 at 14:02 +0100, Mun, Gwan-gyeong wrote:
> > > > On Thu, 2020-09-17 at 18:02 -0700, José Roberto de Souza wrote:
> > > > > Another step towards PSR2 selective fetch, here programming
> > > > > plane
> > > > > selective fetch registers and MAN_TRK_CTL enabling selective
> > > > > fetch
> > > > > but
> > > > > for now it is fetching the whole area of the planes.
> > > > > The damaged area calculation will come as next and final step.
> > > > >
> > > > > v2:
> > > > > - removed warn on when no plane is visible in state
> > > > > - removed calculations using plane damaged area in
> > > > > intel_psr2_program_plane_sel_fetch()
> > > > >
> > > > > v3:
> > > > > - do not shift 16 positions the plane dst coordinates, only src
> > > > > is
> > > > > shifted
> > > > >
> > > > > BSpec: 55229
> > > > > Cc: Gwan-gyeong Mun <
> > > > > gwan-gyeong.mun@intel.com
> > > > >
> > > > >
> > > > >
> > > > > Cc: Ville Syrjälä <
> > > > > ville.syrjala@linux.intel.com
> > > > >
> > > > >
> > > > >
> > > > > Signed-off-by: José Roberto de Souza <
> > > > > jose.souza@intel.com
> > > > >
> > > > >
> > > > >
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 10 +-
> > > > > drivers/gpu/drm/i915/display/intel_psr.c | 120
> > > > > ++++++++++++++++++-
> > > > > drivers/gpu/drm/i915/display/intel_psr.h | 10 +-
> > > > > drivers/gpu/drm/i915/display/intel_sprite.c | 3 +
> > > > > 4 files changed, 134 insertions(+), 9 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 5a9d933e425a..96bc515497c1 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -11812,6 +11812,9 @@ static void i9xx_update_cursor(struct
> > > > > intel_plane *plane,
> > > > > if (INTEL_GEN(dev_priv) >= 9)
> > > > > skl_write_cursor_wm(plane, crtc_state);
> > > > >
> > > > > + if (!needs_modeset(crtc_state))
> > > > > + intel_psr2_program_plane_sel_fetch(plane,
> > > > > crtc_state,
> > > > > plane_state, 0);
> > > > > +
> > > > > if (plane->cursor.base != base ||
> > > > > plane->cursor.size != fbc_ctl ||
> > > > > plane->cursor.cntl != cntl) {
> > > > > @@ -12823,8 +12826,11 @@ static int
> > > > > intel_crtc_atomic_check(struct
> > > > > intel_atomic_state *state,
> > > > >
> > > > > }
> > > > >
> > > > > - if (!mode_changed)
> > > > > - intel_psr2_sel_fetch_update(state, crtc);
> > > > > + if (!mode_changed) {
> > > > > + ret = intel_psr2_sel_fetch_update(state, crtc);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > + }
> > > > >
> > > > > return 0;
> > > > > }
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 02f74b0ddec1..deb0523f9f29 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -1166,6 +1166,41 @@ static void
> > > > > psr_force_hw_tracking_exit(struct
> > > > > drm_i915_private *dev_priv)
> > > > > intel_psr_exit(dev_priv);
> > > > > }
> > > > >
> > > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane
> > > > > *plane,
> > > > > + const struct
> > > > > intel_crtc_state
> > > > > *crtc_state,
> > > > > + const struct
> > > > > intel_plane_state
> > > > > *plane_state,
> > > > > + int color_plane)
> > > > > +{
> > > > > + struct drm_i915_private *dev_priv = to_i915(plane-
> > > > > > base.dev);
> > > > >
> > > > > + enum pipe pipe = plane->pipe;
> > > > > + u32 val;
> > > > > +
> > > > > + if (!crtc_state->enable_psr2_sel_fetch)
> > > > > + return;
> > > > > +
> > > > > + /*
> > > > > + * skl_plane_ctl_crtc()/i9xx_cursor_ctl_crtc() return 0
> > > > > for
> > > > > gen11+, so
> > > > > + * plane_state->ctl is the right value
> > > > > + */
> > > > > + val = plane_state ? plane_state->ctl : 0;
> > > >
> > > > IMHO, skl_plane_ctl() might set other ctl bits, it would be
> > > > better to
> > > > have separated ctl bit value for "selective fetch ctl".
> > >
> > > Like said all other bits are spares so can be set without issues
> > > but okay will a "plane_state->ctl & PLANE_SEL_FETCH_CTL_ENABLE".
> >
> > Please take a look to the answer of your other comment bellow, with
> > the change above can I have your rv-b?
>
> The purpose and composition of bits of Register_SEL_FETCH_PLANE_CTL is
> different from Register_PLANE_CTL.
> And the Spares bits of Register_SEL_FETCH_PLANE_CTL might be used for
> other purpose.
> (And we current don't know the side effect of setting of Spares bit of
> Register_SEL_FETCH_PLANE_CTL )
> therefor I recommend "Read and Modify" to SEL_FETCH_PLANE_CTL.
Ah just remembered why I was using doing this, for cursor the bits that needs to be set is the first 5 bits.
Anyways masking out other bits in v4.
> > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe,
> > > > > plane-
> > > > > > id), val);
> > > > >
> > > > > + if (!val || plane->id == PLANE_CURSOR)
> > > > > + return;
> > > > > +
> > > > > + val = plane_state->uapi.dst.y1 << 16 | plane_state-
> > > > > > uapi.dst.x1;
> > > > >
> > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe,
> > > > > plane-
> > > > > > id), val);
> > > > >
> > > > > +
> > > > > + val = plane_state->color_plane[color_plane].y << 16;
> > > > > + val |= plane_state->color_plane[color_plane].x;
> > > > > + intel_de_write_fw(dev_priv,
> > > > > PLANE_SEL_FETCH_OFFSET(pipe, plane-
> > > > > > id),
> > > > >
> > > > > + val);
> > > > > +
> > > > > + /* Sizes are 0 based */
> > > > > + val = ((drm_rect_height(&plane_state->uapi.src) >> 16)
> > > > > - 1) <<
> > > > > 16;
> > > > > + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) -
> > > > > 1;
> > > > > + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe,
> > > > > plane-
> > > > > > id), val);
> > > > >
> > > > > +}
> > > > > +
> > > > > void intel_psr2_program_trans_man_trk_ctl(const struct
> > > > > intel_crtc_state *crtc_state)
> > > > > {
> > > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> > > > > > uapi.crtc);
> > > > >
> > > > > @@ -1180,16 +1215,91 @@ void
> > > > > intel_psr2_program_trans_man_trk_ctl(const struct
> > > > > intel_crtc_state
> > > > > *crtc_st
> > > > > crtc_state->psr2_man_track_ctl);
> > > > > }
> > > > >
> > > > > -void intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > > > *state,
> > > > > - struct intel_crtc *crtc)
> > > > > +static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> > > > > *crtc_state,
> > > > > + struct drm_rect *clip, bool
> > > > > full_update)
> > > > > +{
> > > > > + u32 val = PSR2_MAN_TRK_CTL_ENABLE;
> > > > > +
> > > > > + if (full_update) {
> > > > > + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> > > > > + goto exit;
> > > > > + }
> > > > > +
> > > > > + if (clip->y1 == -1)
> > > > > + goto exit;
> > > > > +
> > > > > + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
> > > > > + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 /
> > > > > 4 + 1);
> > > >
> > > > I think the start address block would be like this too.
> > > > PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(DIV_ROUND_UP(clip->y1 ,
> > > > 4));
> > >
> > > This would not match for numbers that divide by 4.
> > > y pos 0 = region 1y pos 1 = region 1
> > > y pos 4 = region 2
> > >
>
> yes. you are right.
> > > > > + val |=
> > > > > PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip-
> > > > > > y2, 4) + 1);
> > > > >
> > > > > +exit:
> > > > > + crtc_state->psr2_man_track_ctl = val;
> > > > > +}
> > > > > +
> > > > > +static void clip_area_update(struct drm_rect
> > > > > *overlap_damage_area,
> > > > > + struct drm_rect *damage_area)
> > > > > +{
> > > > > + if (overlap_damage_area->y1 == -1) {
> > > > > + overlap_damage_area->y1 = damage_area->y1;
> > > > > + overlap_damage_area->y2 = damage_area->y2;
> > > > > + return;
> > > > > + }
> > > > > +
> > > > > + if (damage_area->y1 < overlap_damage_area->y1)
> > > > > + overlap_damage_area->y1 = damage_area->y1;
> > > > > +
> > > > > + if (damage_area->y2 > overlap_damage_area->y2)
> > > > > + overlap_damage_area->y2 = damage_area->y2;
> > > > > +}
> > > > > +
> > > > > +int intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > > > *state,
> > > > > + struct intel_crtc *crtc)
> > > > > {
> > > > > struct intel_crtc_state *crtc_state =
> > > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > > > + struct intel_plane_state *new_plane_state,
> > > > > *old_plane_state;
> > > > > + struct drm_rect pipe_clip = { .y1 = -1 };
> > > > > + struct intel_plane *plane;
> > > > > + bool full_update = false;
> > > > > + int i, ret;
> > > > >
> > > > > if (!crtc_state->enable_psr2_sel_fetch)
> > > > > - return;
> > > > > + return 0;
> > > > > +
> > > > > + ret = drm_atomic_add_affected_planes(&state->base,
> > > > > &crtc-
> > > > > > base);
> > > > >
> > > > > + if (ret)
> > > > > + return ret;
> > > > > +
> > > > > + for_each_oldnew_intel_plane_in_state(state, plane,
> > > > > old_plane_state,
> > > > > + new_plane_state,
> > > > > i) {
> > > > > + struct drm_rect temp;
> > > > > +
> > > > > + if (new_plane_state->uapi.crtc != crtc_state-
> > > > > > uapi.crtc)
> > > > >
> > > > > + continue;
> > > > >
> > > > > - crtc_state->psr2_man_track_ctl =
> > > > > PSR2_MAN_TRK_CTL_ENABLE |
> > > > > - PSR2_MAN_TRK_CTL_SF_SI
> > > > > NGLE_FUL
> > > > > L_FRAME;
> > > > > + /*
> > > > > + * TODO: Not clear how to handle planes with
> > > > > negative
> > > > > position,
> > > > > + * also planes are not updated if they have a
> > > > > negative
> > > > > X
> > > > > + * position so for now doing a full update in
> > > > > this
> > > > > cases
> > > > > + */
> > > > > + if (new_plane_state->uapi.dst.y1 < 0 ||
> > > > > + new_plane_state->uapi.dst.x1 < 0) {
> > > > > + full_update = true;
> > > > > + break;
> > > > > + }
> > > > > +
> > > > > + if (!new_plane_state->uapi.visible)
> > > > > + continue;
> > > > > +
> > > > > + /*
> > > > > + * For now doing a selective fetch in the whole
> > > > > plane
> > > > > area,
> > > > > + * optimizations will come in the future.
> > > > > + */
> > > > > + temp.y1 = new_plane_state->uapi.dst.y1;
> > > > > + temp.y2 = new_plane_state->uapi.dst.y2;
> > > > > + clip_area_update(&pipe_clip, &temp);
> > > > > + }
> > > > > +
> > > > > + psr2_man_trk_ctl_calc(crtc_state, &pipe_clip,
> > > > > full_update);
> > > > > + return 0;
> > > > > }
> > > > >
> > > > > /**
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > index 6a83c8e682e6..3eca9dcec3c0 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > @@ -15,6 +15,8 @@ struct intel_crtc_state;
> > > > > struct intel_dp;
> > > > > struct intel_crtc;
> > > > > struct intel_atomic_state;
> > > > > +struct intel_plane_state;
> > > > > +struct intel_plane;
> > > > >
> > > > > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv-
> > > > > > psr.sink_support)
> > > > >
> > > > > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > > > > @@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct
> > > > > drm_connector
> > > > > *connector,
> > > > > struct drm_connector_state
> > > > > *old_state,
> > > > > struct drm_connector_state
> > > > > *new_state);
> > > > > void intel_psr_set_force_mode_changed(struct intel_dp
> > > > > *intel_dp);
> > > > > -void intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > > > *state,
> > > > > - struct intel_crtc *crtc);
> > > > > +int intel_psr2_sel_fetch_update(struct intel_atomic_state
> > > > > *state,
> > > > > + struct intel_crtc *crtc);
> > > > > void intel_psr2_program_trans_man_trk_ctl(const struct
> > > > > intel_crtc_state *crtc_state);
> > > > > +void intel_psr2_program_plane_sel_fetch(struct intel_plane
> > > > > *plane,
> > > > > + const struct
> > > > > intel_crtc_state
> > > > > *crtc_state,
> > > > > + const struct
> > > > > intel_plane_state
> > > > > *plane_state,
> > > > > + int color_plane);
> > > > >
> > > > > #endif /* __INTEL_PSR_H__ */
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > > index 63040cb0d4e1..f12425b90607 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > > > @@ -690,6 +690,9 @@ skl_program_plane(struct intel_plane
> > > > > *plane,
> > > > > intel_de_write_fw(dev_priv,
> > > > > PLANE_AUX_OFFSET(pipe,
> > > > > plane_id),
> > > > > (plane_state-
> > > > > > color_plane[1].y << 16)
> > > > > > plane_state->color_plane[1].x);
> > > > >
> > > > >
> > > > > + if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
> > > > > + intel_psr2_program_plane_sel_fetch(plane,
> > > > > crtc_state,
> > > > > plane_state, color_plane);
> > > > > +
> > > > > /*
> > > > > * The control register self-arms if the plane was
> > > > > previously
> > > > > * disabled. Try to make the plane enable atomic by
> > > > > writing
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-09-24 17:38 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-18 1:02 [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch José Roberto de Souza
2020-09-18 1:02 ` [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Check PSR parameter and flag only in state compute phase José Roberto de Souza
2020-09-18 1:02 ` [Intel-gfx] [PATCH v3 3/3] drm/i915/display: Program PSR2 selective fetch registers José Roberto de Souza
2020-09-23 13:02 ` Mun, Gwan-gyeong
2020-09-23 17:07 ` Souza, Jose
2020-09-23 17:09 ` Souza, Jose
2020-09-24 13:27 ` Mun, Gwan-gyeong
2020-09-24 17:38 ` Souza, Jose
2020-09-18 1:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch Patchwork
2020-09-18 3:44 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-09-18 17:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch (rev2) Patchwork
2020-09-18 18:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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