From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level Date: Thu, 31 Mar 2011 08:29:31 +0100 Message-ID: References: <1301443195-10721-1-git-send-email-eric@anholt.net> <1301443195-10721-5-git-send-email-eric@anholt.net> <87wrjg4k8k.fsf@pollan.anholt.net> <849307$c839fg@azsmga001.ch.intel.com> <87aagcb7vc.fsf@pollan.anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 55A0E9E799 for ; Thu, 31 Mar 2011 00:29:34 -0700 (PDT) In-Reply-To: <87aagcb7vc.fsf@pollan.anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 30 Mar 2011 14:45:11 -0700, Eric Anholt wrote: > On Wed, 30 Mar 2011 18:16:11 +0100, Chris Wilson wrote: > > On Wed, 30 Mar 2011 09:59:55 -0700, Eric Anholt wrote: > > > And what about a CPU write through the GTT? > > > > Even on SNB these are still UC. And we should try hard not to, as the > > specs give dire warnings about writing to snooped PTEs through the GTT. > > (Since we will bypass the caches with the write, aiui, and cause > > confusion.) > > Oh, wow. That's really bad. Reject this series if so. I plucked that tidbit out of the specs for the BLT engine, which has not been rigorously updated since gen2... Though don't we also encounter a few subtleties with movnta (__copy_from_user_nocache_nozero from pwrite) and data in cachelines? But it is something that I worry about given my desire to start mapping user pages and using the BLT engine for C to UC transfers. -Chris -- Chris Wilson, Intel Open Source Technology Centre