From: Chris Wilson <chris@chris-wilson.co.uk>
To: Eric Anholt <eric@anholt.net>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level
Date: Wed, 30 Mar 2011 08:09:47 +0100 [thread overview]
Message-ID: <b9dded$ig3i1o@orsmga002.jf.intel.com> (raw)
In-Reply-To: <1301443195-10721-5-git-send-email-eric@anholt.net>
The series looks really good, only one quibble below.
On Tue, 29 Mar 2011 16:59:53 -0700, Eric Anholt <eric@anholt.net> wrote:
> +int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
> + enum i915_cache_level cache_level)
> + if (cache_level == I915_CACHE_NONE) {
> + /* If we're coming frm LLC cached, then we haven't
> + * actually been tracking whether the data is in the
> + * CPU cache or not, since we only allow one bit set
> + * in obj->write_domain. Just set it to the CPU cache
> + * for now.
> + */
> + BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
> + obj->base.write_domain = I915_GEM_DOMAIN_CPU;
> + }
[We can rearrange the code to convert the BUG_ON into a
if (WARN_ON()) return -EBUSY;.]
I think this is overkill, at least by my interpretation of the old BLT
docs which imply that cache line invalidation (both CPU and GPU) is done
for snooped PTEs on MI_FLUSH.
LLC -> UC transitions will be rare, only for new buffers (and on the first
page flip) after a modeset, but it's the principle! ;-)
Until we expose cache control through an ioctl we will never be able to
experiment...
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2011-03-30 7:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-29 23:59 reduced LLC caching series Eric Anholt
2011-03-29 23:59 ` [PATCH 1/6] drm/i915: Rename agp_type to cache_level Eric Anholt
2011-03-29 23:59 ` [PATCH 2/6] drm/i915: Mark the cursor and the overlay as being part of the display planes Eric Anholt
2011-03-29 23:59 ` [PATCH 3/6] drm/i915: Do not clflush snooped objects Eric Anholt
2011-03-29 23:59 ` [PATCH 4/6] drm/i915: Add an interface to dynamically change the cache level Eric Anholt
2011-03-30 7:09 ` Chris Wilson [this message]
2011-03-30 16:59 ` Eric Anholt
2011-03-30 17:16 ` Chris Wilson
2011-03-30 21:45 ` Eric Anholt
2011-03-31 7:29 ` Chris Wilson
2011-03-31 20:10 ` Eric Anholt
2011-03-29 23:59 ` [PATCH 5/6] drm/i915: Use the uncached domain for the display planes v2 Eric Anholt
2011-03-29 23:59 ` [PATCH 6/6] drm/i915: Use the LLC mode on gen6 for everything but display Eric Anholt
2011-03-30 22:35 ` reduced LLC caching series Michael Larabel
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