From: "Souza, Jose" <jose.souza@intel.com>
To: "Mun, Gwan-gyeong" <gwan-gyeong.mun@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 4/4] DO_NOT_MERGE: drm/i915/display: Enable PSR2 selective fetch by default
Date: Tue, 3 Aug 2021 17:18:37 +0000 [thread overview]
Message-ID: <c30de5129bec44f07238d2e8906c031820a5e36d.camel@intel.com> (raw)
In-Reply-To: <c0055e67-2841-0ef9-c18f-d60e9e186897@intel.com>
On Tue, 2021-08-03 at 14:17 +0300, Gwan-gyeong Mun wrote:
>
> On 7/31/21 3:10 AM, José Roberto de Souza wrote:
> > Only to execute tests with PSR2 selective fetch enabled and check what
> > is broken.
> >
> > IGT tests know to fail with this:
> > - kms_cursor_legacy: all tests that checks if evasion happend, I have
> > fix for it making cursor_slowpath() returns true for display 12+.
> >
> > - kms_psr2_su: The pageflip test, it needs to have the damage clip set
> > otherwise it will update the whole screen and the selective blocks
> > will not match with expected.
> >
> kms_psr2_su is a test case for intel PSR2 HW tracking and kms_psr2_sf is
> used as a test for intel PSR2 manual tracking. Is it necessary to modify
> kms_psr2_su for testing PSR2 manual tracking?
kms_psr2_su is to test that PSR2 is sending selective updates, just adding a couple of lines we can make it work with selective fetch.
> > - kms_psr: psr2_*_(mmap_gtt, mmap_cpu, blt and render), all those
> > tests should be dropped or skipped for display 12+.
> >
> Could you explain in more detail why we need to skip on display 12+?
This are stuff that would end up calling intel_psr_invalidate/flush().
>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 9 ---------
> > drivers/gpu/drm/i915/i915_params.h | 2 +-
> > 2 files changed, 1 insertion(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 894a2d35668a2..e128f0c2aeecc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -877,15 +877,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> > return false;
> > }
> >
> > - /*
> > - * We are missing the implementation of some workarounds to enabled PSR2
> > - * in Alderlake_P, until ready PSR2 should be kept disabled.
> > - */
> > - if (IS_ALDERLAKE_P(dev_priv)) {
> > - drm_dbg_kms(&dev_priv->drm, "PSR2 is missing the implementation of workarounds\n");
> > - return false;
> > - }
> > -
> > if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
> > drm_dbg_kms(&dev_priv->drm,
> > "PSR2 not supported in transcoder %s\n",
> > diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> > index f27eceb82c0f5..8d725b64592d8 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -55,7 +55,7 @@ struct drm_printer;
> > param(int, enable_fbc, -1, 0600) \
> > param(int, enable_psr, -1, 0600) \
> > param(bool, psr_safest_params, false, 0400) \
> > - param(bool, enable_psr2_sel_fetch, false, 0400) \
> > + param(bool, enable_psr2_sel_fetch, true, 0400) \
> > param(int, disable_power_well, -1, 0400) \
> > param(int, enable_ips, 1, 0600) \
> > param(int, invert_brightness, 0, 0600) \
> >
next prev parent reply other threads:[~2021-08-03 17:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-31 0:10 [Intel-gfx] [PATCH 1/4] drm/i915/display/tgl+: Dispatch atomic commits instead of front buffer modifications José Roberto de Souza
2021-07-31 0:10 ` [Intel-gfx] [PATCH 2/4] drm/i915/display: Fix sel fetch plane offset calculation José Roberto de Souza
2021-08-13 7:40 ` Gwan-gyeong Mun
2021-07-31 0:10 ` [Intel-gfx] [PATCH 3/4] drm/i915: Nuke ORIGIN_GTT José Roberto de Souza
2021-08-03 11:20 ` Gwan-gyeong Mun
2021-08-03 17:19 ` Souza, Jose
2021-08-13 7:41 ` Gwan-gyeong Mun
2021-07-31 0:10 ` [Intel-gfx] [PATCH 4/4] DO_NOT_MERGE: drm/i915/display: Enable PSR2 selective fetch by default José Roberto de Souza
2021-08-03 11:17 ` Gwan-gyeong Mun
2021-08-03 17:18 ` Souza, Jose [this message]
2021-08-05 18:26 ` Gwan-gyeong Mun
2021-08-05 21:47 ` Souza, Jose
2021-07-31 0:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/display/tgl+: Dispatch atomic commits instead of front buffer modifications Patchwork
2021-07-31 0:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-08-12 17:24 ` [Intel-gfx] [PATCH 1/4] " Souza, Jose
2021-08-12 19:02 ` Daniel Vetter
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