From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6432DC433E6 for ; Tue, 2 Feb 2021 11:57:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D1C364F53 for ; Tue, 2 Feb 2021 11:57:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0D1C364F53 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 779B26E10B; Tue, 2 Feb 2021 11:57:28 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id F3C076E10B for ; Tue, 2 Feb 2021 11:57:26 +0000 (UTC) IronPort-SDR: 3TxZHIwe/wH0z8Wecx5x+jh2dTPvKYdiE4TvDz1nlKOqzUB78I3vHHZe80jWsK5h5RGH12Ngrl b3oexJx97Ygw== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="180984125" X-IronPort-AV: E=Sophos;i="5.79,394,1602572400"; d="scan'208";a="180984125" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2021 03:57:26 -0800 IronPort-SDR: OK4uMolGmCAB+nQuf1IqLmOts7ffp67LZx4cnZIbNrktxz8VTCaOsSvIrdX2QIjN3Z9dd8Y/qI gCpVfYMqXMTw== X-IronPort-AV: E=Sophos;i="5.79,394,1602572400"; d="scan'208";a="432879199" Received: from irisshal-mobl1.ger.corp.intel.com (HELO [10.214.210.18]) ([10.214.210.18]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2021 03:57:24 -0800 To: Chris Wilson , intel-gfx@lists.freedesktop.org References: <20210201085715.27435-1-chris@chris-wilson.co.uk> <20210201085715.27435-7-chris@chris-wilson.co.uk> From: Tvrtko Ursulin Organization: Intel Corporation UK Plc Message-ID: Date: Tue, 2 Feb 2021 11:57:20 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <20210201085715.27435-7-chris@chris-wilson.co.uk> Content-Language: en-US Subject: Re: [Intel-gfx] [PATCH 07/57] drm/i915/gt: Move engine setup out of set_default_submission X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 01/02/2021 08:56, Chris Wilson wrote: > Now that we no longer switch back and forth between guc and execlists, > we no longer need to restore the backend's vfunc and can leave them set > after initialisation. The only catch is that we lose the submission on > wedging and still need to reset the submit_request vfunc on unwedging. > > Signed-off-by: Chris Wilson > --- > .../drm/i915/gt/intel_execlists_submission.c | 46 ++++++++--------- > .../gpu/drm/i915/gt/intel_ring_submission.c | 4 -- > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 50 ++++++++----------- > 3 files changed, 44 insertions(+), 56 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > index 45a8ac152b88..5d824e1cfcba 100644 > --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c > @@ -3089,29 +3089,6 @@ static void execlists_set_default_submission(struct intel_engine_cs *engine) > engine->submit_request = execlists_submit_request; > engine->schedule = i915_schedule; > engine->execlists.tasklet.callback = execlists_submission_tasklet; > - > - engine->reset.prepare = execlists_reset_prepare; > - engine->reset.rewind = execlists_reset_rewind; > - engine->reset.cancel = execlists_reset_cancel; > - engine->reset.finish = execlists_reset_finish; > - > - engine->park = execlists_park; > - engine->unpark = NULL; > - > - engine->flags |= I915_ENGINE_SUPPORTS_STATS; > - if (!intel_vgpu_active(engine->i915)) { > - engine->flags |= I915_ENGINE_HAS_SEMAPHORES; > - if (can_preempt(engine)) { > - engine->flags |= I915_ENGINE_HAS_PREEMPTION; > - if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION)) > - engine->flags |= I915_ENGINE_HAS_TIMESLICES; > - } > - } > - > - if (intel_engine_has_preemption(engine)) > - engine->emit_bb_start = gen8_emit_bb_start; > - else > - engine->emit_bb_start = gen8_emit_bb_start_noarb; > } > > static void execlists_shutdown(struct intel_engine_cs *engine) > @@ -3142,6 +3119,14 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) > engine->cops = &execlists_context_ops; > engine->request_alloc = execlists_request_alloc; > > + engine->reset.prepare = execlists_reset_prepare; > + engine->reset.rewind = execlists_reset_rewind; > + engine->reset.cancel = execlists_reset_cancel; > + engine->reset.finish = execlists_reset_finish; > + > + engine->park = execlists_park; > + engine->unpark = NULL; > + > engine->emit_flush = gen8_emit_flush_xcs; > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb; > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs; > @@ -3162,6 +3147,21 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) > * until a more refined solution exists. > */ > } > + > + engine->flags |= I915_ENGINE_SUPPORTS_STATS; > + if (!intel_vgpu_active(engine->i915)) { > + engine->flags |= I915_ENGINE_HAS_SEMAPHORES; > + if (can_preempt(engine)) { > + engine->flags |= I915_ENGINE_HAS_PREEMPTION; > + if (IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION)) > + engine->flags |= I915_ENGINE_HAS_TIMESLICES; > + } > + } > + > + if (intel_engine_has_preemption(engine)) > + engine->emit_bb_start = gen8_emit_bb_start; > + else > + engine->emit_bb_start = gen8_emit_bb_start_noarb; > } > > static void logical_ring_default_irqs(struct intel_engine_cs *engine) > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 9c2c605d7a92..3cb2ce503544 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -969,14 +969,10 @@ static void gen6_bsd_submit_request(struct i915_request *request) > static void i9xx_set_default_submission(struct intel_engine_cs *engine) > { > engine->submit_request = i9xx_submit_request; > - > - engine->park = NULL; > - engine->unpark = NULL; > } > > static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) > { > - i9xx_set_default_submission(engine); > engine->submit_request = gen6_bsd_submit_request; > } > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > index 92688a9b6717..f72faa0b8339 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c > @@ -608,35 +608,6 @@ static int guc_resume(struct intel_engine_cs *engine) > static void guc_set_default_submission(struct intel_engine_cs *engine) > { > engine->submit_request = guc_submit_request; > - engine->schedule = i915_schedule; > - engine->execlists.tasklet.callback = guc_submission_tasklet; > - > - engine->reset.prepare = guc_reset_prepare; > - engine->reset.rewind = guc_reset_rewind; > - engine->reset.cancel = guc_reset_cancel; > - engine->reset.finish = guc_reset_finish; > - > - engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; > - engine->flags |= I915_ENGINE_HAS_PREEMPTION; > - > - /* > - * TODO: GuC supports timeslicing and semaphores as well, but they're > - * handled by the firmware so some minor tweaks are required before > - * enabling. > - * > - * engine->flags |= I915_ENGINE_HAS_TIMESLICES; > - * engine->flags |= I915_ENGINE_HAS_SEMAPHORES; > - */ > - > - engine->emit_bb_start = gen8_emit_bb_start; > - > - /* > - * For the breadcrumb irq to work we need the interrupts to stay > - * enabled. However, on all platforms on which we'll have support for > - * GuC submission we don't allow disabling the interrupts at runtime, so > - * we're always safe with the current flow. > - */ > - GEM_BUG_ON(engine->irq_enable || engine->irq_disable); > } > > static void guc_release(struct intel_engine_cs *engine) > @@ -658,6 +629,13 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine) > engine->cops = &guc_context_ops; > engine->request_alloc = guc_request_alloc; > > + engine->schedule = i915_schedule; > + > + engine->reset.prepare = guc_reset_prepare; > + engine->reset.rewind = guc_reset_rewind; > + engine->reset.cancel = guc_reset_cancel; > + engine->reset.finish = guc_reset_finish; > + > engine->emit_flush = gen8_emit_flush_xcs; > engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb; > engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_xcs; > @@ -666,6 +644,20 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine) > engine->emit_flush = gen12_emit_flush_xcs; > } > engine->set_default_submission = guc_set_default_submission; > + > + engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET; > + engine->flags |= I915_ENGINE_HAS_PREEMPTION; > + > + /* > + * TODO: GuC supports timeslicing and semaphores as well, but they're > + * handled by the firmware so some minor tweaks are required before > + * enabling. > + * > + * engine->flags |= I915_ENGINE_HAS_TIMESLICES; > + * engine->flags |= I915_ENGINE_HAS_SEMAPHORES; > + */ > + > + engine->emit_bb_start = gen8_emit_bb_start; > } > > static void rcs_submission_override(struct intel_engine_cs *engine) > Reviewed-by: Tvrtko Ursulin Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx