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Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Subject: Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: Use the correct IRQ during resume X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: airlied@linux.ie, Daniel Vetter , intel-gfx@lists.freedesktop.org, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org, chris@chris-wilson.co.uk Content-Type: multipart/mixed; boundary="===============0092394626==" Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --===============0092394626== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="a30RO2t3JXHEiirTgF6hZ3eL9QhW3hHFz" This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --a30RO2t3JXHEiirTgF6hZ3eL9QhW3hHFz Content-Type: multipart/mixed; boundary="r5rQSf3n0gVOq0ugtBXSd8ar4zo1cOaYe"; protected-headers="v1" From: Thomas Zimmermann To: Daniel Vetter Cc: matthew.brost@intel.com, airlied@linux.ie, mika.kuoppala@linux.intel.com, intel-gfx@lists.freedesktop.org, chris@chris-wilson.co.uk, Daniel Vetter , dri-devel@lists.freedesktop.org, rodrigo.vivi@intel.com, lucas.demarchi@intel.com Message-ID: Subject: Re: [PATCH v3 1/2] drm/i915: Use the correct IRQ during resume References: <20210630095228.6665-1-tzimmermann@suse.de> <20210630095228.6665-2-tzimmermann@suse.de> In-Reply-To: --r5rQSf3n0gVOq0ugtBXSd8ar4zo1cOaYe Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable Hi Am 30.06.21 um 12:49 schrieb Daniel Vetter: > On Wed, Jun 30, 2021 at 11:52:27AM +0200, Thomas Zimmermann wrote: >> The code in xcs_resume() probably didn't work as intended. It uses >> struct drm_device.irq, which is allocated to 0, but never initialized >> by i915 to the device's interrupt number. >> >> v3: >> * also use intel_synchronize_hardirq() at another callsite >> v2: >> * wrap irq code in intel_synchronize_hardirq() (Ville) >> >> Signed-off-by: Thomas Zimmermann >> Fixes: 536f77b1caa0 ("drm/i915/gt: Call stop_ring() from ring resume, = again") >> Cc: Chris Wilson >> Cc: Mika Kuoppala >> Cc: Daniel Vetter >> Cc: Rodrigo Vivi >> Cc: Joonas Lahtinen >> Cc: Maarten Lankhorst >> Cc: Lucas De Marchi >> --- >> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- >> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +- >> drivers/gpu/drm/i915/i915_irq.c | 5 +++++ >> drivers/gpu/drm/i915/i915_irq.h | 1 + >> 4 files changed, 8 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/d= rm/i915/gt/intel_engine_cs.c >> index 88694822716a..5ca3d1664335 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c >> @@ -1229,7 +1229,7 @@ bool intel_engine_is_idle(struct intel_engine_cs= *engine) >> return true; >> =20 >> /* Waiting to drain ELSP? */ >> - synchronize_hardirq(to_pci_dev(engine->i915->drm.dev)->irq); >> + intel_synchronize_hardirq(engine->i915); >> intel_engine_flush_submission(engine); >> =20 >> /* ELSP is empty, but there are ready requests? E.g. after reset */= >> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers= /gpu/drm/i915/gt/intel_ring_submission.c >> index 5d42a12ef3d6..1b5a22a83db6 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c >> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c >> @@ -185,7 +185,7 @@ static int xcs_resume(struct intel_engine_cs *engi= ne) >> ring->head, ring->tail); >> =20 >> /* Double check the ring is empty & disabled before we resume */ >> - synchronize_hardirq(engine->i915->drm.irq); >> + intel_synchronize_hardirq(engine->i915); >> if (!stop_ring(engine)) >> goto err; >> =20 >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i9= 15_irq.c >> index 7d0ce8b9f8ed..2203dca19895 100644 >> --- a/drivers/gpu/drm/i915/i915_irq.c >> +++ b/drivers/gpu/drm/i915/i915_irq.c >> @@ -4575,3 +4575,8 @@ void intel_synchronize_irq(struct drm_i915_priva= te *i915) >> { >> synchronize_irq(to_pci_dev(i915->drm.dev)->irq); >> } >> + >> +void intel_synchronize_hardirq(struct drm_i915_private *i915) >> +{ >> + synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq); >=20 > I honestly think the hardirq here is about as much cargo-culted as usin= g > the wrong irq number. >=20 > I'd just use intel_synchronize_irq in both places and see whether CI > complains, then go with that. Well, ok. I don't think I have Sandybridge HW available. Would the Intel = CI infrastructure catch any problems with such a change? Best regards Thomas > -Daniel >=20 >> +} >> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i9= 15_irq.h >> index db34d5dbe402..e43b6734f21b 100644 >> --- a/drivers/gpu/drm/i915/i915_irq.h >> +++ b/drivers/gpu/drm/i915/i915_irq.h >> @@ -94,6 +94,7 @@ void intel_runtime_pm_disable_interrupts(struct drm_= i915_private *dev_priv); >> void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev= _priv); >> bool intel_irqs_enabled(struct drm_i915_private *dev_priv); >> void intel_synchronize_irq(struct drm_i915_private *i915); >> +void intel_synchronize_hardirq(struct drm_i915_private *i915); >> =20 >> int intel_get_crtc_scanline(struct intel_crtc *crtc); >> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_pr= iv, >> --=20 >> 2.32.0 >> >=20 --=20 Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany (HRB 36809, AG N=C3=BCrnberg) Gesch=C3=A4ftsf=C3=BChrer: Felix Imend=C3=B6rffer --r5rQSf3n0gVOq0ugtBXSd8ar4zo1cOaYe-- --a30RO2t3JXHEiirTgF6hZ3eL9QhW3hHFz Content-Type: application/pgp-signature; name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature" -----BEGIN PGP SIGNATURE----- wsF5BAABCAAjFiEExndm/fpuMUdwYFFolh/E3EQov+AFAmDcfScFAwAAAAAACgkQlh/E3EQov+C5 xg/+KhqHd3uPCVG77kDRARlJ0YJ0NkwnqvwS6cm2Ysjkho1aFCUR3KZ7lp7nvwB4Z2THvQaTnKHG Y28G3CBK4gay1m6P22ntYq8wLKx/2zQUC8vtLasMSnoOxNELRYgTOoIrnAnSEopSdQsAxFtNGIR8 xdm8cnvSKE18AmWYUzaPCoZrOP3OY2bZlIKJpRQfOHo6s0JfCXyhmW0v3QMLUqIKqUVXs0oIXx3F /AmseHy3oT0HTbOH3SChHg1Fe/rJ+V4fyNyHVDjJHWvpxYCqE+Dkd1n8YdQAE7GnLuUaJYpNVf4q 3kAyTy+2o/H1jefUFRA1OzfVG6vLLSsBpM2r4MwBGU0nhPSLhutScAUZHPsZ524b9gsqKDak9ckJ xlX4EEX/LyA097Pi3JC/jiLUQcoDlimfnF6LfQVUtZSfuIg8djm8VRF8lgN31v51TAdOUCnBBglS XmLRY6kRbBYfJezZtBDtiSS5ZqEFPdDHKP6xNCqr/VwDOS9ymsNuwbqnUBLjl+fmSFBtHKyfcmgV Hypk7S6guxaV+KQT6VpeKpXT3D9iyXcLthLqo8zyXstEoy3Q6+z9pb4pbkxxK3+6BAyqz0SvjNv/ L2Y9Q5g3t9UC7yRVdoqblInvhIfi/Y/MmU+KbdcaW9cWaQC3NLKd3w8Nf2FWBLj6A6qsvcLmZmp9 QII= =atNS -----END PGP SIGNATURE----- --a30RO2t3JXHEiirTgF6hZ3eL9QhW3hHFz-- --===============0092394626== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0092394626==--