From: Chris Wilson <chris@chris-wilson.co.uk>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915: clear GFX_MODE on IVB at init time
Date: Fri, 12 Aug 2011 23:56:27 +0100 [thread overview]
Message-ID: <e39f63$155frs@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <20110812152832.6c922a17@jbarnes-desktop>
On Fri, 12 Aug 2011 15:28:32 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> I915_WRITE(MI_MODE, mode);
> + if (IS_GEN7(dev))
> + I915_WRITE(GFX_MODE_GEN7, ((GFX_TLB_INVALIDATE_ALWAYS |
> + GFX_REPLAY_MODE) << 16) |
> + GFX_REPLAY_MODE);
That's maximally confusing indentation ;-)
Also it reads like that is a chicken bit, as in order to invalidate always
on flush we need to clear it? Can we play around with the name to avoid
confusion in the code and confusion with the spec?
#define ENABLE(x) ((x) << 16 | (x))
#define DISABLE(x) ((x) << 16 | 0)
Granted finding good names for those is hard. Perhaps ENABLE_16(x),
DISABLE_16(x) to indicate the mask size.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2011-08-12 22:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-12 21:55 [PATCH 1/2] drm/i915: clear GFX_MODE on IVB at init time Jesse Barnes
2011-08-12 21:55 ` [PATCH 2/2] drm/i915: suspend/resume rps and ring freq state on IVB Jesse Barnes
2011-08-12 22:18 ` [PATCH 1/2] drm/i915: clear GFX_MODE on IVB at init time Jesse Barnes
2011-08-12 22:28 ` Jesse Barnes
2011-08-12 22:56 ` Chris Wilson [this message]
2011-08-15 23:59 ` Kenneth Graunke
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