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From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 11/13] drm/i915: Do pipe updates after enables for everyone
Date: Fri, 3 Apr 2020 00:44:59 +0000	[thread overview]
Message-ID: <e604bd0c5f67dad5943547438a5879bbe0f1985c.camel@intel.com> (raw)
In-Reply-To: <20200313164831.5980-12-ville.syrjala@linux.intel.com>

On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently only port sync pipes do the sequence such that
> we first do the modeset part for every pipe and then do
> the plane/etc. updates. Let's follow that apporach for
> all pipes in skl+ so that we can properly integrate the
> port sync into the normal modeset flow.
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 44 ++++++++++------
> ----
>  1 file changed, 22 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 33f38c8a5da4..3926ac8f1f10 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15152,17 +15152,6 @@ static void
> intel_update_trans_port_sync_crtcs(struct intel_atomic_state *state,
>  
>  	usleep_range(200, 400);
>  	intel_set_dp_tp_ctl_normal(state, crtc);
> -
> -	for_each_new_intel_crtc_in_state(state, slave_crtc,
> -					 new_slave_crtc_state, i) {
> -		if (new_slave_crtc_state->master_transcoder !=
> -		    new_crtc_state->cpu_transcoder)
> -			continue;
> -
> -		intel_update_crtc(state, slave_crtc);
> -	}
> -
> -	intel_update_crtc(state, crtc);
>  }
>  
>  static void icl_dbuf_slice_pre_update(struct intel_atomic_state
> *state)
> @@ -15251,6 +15240,8 @@ static void skl_commit_modeset_enables(struct
> intel_atomic_state *state)
>  		}
>  	}
>  
> +	update_pipes = modeset_pipes;
> +
>  	/*
>  	 * Enable all pipes that needs a modeset and do not depends on
> other
>  	 * pipes
> @@ -15266,10 +15257,6 @@ static void
> skl_commit_modeset_enables(struct intel_atomic_state *state)
>  		    is_trans_port_sync_slave(new_crtc_state))
>  			continue;
>  
> -		drm_WARN_ON(&dev_priv->drm,
> skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
> -									
> entries, I915_MAX_PIPES, pipe));
> -
> -		entries[pipe] = new_crtc_state->wm.skl.ddb;
>  		modeset_pipes &= ~BIT(pipe);
>  
>  		if (is_trans_port_sync_mode(new_crtc_state)) {
> @@ -15287,14 +15274,13 @@ static void
> skl_commit_modeset_enables(struct intel_atomic_state *state)
>  			}
>  		} else {
>  			intel_enable_crtc(state, crtc);
> -			intel_update_crtc(state, crtc);
>  		}
>  	}
>  
>  	/*
> -	 * Finally enable all pipes that needs a modeset and depends on
> -	 * other pipes, right now it is only MST slaves as both port
> sync slave
> -	 * and master are enabled together
> +	 * Then we enable all remaining pipes that depend on other
> +	 * pipes, right now it is only MST slaves as both port sync
> +	 * slave and master are enabled together
>  	 */
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state,
> i) {
>  		enum pipe pipe = crtc->pipe;
> @@ -15302,18 +15288,32 @@ static void
> skl_commit_modeset_enables(struct intel_atomic_state *state)
>  		if ((modeset_pipes & BIT(pipe)) == 0)
>  			continue;
>  
> +		modeset_pipes &= ~BIT(pipe);
> +
> +		intel_enable_crtc(state, crtc);
> +	}
> +
> +	/*
> +	 * Finally we do the plane updates/etc. for all pipes that got
> enabled.
> +	 */
> +	for_each_oldnew_intel_crtc_in_state(state, crtc,
> old_crtc_state,
> +					    new_crtc_state, i) {
> +		enum pipe pipe = crtc->pipe;
> +
> +		if ((update_pipes & BIT(pipe)) == 0)
> +			continue;
> +
>  		drm_WARN_ON(&dev_priv->drm,
> skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
>  									
> entries, I915_MAX_PIPES, pipe));
>  
>  		entries[pipe] = new_crtc_state->wm.skl.ddb;
> -		modeset_pipes &= ~BIT(pipe);
> +		update_pipes &= ~BIT(pipe);
>  
> -		intel_enable_crtc(state, crtc);
>  		intel_update_crtc(state, crtc);
>  	}
>  
>  	drm_WARN_ON(&dev_priv->drm, modeset_pipes);
> -
> +	drm_WARN_ON(&dev_priv->drm, update_pipes);
>  }
>  
>  static void intel_atomic_helper_free_state(struct drm_i915_private
> *dev_priv)
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  reply	other threads:[~2020-04-03  0:45 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-13 16:48 [Intel-gfx] [PATCH 00/13] drm/i915: Port sync for skl+ Ville Syrjala
2020-03-13 16:48 ` [Intel-gfx] [PATCH 01/13] drm/i915/mst: Use .compute_config_late() to compute master transcoder Ville Syrjala
2020-03-20 23:37   ` Souza, Jose
2020-03-20 23:54     ` Souza, Jose
2020-03-13 16:48 ` [Intel-gfx] [PATCH 02/13] drm/i915: Move TRANS_DDI_FUNC_CTL2 programming where it belongs Ville Syrjala
2020-03-18 22:34   ` Manasi Navare
2020-03-19 13:20     ` Ville Syrjälä
2020-03-20 18:36       ` Manasi Navare
2020-03-13 16:48 ` [Intel-gfx] [PATCH 03/13] drm/i915: Drop usless master_transcoder assignments Ville Syrjala
2020-03-18 22:37   ` Manasi Navare
2020-03-19 13:22     ` Ville Syrjälä
2020-03-20 23:12       ` Manasi Navare
2020-03-13 16:48 ` [Intel-gfx] [PATCH 04/13] drm/i915: Move icl_get_trans_port_sync_config() into the DDI code Ville Syrjala
2020-03-18 22:44   ` Manasi Navare
2020-03-13 16:48 ` [Intel-gfx] [PATCH 05/13] drm/i915: Use REG_FIELD_PREP() & co. for TRANS_DDI_FUNC_CTL2 Ville Syrjala
2020-03-18 22:53   ` Manasi Navare
2020-03-13 16:48 ` [Intel-gfx] [PATCH 06/13] drm/i915: Include port sync state in the state dump Ville Syrjala
2020-03-18 23:00   ` Manasi Navare
2020-03-27 17:15     ` Ville Syrjälä
2020-03-13 16:48 ` [Intel-gfx] [PATCH 07/13] drm/i915: Store cpu_transcoder_mask in device info Ville Syrjala
2020-03-18 17:02   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2020-04-02  0:59     ` Souza, Jose
2020-03-13 16:48 ` [Intel-gfx] [PATCH 08/13] drm/i915: Implement port sync for SKL+ Ville Syrjala
2020-03-18 23:32   ` Manasi Navare
2020-03-13 16:48 ` [Intel-gfx] [PATCH 09/13] drm/i915: Eliminate port sync copy pasta Ville Syrjala
2020-04-02  1:25   ` Souza, Jose
2020-03-13 16:48 ` [Intel-gfx] [PATCH 10/13] drm/i915: Fix port sync code to work with >2 pipes Ville Syrjala
2020-04-03  0:32   ` Souza, Jose
2020-04-03 17:25     ` Ville Syrjälä
2020-03-13 16:48 ` [Intel-gfx] [PATCH 11/13] drm/i915: Do pipe updates after enables for everyone Ville Syrjala
2020-04-03  0:44   ` Souza, Jose [this message]
2020-03-13 16:48 ` [Intel-gfx] [PATCH 12/13] drm/i915: Pass atomic state to encoder hooks Ville Syrjala
2020-04-02  1:18   ` Souza, Jose
2020-03-13 16:48 ` [Intel-gfx] [PATCH 13/13] drm/i915: Move the port sync DP_TP_CTL stuff to the encoder hook Ville Syrjala
2020-04-03  0:59   ` Souza, Jose
2020-03-16 14:43 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Port sync for skl+ Patchwork
2020-03-18 18:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Port sync for skl+ (rev2) Patchwork
2020-03-18 18:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-18 21:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Port sync for skl+ (rev3) Patchwork
2020-03-18 22:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-19  0:19 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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